US20150091195A1 - Method of Packaging a Die - Google Patents

Method of Packaging a Die Download PDF

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Publication number
US20150091195A1
US20150091195A1 US14/563,661 US201414563661A US2015091195A1 US 20150091195 A1 US20150091195 A1 US 20150091195A1 US 201414563661 A US201414563661 A US 201414563661A US 2015091195 A1 US2015091195 A1 US 2015091195A1
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Prior art keywords
die
substrate
tape
solder balls
tape segment
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Abandoned
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US14/563,661
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Chee Chian Lim
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to US12/147,051 priority Critical patent/US8563357B2/en
Priority to US14/030,825 priority patent/US8907501B2/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US14/563,661 priority patent/US20150091195A1/en
Publication of US20150091195A1 publication Critical patent/US20150091195A1/en
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
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    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

Description

  • This is a continuation application of U.S. patent application Ser. No. 14/030,825, issued on Dec. 9, 2014 as U.S. Pat. No. 8,907,501, entitled “Method of Packaging a Die,” which was filed on Sep. 18, 2013 which is a divisional application of U.S. patent application Ser. No. 12/147,051, issued on Oct. 22, 2013 as U.S. Pat. No. 8,563,357, entitled “Method of Packaging a Die,” which was filed on Jun. 26, 2008, both of which are incorporated herein by reference.
  • BACKGROUND
  • One known type of die (that is a body, largely composed of semiconductor material, containing electronic circuitry formed therein and which is a fragment of a semiconductor wafer) has an array of electrical contacts on at least one of its major sides. The die is attached to a substrate (typically a circuit board) in the following steps. Firstly, an array of electrically conductive bumps (solder balls) are formed on the respective electrical contacts of the die, to form a flip chip. (Optionally, the solder balls are placed on the wafer before the wafer is singulated into individual dies, thereby forming the flip chips.)
  • The flip chip is then inverted and positioned with the solder balls on respective bond pads of the substrate, with a small space between the die and the substrate. The solder is then heated to cause re-flow, in which an electrical connection is produced between the balls and the respective bond pads of the substrate. An electrically-insulating adhesive (“underfill”) is then injected into the space and then cured. The underfill provides a strong mechanical connection between the die and substrate, and a heat bridge between them, and ensures the solder joints are not stressed in use due to differential heating of the chip and the rest of the system.
  • This process is relatively slow because it takes considerable time to fill the space between the die and the substrate. For example, this may take 4 to 5 minutes for a 6 mm die with a 3 mm gap. Since this step is performed individually for each substrate (e.g., each circuit board), it can cause a bottleneck in a process which produces a great many dies from each wafer. Furthermore, the separate curing procedure may take 1-4 hours. Furthermore, air bubbles may be trapped between the die and the substrate, creating “voids”. Also, a lateral force is applied to the solder balls during the insertion of the underfill layer which may displace them. This is expected to become an increasing problem in the future as the pitch of the die pads of the flip chip becomes increasingly fine.
  • The underfill material is typically a thermosetting material, so once the die and substrate are attached, they are hard to separate again. Choosing the underfill material is subject to conflicting requirements. If the material has high filler loading, it tends to flow slowly into the space between the die and the substrate. Conversely, if it has low filler loading, it becomes subject to “popcorning”. Furthermore, some suitable underfill materials have a relatively short floor life before their curing properties degrade. Also, if subsequent process steps expose the underfill layer to solvents, the solvents may cause voiding or bubbling within the cured underfill.
  • An alternative attachment procedure is to dispense the liquid underfill onto the bond pads before positioning the flip-chip onto it. That is, the flip-chip is moved towards the substrate, such that the solder balls push the adhesive out of their way, until the solder balls make contact with the respective bond pads of the substrate. Once the solder balls have contacted the respective bond pads of the substrate, a heat treatment process is performed to bond the solder balls to the bond pads and to cure the underfill.
  • Note that once the bond pads of the substrate are covered by the underfill, aligning the flip chip with them is less than straightforward. Although the alignment may be performed before the underfill material is dispensed, this alignment may degrade when the flip chip is moved towards the substrate, and there is a tendency for the die to “float” on the underfill material (that is for the resistance of the underfill to displace the flip chip from its correct position). Furthermore, underfill material may remain trapped between the solder balls and the bond pads, risking mechanical or electrical joint failure.
  • Furthermore, this alternative procedure shares many of the disadvantages of the first technique explained above. It is performed at a package level, so it is relatively slow. Also, it too is susceptible to voiding. Also, materials which would allow it to be performed reliably are not yet available. For example, the material should have a coefficient of thermal expansion (CTE) no higher than 80 ppm/K, to ensure that it is not damaged during the heat treatment process, and such materials are not readily available. Also, there is potential for moisture to be absorbed into the underfill, damaging it. Also, once the curing operation is concluded, the resulting package is not reworkable.
  • SUMMARY OF THE INVENTION
  • Embodiments of the present invention propose that a surface of a die is covered by a tape segment comprising a plurality of apertures corresponding to electrical contacts of the die. Conductive elements are inserted into the apertures, and bonded to the contacts. The die is located on a substrate with the conductive elements in register with die pads of the substrate, and the conductive elements are bonded to the die pads by a heat treatment.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • An embodiment of the invention will now be described, for the sake of example only, with reference to the following figures in which:
  • FIG. 1, which is composed of FIGS. 1( a) to 1(e), shows the steps of the an embodiment of the invention; and
  • FIG. 2 is a flow diagram of the steps of the embodiment.
  • DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • Referring firstly to FIG. 1, a method which is an embodiment of the invention is shown. The steps of the method are shown in FIG. 2. In FIG. 1( a), a die 10 (shown in side view) has a regular array of electrical contacts 11 on its major surface 12.
  • The major surface 12 of the die 10 is covered with a segment of tape 20 (shown in a cross-sectional side view) having a regular array of apertures (through-holes) 21 within it (step 61). Although in FIG. 1, for simplicity, only a single die 10 and tape segment 20 are shown separate, in fact, the tape segment 20 may be applied to the die 10 before the singulation process which separates multiple dies from a single wafer. For example, a tape can be applied to the wafer such that the tape extends over a plurality of portions of the wafer which are to be singulated into respective dies. Then the tape may be segmented (i.e., divided into tape segments 20) during the singulation of the wafer, so that there is one tape segment 20 attached to each respective die 10.
  • The tape is typically an elastomeric material which may comprise one or more of rubber, silica and resin. It has a thickness which is at least about 15 μm, and may be significantly more. It carries a first layer of adhesive on the side facing the die, for adhering each tape segment 20 to the respective die 10. As described in more detail below, it also comprises a second layer of adhesive on the side facing away from the die 10.
  • A view of the tape segment 20 facing one of its major surfaces is given in FIG. 1( b).
  • Subsequently, in FIG. 1( c), the tape segment 20 and die 10 are placed beneath a reservoir 30 which holds many solder balls 41. The reservoir 30 contains apertures 31 through which the solder balls 41 fall onto the surface of the tape 20 (step 62). The apertures 31 are aligned with the apertures 21. The balls 41 are slightly smaller than the holes 21, and come to rest inside respective holes 21.
  • A first heat treatment process (“die reflow”) is then performed, in which the solder balls 41 become bonded to the major surface 12 of the die 10 (step 63).
  • The die is then inverted, and placed onto a substrate 50 (which may be a printed circuit board, PCB), having an array of bond pads 51, as shown in FIG. 1( d) (step 64).
  • A second heat treatment process (“reflow”) is then performed in which the solder balls 41 are melted into discs filling the apertures 21, and in particular bonding the solder balls 41 to the bond pads 51 (step 65). The melting solder balls 41 are held in place by the tape segment 20, to give a high reliability solder joint. The second layer of adhesive (which may be the same kind of adhesive as used in the first layer, or a different kind of adhesive) on the surface of the tape segment 20 facing away from the die 10, adheres the tape segment 20 to a portion of the substrate 50 (e.g., to its bond pads 51 as shown in FIG. 1( e)).
  • The tape segment 20, which is not removed in use, makes it unnecessary to provide an underfill layer between the die 10 and the substrate 50. The tape segment 20 provides a heat bridge between the die 10 and the substrate 50, and stress relief when the structure of FIG. 1( e) is in use. The tape segment 20 will hold each solder ball firmly in directions parallel to the major face of the die 10. Due to the elasticity of the tape segment 20 it acts like many micro-springs, to enhance the reliability performance. The tape segment 20 re-enforces the solder balls' connection between the die pads and the PCB board pads, which reduces common solder ball cracking issues due to CTE (coefficient of thermal expansion) mismatch.
  • Since no underfill layer is required, the various problems associated with an underfill layer (e.g., under-cure and voiding) are eliminated. Furthermore, since there is no process of applying underfill, no lateral stress is applied to the solder balls. This is particularly important for fine pitch flip chips.
  • The thickness of the spacing between the die 10 and the substrate 50 is guaranteed by the thickness of the tape segment 20. That is, there is consistent “standoff”. Typically, the spacing of the contacts 11 and the bond pads 51 is substantially equal to the thickness of the tape segment 20. This is true even though the solder balls 41 substantially collapse due to the reflow process. The tape segment's thickness also acts as a Z-direction stress absorber for die stress relief after the solder reflow and in use.
  • Although only a single embodiment of the invention has been described in detail, many variations are possible within the scope of the invention as defined by the appended claims.
  • For example, as mentioned above the tape segments may be produced by applying a single tape to a wafer so that it extends over multiple portions which are to be singulated into dies, and then singulating the tape at the same time as the singulation of the wafer, to form respective tape segments attached to each die. However, in an alternative, the tape segments may be discrete and adhered individually to dies which have already been singulated.
  • Furthermore, although in the embodiments described, the tape segments are adhered to the die (or wafer) by adhesive, in some embodiments the tape may be attached by a heating process which partially melts the surface of the tape onto the die and/or wafer surface.
  • Similarly, in some embodiments the tape segments may be attached to the substrate at least partly by a heating process.
  • Although the die is shown above as having an array of only twelve electrical contacts, the number of contacts may be higher or lower.
  • Instead of the electrical contacts having a rectangular array, they may have any other such array, such as a hexagonal array. The die may also be a flip-chip of the kind which additionally has electrical contacts on a face facing away from the substrate, and which are intended to be wire-bonded (e.g., to further die pads on the substrate). The die may have any electronic functionality (e.g., it may be a memory, a micro-controller, etc).

Claims (1)

What is claimed is:
1. A system comprising:
a die comprising a plurality of electrical contacts;
a substrate having a plurality of bond pads;
a tape segment sandwiched between the die and the substrate, wherein the tape segment comprises an adhesive layer and a plurality of apertures, wherein the tape segment is directly disposed on the die; and
a plurality of conductive elements disposed in the plurality of apertures, each conductive element being respectively bonded to a corresponding one of the plurality of electrical contacts and the plurality of bond pads.
US14/563,661 2008-06-26 2014-12-08 Method of Packaging a Die Abandoned US20150091195A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/147,051 US8563357B2 (en) 2008-06-26 2008-06-26 Method of packaging a die
US14/030,825 US8907501B2 (en) 2008-06-26 2013-09-18 Method of packaging a die
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US8563357B2 (en) * 2008-06-26 2013-10-22 Infineon Technologies Ag Method of packaging a die
RU2463334C1 (en) * 2011-08-03 2012-10-10 Государственное унитарное предприятие "Институт нефтехимпереработки Республики Башкортостан" (ГУП "ИНХП РБ") Thermal destruction unit for processing oil residues
CN105097680B (en) 2014-05-16 2019-06-07 恩智浦美国有限公司 Protectiveness for integrated circuit device encapsulates
KR20160034717A (en) * 2014-09-22 2016-03-30 삼성전자주식회사 semiconductor package and manufacturing method thereof

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US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
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US8563357B2 (en) 2013-10-22

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