WO1997026585A1 - Dispositif d'affichage a cristaux liquides et procede de fabrication associe - Google Patents

Dispositif d'affichage a cristaux liquides et procede de fabrication associe Download PDF

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Publication number
WO1997026585A1
WO1997026585A1 PCT/JP1997/000062 JP9700062W WO9726585A1 WO 1997026585 A1 WO1997026585 A1 WO 1997026585A1 JP 9700062 W JP9700062 W JP 9700062W WO 9726585 A1 WO9726585 A1 WO 9726585A1
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Prior art keywords
film
insulating film
gate
liquid crystal
display device
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PCT/JP1997/000062
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English (en)
Japanese (ja)
Inventor
Kenichi Onisawa
Kikuo Ono
Toshiki Kaneko
Kenichi Chahara
Etsuko Nishimura
Katsunori Nakajima
Takeshi Satou
Kenichi Hashimoto
Tetsurou Minemura
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Hitachi, Ltd.
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Publication of WO1997026585A1 publication Critical patent/WO1997026585A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Liquid crystal display device and method of manufacturing the same
  • the present invention relates to an active matrix drive type liquid crystal display device using a thin film transistor (TFT) and a method of manufacturing the same.
  • TFT thin film transistor
  • a scanning signal line (gate line) is provided on an insulated transparent substrate, a gate insulating film is provided thereon, a semiconductor layer is provided thereon, and a semiconductor layer is provided above the semiconductor layer.
  • TFT structure in which a gate electrode is first formed on a substrate is generally called an inverted staggered structure. Japanese Patent Application Laid-Open No. 2-48639 is known as such a TFT.
  • Document 2 discloses a conductor structure containing Mo as a main component and containing at least 0.5 to 10 wt% of Cr. Further, in Japanese Patent Application Laid-Open No. 301822/1991 (hereinafter referred to as Reference 3), the third column 30 The line discloses a conductor structure in which Mo contains 15 to 85 atomic percent (25 to 91 wt%) with respect to Cr.
  • the liquid crystal display device using TFT has a feature that the contrast is high because active driving is possible.
  • the process of forming the TFT on the substrate is complicated, and requires at least six photolithographic steps. The reason is that the basic elements (membrane) that constitute TFT are scanning signal lines.
  • Gate line Gate insulating film, semiconductor layer, drain electrode (data line, same as normal source electrode), transparent pixel electrode, and protective green film. This is for patterning by photolithography.
  • the production cost of the TFT substrate is high due to the large investment amount of the production line and low throughput. If the TFT element structure is not devised, short-circuits between the electrodes, disconnection of the electrodes, etc. will occur, and the yield of the substrate will be reduced, resulting in an increase in cost. Specific examples of yield reduction include gate lines, data lines, shorts between data lines and transparent pixel electrodes, and gaps formed by gate lines (through gate insulating films). ) Disconnection of the data line, disconnection of the transparent pixel electrode at the step of the source electrode, and poor electrical contact between the source electrode and the transparent pixel electrode. It is necessary to eliminate these factors when manufacturing TFT.
  • an interlayer insulating film (referred to as a protective insulating film in the present invention) is provided on the source and drain electrodes of a TFT.
  • a structure has been proposed in which the source and drain electrodes and the transparent pixel electrode are connected through an opening provided in the film. According to this method, the source and drain electrodes and the transparent pixel electrode can be made into different layers via an insulating film, so that they occur when they are on the same plane. It is possible to prevent a short circuit between the two electrodes, which is easily caused.
  • a method for simplifying the process is not taken into consideration, and the above-mentioned measures for disconnection of the transparent pixel electrode and contact failure are insufficient, so that the manufacturing cost cannot be reduced.
  • a gate insulating film and a semiconductor layer, and a metal film serving as a drain electrode and a source electrode are continuously formed, and the semiconductor layer is processed using a mask of the metal film.
  • a method of forming a transparent electrode has been proposed in Japanese Patent Application Laid-Open No. 61-16764.
  • the source electrode remains in an eaves shape, and the transparent electrode is disconnected due to the step. The problem of being easy remains. That is, the yield at the time of manufacturing is not sufficiently considered.
  • An object of the present invention is to provide a liquid crystal display device having a small number of manufacturing steps and a method for manufacturing the same.
  • Another object of the present invention is to provide a liquid crystal display device which is less likely to be disconnected and has a high production yield, and a method of manufacturing the same.
  • Still another object of the present invention is to provide an active matrix type liquid crystal display device capable of obtaining a bright display screen. Disclosure of the invention
  • a plurality of gate lines are provided on one substrate of the liquid crystal display device of the present invention.
  • a plurality of data lines formed so as to intersect the plurality of gate lines, a plurality of thin film transistors formed near intersections of the plurality of gate lines and the plurality of data lines, It has a plurality of pixel electrodes connected to each of the plurality of thin film transistors.
  • a gate insulating film is formed on the plurality of gate lines, and a plurality of data lines are formed on the gate insulating film.
  • a protective insulating film is formed on the gate insulating film, the plurality of data lines, and the plurality of thin film transistors. Each corresponding pixel electrode is connected to each source electrode of the plurality of thin film transistors via an opening formed in the protective insulating film.
  • the peripheral end portions of the gate insulating film and the protective insulating film have the same planar shape.
  • the gate insulating film and the protective insulating film are simultaneously etched with the same photomask pattern.
  • the source electrodes of the plurality of thin film transistors are preferably metal films mainly composed of crystal particles having a particle diameter of 200 nm or more.
  • the source electrodes of the plurality of thin film transistors are composed of an alloy film containing Cr and Mo having a Mo composition of not less than 20 wt% and not more than 55 wt%.
  • the protective insulating film and the gate insulating film are dry-etched with one photomask pattern so that they have the same planar shape. That is, the number of hot masks can be reduced by one. However, if such a means is adopted, when etching is performed continuously, After the upper protective insulating film is etched around the transparent insulating substrate, the drain line below the opening in the protective insulating film, and the metal forming the source electrode, until the gate insulating film is completely etched. The film must remain exposed to the etching plasma.
  • the metal film forming the data line and the source electrode is not etched by 1 nm or more. This is derived from various experiments using different materials, and corresponds to the fact that the film thickness was not substantially reduced by the measurement using a surface roughness meter, and there was almost no surface roughness or deterioration. are doing.
  • materials that do not satisfy the above conditions for example, in the case of alloys mainly composed of Ta, Mo, or W, the surface exposed to the etching plasma was observed with a scanning electron microscope (SEM). It was found that the projections that seemed to correspond to the world existed at high density. For this reason, it is presumed that the contact with the transparent pixel electrode formed on this surface becomes worse.
  • the data line and the source electrode are made of a metal film.
  • the metal film contains crystal particles having a particle diameter of 200 nm or more, the data line gets over the step of the base. Resistance and disconnection I found nothing.
  • the base step is a gap in the gate insulating film caused by the step of the gate line.
  • one data line usually has about 480 to 1200 gates. You have to get over the bridge without breaking the step.
  • the step of the gate line is small or the step is tapered so as to expand, the data line is relatively hard to break. And the formation of the taper complicates the process and reduces production efficiency. According to the present invention, disconnection does not occur at the crossing portion of the data line without applying any special processing to the gateway.
  • the first factor is that the data line has excellent surmounting properties. This is because, when used in a pattern, a divergent taper is formed even by a normal jet etching process. According to measurements, the angle was 70-80 degrees. Here, a range of 100 to 350 nm is appropriate as the thickness of the gate line. When the thickness is 350 nm or more, not only is taper processing necessary, but also it takes a long time to deposit and etch the film, which lowers the production efficiency. Therefore, application to a liquid crystal display device is not preferable.
  • An alloy of two elements and Cr has been found to be suitable.
  • the data line and the source electrode are composed of an alloy film of Cr and Mo and the composition of Mo in the alloy film is not less than 20 wt% and not more than 55 wt%.
  • the transparent pixel electrode at the opening of the protective insulating film It was confirmed that there was no contact failure with, and no disconnection at the step of the base. The reason why the optimum composition range is limited to 20 to 55 wt% will be clarified in Examples described later.
  • the protective insulating film and the gate insulating film can be dry-etched with one hot mask pattern, and it goes without saying that the number of hot masks can be reduced.
  • the alloy film of at least one selected element and Cr can also be easily reduced to a specific resistance of 22 ⁇ or less, so that it can be applied to gate lines that require low resistance.
  • the film stress of the data line and the source electrode is not less than 120 OMPa and not more than 50 OMPa.
  • the stress in this range it is possible to almost completely suppress disconnection and a rise in resistance at the step portion of the base.
  • specific contactor sheet resistance of the source electrode and the pixel electrode to be a 1 X 1 0 s ⁇ ⁇ m 2 or less, the contribution to the resolution of contactors Bok failure problems with source Ichisu electrode and the pixel electrode it can.
  • the surface roughness of the source electrode surface and the data line surface in the opening formed in the protective insulating film is almost the same. I do.
  • the problem of the contact failure between the source electrode and the pixel electrode can be almost completely solved.
  • Another object of the present invention is to provide an active matrix type liquid crystal display device which can provide a bright display screen.
  • the line width is reduced, in addition to the disconnection at the ground difference part,
  • the disconnection at the stepped portion does not easily occur, and the adhesiveness with the register is sufficient.
  • the aperture ratio can be improved.
  • the wet etching method is a processing method having advantages such as low equipment cost and high throughput, which are advantageous for productivity.
  • the semiconductor layer below the end of the source metal electrode is formed wider than the source metal electrode, even if the semiconductor film is etched using the metal film of the source electrode as a mask, Since the ends of the electrodes do not become eaves with respect to the semiconductor layer, the production yield can be improved while simplifying the production process without breaking the transparent electrode.
  • a light-shielding electrode is formed near and below the data line, and the contour of the transparent pixel electrode is on the light-shielding electrode and on the gate line, so that the aperture ratio is large and the screen is bright.
  • the manufacture of liquid crystal display devices includes the steps of etching the gate electrode film, etching the semiconductor layer and the data lines and source metal electrodes on the semiconductor layer, selectively etching the semiconductor layer, protective insulating film and gate insulating film. using the same mask film, CF 4 and ⁇ 2 or SF B and 0 etching step with 2 mixed gas, because due to simplified manufacturing process by 5 Tsunoho Bok mask process step of etching the transparent pixel electrode liquid crystal display device Cost can be reduced.
  • At least one element selected from Nb, Ta, and W is used as a target material.
  • a film is deposited by a DC magnetron sputtering method using an alloy with Cr, and the sputtering conditions are adjusted to contain a crystal particle having a crystal grain size of 200 nm or more, and the film stress is reduced to ⁇ 200.
  • an alloy of Cr and Mo having a Mo composition of not less than 20 wt% and not more than 55 wt% is used as a target material, and a DC magnetron is used.
  • Deposition is also possible by depositing a film by sputtering and adjusting the sputtering conditions so that the film stress is not less than 200 Mpa and not more than 500 Mpa. This can prevent disconnection of the components and improve the production yield.
  • the i-type semiconductor layer is selectively etched on the gate insulating film with a different mask pattern.
  • the semiconductor layer below the extreme portion is formed wider than the source metal electrode, and the end of the metal film does not become eaves with respect to the semiconductor layer. Therefore, the production yield is improved while simplifying the production process without disconnection of the transparent electrode.
  • FIG. 1 is a plan pattern diagram of one pixel of the TFT substrate of the present invention and each layer in the peripheral portion thereof.
  • FIG. 2 is a sectional view taken along line 2-2 of the liquid crystal display panel shown in FIG.
  • FIG. 3 is a sectional view taken along line 3-3 of the liquid crystal display panel shown in FIG.
  • FIG. 4 is a diagram showing the results of contact evaluation of various metal films with the ITO film.
  • FIG. 5 is a diagram showing the relationship between the Mo composition of the Cr—Mo alloy film and the specific resistance.
  • FIG. 6 is a graph showing the relationship between the Mo composition of the Cr—Mo alloy film and the etching rate.
  • FIG. 7 is a diagram showing the evaluation results of the resistance over the power of various metal films.
  • FIG. 8 is a graph showing the relationship between the Mo composition of the Cr-Mo gold-containing film and the over-ride resistance ratio.
  • FIG. 9 is a diagram showing the relationship between the Mo composition and the film stress of the Cr—Mo alloy film.
  • FIG. 10 is a schematic view of the surface and cross-sectional structure of the alloy film according to the present invention.
  • FIG. 11 is a schematic view of the surface and cross-sectional structure of an alloy film according to the prior art.
  • FIG. 12 is a plan view showing the vicinity of the connection between the gate terminal GTM and the gate wiring GL.
  • FIG. 13 is a cross-sectional view showing the vicinity of the connection between the gate terminal GTM and the gate wiring GL.
  • FIG. 14 is a plan view showing the vicinity of the connection between the drain terminal DTM and the data wiring DL.
  • FIG. 15 is a cross-sectional view showing the vicinity of the connection between the drain terminal DTM and the data wiring DL.
  • FIG. 16 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.
  • FIG. 17 is a flowchart showing a method of manufacturing the TFT substrate TFTSUB of the liquid crystal display device of the present invention.
  • FIG. 18 is a sectional view corresponding to the flowchart of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a diagram showing a plane pattern of each layer constituting the TFT substrate TFTSUB, showing one pixel and a peripheral area.
  • FIG. 2 is a cross-sectional view taken along the line 2-2 in FIG. 1
  • FIG. 3 is a cross-sectional view taken along the line 3-3 in FIG.
  • the display panel has a thin film transistor, a transparent conductive film ITO (Indium Tin Oxide; short for Indium Tin Oxide) 1, and various wirings formed on one surface of the transparent glass substrate SUB 1.
  • An image signal voltage is applied between the transparent conductive film ITO] and the common electrode ITO 2 to control the electro-optical state of the liquid crystal layer LC between the two electrodes, thereby changing the light transmission state of this portion of the display panel. And display a predetermined image.
  • a back light is installed on the opposite substrate side of the liquid product panel (PSUB side) or on the TFT substrate side (TFTSUB side), and the light transmitted through the screen of the liquid crystal panel is observed from the side opposite to the back light.
  • a plurality of parallel gate lines (scanning signal lines or horizontal signal lines) GL and a plurality of parallel data lines (video signal lines or vertical lines) formed so as to intersect the gate lines Signal line) DL is provided on the surface of the TFT substrate.
  • a region surrounded by two adjacent gate lines GL and two adjacent data lines DL is a pixel region.
  • a transparent conductive film IT ⁇ 1 is formed on almost the entire surface. In addition, this area
  • the thin-film transistor as a switching element corresponds to the convex portion of the gate line (the upwardly convex portion in FIG. 1) corresponding to each pixel electrode.
  • the source lightning pole SD 1 is formed and connected to the pixel electrode.
  • the scanning voltage applied to the gate line GL is applied to the gate electrode of TF ⁇ ⁇ ⁇ ⁇ , which is a part of the gate line, so that TF ⁇ ⁇ ⁇ is in the ⁇ ⁇ state. At this time, it is supplied to the data line DL.
  • the resulting image signal is written to the transparent conductive film I 01 via the source electrode SD 1.
  • a gate line GL composed of a conductive film g1 is formed on a transparent glass substrate S1 and an insulating film, a semiconductor layer, and the like are formed thereon as described later.
  • a thin film transistor TFT is formed.
  • the thin-film transistor reduces the channel resistance between the source drain (data line DL) and increases the channel resistance when the bias voltage is reduced to zero.
  • a gate insulating film G1 made of silicon nitride is provided on a gate electrode which is a part of the gate line GL, and an i-type semiconductor made of an amorphous silicon to which no impurity is intentionally added is provided thereon.
  • a layer AS and an N-type semiconductor layer d0 made of amorphous silicon doped with impurities are formed.
  • This i-type semiconductor layer AS constitutes the active layer of the thin film transistor.
  • a source electrode SD 1 and a drain electrode (a part of the data line DL constitutes a drain electrode in the embodiment. In the following description, the drain electrode is referred to as a data line DL unless otherwise specified).
  • a thin film transistor is referred to as a data line DL unless otherwise specified.
  • the gate insulating film GI for example, a silicon nitride film formed by plasma CVD is selected and has a thickness of 200 to 500 nm (in this embodiment, (About 350 nm) is formed.
  • the i-type semiconductor layer AS is formed with a thickness of 50 to 250 nm (about 200 nm in this embodiment).
  • the N-type semiconductor layer d O is formed to be thin with a thickness of 50 nm or less, and is provided for forming a homogeneous contact between the i-type semiconductor layer AS and the source and drain electrodes, It is formed of an amorphous silicon semiconductor doped with P).
  • the names of the source electrode and the drain electrode are originally determined by the polarity of the bias between them.
  • the source electrode and the drain electrode are switched because their polarities are inverted during operation.
  • one is fixed with the source electrode and the other is fixed with the drain electrode.
  • the source electrode S D1 is formed on the N-type semiconductor layer d0, and is constituted by the first conductive film d1.
  • the first conductive film d1 is formed of a metal film having a thickness of 60 to 300 nm (about 200 nm in this embodiment).
  • the pixel electrodes are each formed of a transparent conductive film ITO1 such as indium tin oxide which is the second conductive film d2. It is connected to the source electrode S D1 of the thin film transistor.
  • the transparent conductive film I T01 is formed by a sputtering film of I T0, and has a thickness of 30 to 300 nm (about 140 nm in this embodiment).
  • the source electrode SD 1 is formed on the i-type semiconductor layer AS and the N-type semiconductor layer d 0 formed on the inner side of one pixel region.
  • i-type semiconductor layer AS Is processed wider than the source electrode SD 1.
  • the transparent conductive layer IT01 composed of the second conductive film d2 on the upper side is connected to the source electrode SD1 through an opening CN (hereinafter also referred to as a contact hole) opened in the protective insulating film PSV1. It is connected and formed on the protective insulating film PSV1.
  • the second conductive film d 2 does not break at the step of the first conductive film d 1, which is the lower source electrode SD 1, and its level difference is maintained. Can be successfully overcome. This will be described in more detail later in the manufacturing method. In particular, such an effect becomes remarkable when ITO is used as the second conductive film d 2 as in the present embodiment.
  • ITO which is polycrystalline, has a different etching rate between the crystal grain boundaries and the crystal grains, and the grain boundaries are fast. Therefore, when the cross section of the lower portion of the second conductive film d2 is not processed into a good shape, a grain boundary where etching proceeds more easily occurs on the lower step, and the portion is easily disconnected from that portion in the etching process. .
  • the opening CN is formed in the protective insulating film PSV1
  • the surface of the source electrode SD1 thereunder is formed by terminals around the transparent glass substrate SUB1.
  • the gate insulating film G 1 is exposed to the etching gas plasma until the etching is completed. Therefore, as the source electrode material, CF 4 and ⁇ 2 of the protective insulating film and the gate insulating film are used. Others are required which do not cause the film thickness decreases and deterioration due to etching in the etching process with a mixed gas of S P 't and ⁇ 2.
  • the dry etching rate for gas is rGI
  • the etching time is set slightly longer in consideration of the in-plane distribution.
  • the gate insulating film etching time was set to 1.5 times of tEGI.
  • the thickness d DI of the source electrode S Di is
  • the relationship can be led.
  • the materials used were pure Cr, Cr-Cr alloy with composition changed and Mo added, ⁇ 1> -13 alloy, Cr-Ta alloy, ⁇ 1 "- ⁇ / alloy, Mo-Ta alloy, pure Mo, pure W.
  • These metal films are deposited by DC magnetron sputtering at a substrate temperature of 200 ° C to a thickness of 200 nm and Etching was performed on the triangular electrode pattern, and then a 350 nm thick SiON insulating film was deposited thereon by a CVD method, and a through-hole photo resist was formed on the SiON insulating film.
  • a double circle is contactor sheet resistance 1 X 1 ( ⁇ ⁇ ' ⁇ ⁇ 2 or less, ⁇ is 1 X 1 0 7 ⁇ ⁇ ⁇ ⁇ 2 or less, delta is 1 X 1 0 8 ⁇ . ⁇ m 2 or less, X is 1 X 1 0 shows a more 8 ⁇ ⁇ ⁇ m z.
  • the contactor Bok resistive film thickness reduction amount by the gong I etched from the table that it more 2 0 nm is 1 X 1 ⁇ ' ⁇ ⁇ ⁇ ⁇ 2 or more, which indicates that the electrical contact between the metal film and the ITO film is deteriorated, where 1 X 1 ( ⁇ ⁇ ⁇ ⁇ m 2 does not cause point defects.
  • 1 X 1 ( ⁇ ⁇ ⁇ ⁇ m 2 does not cause point defects.
  • N b, M 0, T a the one at least selected from W element and the C r Gold satisfies this condition
  • the surface of the metal film with a large decrease in film thickness was observed by SEM, the formation of very high-density fine projections was observed. is assumed to be an oxide that existed. Therefore, in the alloy of the contactor I believed to deteriorate. the present invention with the ITO film deposited thereon, CF 4 and 0 2 or SF is long it ® ⁇ with a mixed gas of B and 0 2 in the etching plasma, projections thickness reduction and surface as described above No change such as formation was observed. In other words, the surface roughness of the source electrode surface in the opening formed in the protective insulating film and the surface of the data line formed of the same material are almost equal.
  • the gate line GL is formed of a single-layer conductive film g1.
  • a gold film formed by a DC magnetron sputtering method and having a thickness of 6 Onm or more (about 200 nm in this embodiment) is used.
  • this material include Nb, Mo, Ta, W, and other high melting point gold alloys or alloys between them, or alloys mainly containing A] or A1, or Cu or Cu as a main component. Alloys etc. can be applied.
  • the substrate is glass and there is no overcoming of the difference, there is no strong requirement for the film stress as described later. However, in order to prevent disconnection of the data line and increase in resistance, it is better to form a divergent taper at the end of the wiring.
  • the result of examining the relationship between the M 0 composition of the Cr—Mo alloy and the specific resistance will be described.
  • a method was adopted in which a Mo chip was placed on a Cr target or a Cr chip was placed on a predetermined area (the alloy composition was controlled by the area ratio) on a M0 target. .
  • the Mo composition was determined by chemically analyzing the prepared film. The results obtained are shown in FIG.
  • the sputtering conditions were kept constant. That is, the substrate temperature is 100 °, the pressure is 0.2 Pa, and so on.
  • the thickness was 500 W and the thickness was 200 nm.
  • the etching rate was examined.
  • As the etching solution a 15 wt% aqueous second ammonium ammonium nitrate solution maintained at a temperature of 30 ° C. was used. The results obtained are shown in FIG. From this figure, it can be seen that the etching rate decreases as the amount of Mo added to Cr increases, and reaches a minimum value at about 75 wt% Mo. If the etching rate is too low, the throughput of the etching step is reduced, which is not preferable. From this, it is determined that the upper limit of the amount of M 0 added to Cr is about 55 wt%. In this case, the etching rate is approximately 1 nmZs, which is a value that does not cause any problem in production.
  • the lower the specific resistance of the gate line material the more the signal delay can be suppressed, which is advantageous.
  • a sheet resistance of about 0.6 ⁇ / ⁇ is sufficient. found.
  • the upper limit is set at 35 O nm. Considering these conditions and an appropriate process margin, a specific resistance of about 22 ⁇ cm or less is sufficient. The Cr-M0 alloy satisfies this condition.
  • the resistivity of an alloy thin film of at least one element selected from Nb, Ta, and W and Cr is reduced by adjusting the composition and optimizing the sputtering conditions. Under these conditions, a low resistance of 22 ⁇ Qcm or less can be achieved.
  • the data line DL is formed on the gate insulating film GI on the transparent glass substrate SUB1, the i-type semiconductor layer AS and the n-type semiconductor layer d0 on the gate insulating film GI.
  • the i-type semiconductor layer AS, the N-type semiconductor layer d0, and the first conductive film d1 have a laminated structure having substantially the same plane pattern.
  • the substantially same plane pattern is a feature for processing the i-type semiconductor layer AS in this portion using the first conductive film d1 of the data line DL as a mask, as will be described in a later manufacturing method.
  • the first conductive film d 1 mainly contributes to electric conduction and transmits a signal. Further, as is clear from the figure, the data line DL and the source electrode SD1 can be formed of the same material (the same is applied in this embodiment).
  • the data line DL is formed by the gate insulating film GI, the i-type semiconductor layer AS, and the N-type semiconductor layer d0 due to the pattern edge of the gate line GL. It is necessary to get over the gap without breaking the wire or increasing the resistance. In order to satisfy this requirement, the stress of the source and data line thin film needs to be not less than ⁇ 20 OM Pa and not more than 500 Pa, and preferably the stress value is almost zero. Turned out to be good. Moreover, it has been found that it is essential that the source and data line metal thin films contain crystal particles having a particle size of 200 nm or more.
  • Typical experimental results showing this fact are shown below.
  • a 200 nm thick Cr film was deposited on a glass substrate by DC magnetron sputtering at a substrate temperature of 200 ° C, and then ordinary photolithography and jet etching were performed.
  • a gate Cr pattern without taper
  • a 350-nm thick SiN insulating film and a 150-nm thick a-Si semiconductor were successively stacked on top of each other.
  • Various metal films were deposited under the same conditions as described above to form a stripe pattern that intersects and intersects directly with the gate Cr pattern. Since the gate Cr pattern is not tapered, disconnection and increase in resistance are likely to occur, making it possible to clarify differences between samples.
  • the film / force is evaluated by a general method obtained by depositing various kinds of metal films on the Si wafer under the same sputtering conditions as the above-described strip-like pattern, and obtaining the warpage of the Si wafer. did.
  • a plus sign indicates that the stress is tensile, and a minus sign indicates that the stress is compressive.
  • the resistance to overcoming can be suppressed low by reducing the film stress. Since it is required that the overriding resistance ratio be less than 1.2, the film stress must be less than ⁇ 100 MPa. Also, in the case of tensile stress, at the same sputtering pressure, the larger the (average) atomic weight of the material, the lower the film stress, and for the same material, the lower the sputtering pressure, the lower the film stress. In the case of pressure stress, the stress increases in the same way. According to the present invention, the composition of the alloy of at least one element selected from Nb, Mo, Ta, and W with Cr is adjusted, and the sputtering conditions are optimized. And it was confirmed that the condition was satisfied.
  • the Cr-Mo alloy system was examined in more detail.
  • a stepless underlayer made of a tapeless gate Cr pattern and a laminated film of a SiN insulating film and an a-Si semiconductor film is formed, and the composition is formed thereon.
  • a modified Cr-Mo alloy film was deposited.
  • the sputtering conditions were the same as described above, but the pressure was 0.2 Pa.
  • a strip-shaped pattern that crosses at right angles to the gate Cr and the turn was prepared, and the crossing resistance ratio was measured. The results obtained are shown in FIG. From this figure, it can be seen that in order to reduce the riding resistance ratio to 1.2 or less, the Mo composition is preferably 30 to 80 wt%.
  • FIG. 9 shows the relationship between the Mo composition and the film stress.
  • the overriding resistance ratio was 1.2 when the film stress was in the range of ⁇ 200 to 150 MPa. I was able to keep it below. That is, this experiment It is determined that the lower limit of the Mo composition of the Cr-Mo alloy is 2 O wt%.
  • a TFT substrate was manufactured using a manufacturing process according to the present invention described later. Here, for comparison, 10 types of each of the following four types were manufactured.
  • each of the rice grains constituting the grains is a crystal grain, and the interface between the grains is called a grain boundary. Actually, there is almost no gap between the crystal grains and it is dense.)
  • the diameter of each crystal grain is the crystal grain size (simply called grain size). If the particle shape is an ellipse consisting of a major axis and a minor axis as shown in this figure, it is represented by the average value.
  • the right figure in Fig. 1i shows the thin film cut along with the glass substrate and observed from the cross-sectional direction.
  • FIG. 10 shows the film of the present invention, which is composed of: (a) a block region (domain) of 200 to 500 nm ) Is recognized.
  • each element of 50 to 100 nm is called a sub-grain, and the crystal orientation between adjacent particles is almost the same. Therefore, a lump region with a size of 200 to 500 nm, which is a merging of these sub-crystal grains, behaves as one crystal grain.
  • the crystal grain size is not in the minimum unit of 50 to 100 nm but in the range of 200 to 500 nm.
  • the cut surface of the film was torn, and the film was soft, in other words, excellent in ductility.
  • the alloy film of the present invention has an excellent property of climbing over the step portion of the base.
  • the specific resistance is low because the film is a dense film with few crystal grain boundaries.
  • the effect of the present invention is due to the fact that the crystal size is approximately 20 O nm or more. It was found that the particles were contained (effective if at least one particle was present on the film surface within 1 ⁇ m square).
  • the other films as shown in Fig.
  • the product grain size was as small as 50 nm or less, and the grain boundaries were clearly recognized in the cross section. Therefore, it is judged that small crystal grains are relatively coarsely filled and the ductility is small except for the film of the present invention. Therefore, it is understood that low-density crystal grain boundaries are likely to be formed in the stepped portion of the underlayer, and that the etching (penetration of the etching liquid) is also likely to proceed in that portion, resulting in disconnection.
  • the reason why large crystal grains of 200 nm or more are generated in the alloy film of the present invention is considered to be because the energy of the particles reaching the substrate by sputtering is large and the melting point of the alloy itself is relatively low.
  • Elements with higher atomic weights give more energy to the film growth surface when colliding with the film surface.
  • alloy an element having a large atomic weight having such an effect is added to Cr.
  • the melting point of each element is ⁇ 1 "is 1875 ° C (Cr-50 wt% M0 is about 20000 ° C)
  • Ta force is 2996 ° C
  • Mo is Under the same heating conditions, the lower the melting point, the faster the movement of the atoms is, and the larger the grain size, the larger the grain size.
  • the film surface grows while being hit by a particle having a large atomic weight (Peening Effect), so that a compressive stress is applied to the film and the tensile stress is lower than Cr. It is presumed to disappear.
  • the storage capacitance C add is different from the gate line GL on which the TFT is formed.
  • the gate line GL in the previous stage is intersected with the transparent conductive film sandwiching the laminated film of the gate insulating film GI and the protective insulating film PSV 1] TO 1 It consists of the capacity of the area.
  • the storage capacitor C add has a function of preventing the capacitance of the liquid crystal layer LC from attenuating and preventing a voltage drop when the TFT is turned off.
  • the parasitic capacitance C gs is the intersection area of the gate line GL, which is the gate line GL on which the TFs are formed, and the transparent conductive film ITO 1 across the laminated film of the gate insulating film GI and the protective insulating film PSV 1. It consists of capacity. Further, as shown in FIG. 2, C add and C gs are set such that the second conductive film d 2 is at a predetermined interval on the gate line GL.
  • the gap between the gate line GL and the transparent conductive film IT 01 is opposed to the structure in which the gate line GL of the own stage and the second conductive film d 2 are not overlapped. There is no need to cover with the black matrix formed on the substrate 0 PSU 1, and the aperture ratio is improved.
  • the light-shielding electrode SKD is formed by a conductive film g1 constituting a gate line GL on a transparent glass substrate SUB1 of a TFT substrate TFTSUB.
  • the light-shielding electrode SKD overlaps with the transparent conductive film IT01 along the data line DL as shown in FIG. 1 in plan view, and is formed so as to cover the lower part of the data line DL.
  • the light-shielding electrode SKD is insulated and separated by the data line DL, the gate insulating film GI, the i-type semiconductor layer AS, and the N-type semiconductor layer d0. Therefore, the possibility that the light-shielding electrode SKD and the data line DL are short-circuited is small.
  • the transparent conductive film ITO 1 and the light-shielding electrode SKD are insulated and separated by the gate insulating film GI and the protective insulating film PSV1.
  • the light-shielding electrode SKD has a function of improving the area of the transmission part of the pixel electrode with respect to the area of one pixel, that is, the aperture ratio, and improving the brightness of the display panel.
  • the backlight is set on one side of the TFT SUB having the TFT substrate SUB 1. You. In the following, for convenience, a case where the backlight is irradiated from the TFT substrate SUB 1 and observed from the counter substrate ⁇ PSUB side is shown.
  • the irradiation light passes through the glass substrate SU-1 of the opposite substrate, and enters the liquid crystal layer LC from a portion where the wiring lines formed by sputtering on one surface of the glass substrate SU-1 are not formed.
  • This light is controlled by the voltage applied between the transparent common electrode I ⁇ O2 formed on the opposite substrate and the transparent conductive film I ⁇ Oi formed on the TF ⁇ substrate.
  • 0 PSU 13 requires a wide range of black matrix BM. Without this, light leakage that is not controlled by voltage passes through the gap between the data line DL or the gate line GL and the transparent conductive film IT01, and the display controller Trajectory drops.
  • the TFTSUB is laminated with the liquid crystal in between, and it is necessary to increase the size of the alignment margin, and the aperture ratio is smaller than in this embodiment in which the light shielding electrode structure is formed only on the FT substrate.
  • the light shielding electrode SKD and the gate line GL reflect the backlight once, return the light to the light guide plate in the backlight, and reflect and transmit the light again to the opening.
  • the screen becomes brighter than the aperture ratio.
  • the light-shielding electrode SKD is located below the data line DL. If it is not formed further below the semiconductor layer, the reflectivity decreases and the screen becomes darker.
  • the semiconductor below the data line DL is processed using the data line DL as a mask, the first conductive film d 1 of the data line is used.
  • the combination of the light-shielding electrode SKD and the data line D has an effect of reducing the screen size.
  • the newly obtained effect ⁇ Protective film >>
  • the surface of the TFT substrate TFTSUB on which the thin film transistor FT is formed has a contact hole C ⁇ ′ for connecting the source electrode SD 1 and the pixel electrode, and a TFT as described later. Except for the gate terminal and drain terminal provided on the periphery of the substrate, it is covered with the protective film PSV 1 ⁇ Gate terminal GTM >>
  • Figure 12 is a plan view of the part from the end of the gate line GL on the TFT substrate to the gate terminal GTM, which is the connection part to the external drive circuit, and Figure 13 is 5 in Figure 12 —
  • Fig. 5 is a ffi diagram at the section line 5.
  • the gate terminal GTM is made of the second conductive film d2, and the second conductive film d2 is exposed to the outside.
  • the transparent conductive film of the gate terminal GTM is formed at the same time as the transparent conductive film T O1 constituting the pixel electrode and the data line.
  • the second conductive film d2 has a larger pattern than the conductive film g1. This is to prevent the infiltration of chemicals, moisture, etc., and the corrosion of the conductive film g 1 made of the Cr alloy.
  • the portion exposed to the outside except for the protective film PSV 1 is only the transparent conductive film IT 01.
  • I T0 is an oxide, which is remarkably resistant to the oxidizing reactions that cause corrosion, and therefore this structure has high yield and high reliability.
  • the lower layer film between the gate insulating film GI and the protective film PSV 1 is etched at the boundary between the gate terminal GTM and the contact hole CN. I have. That is, in this portion, the gate insulating film GI and the protective film PSV 1 are etched into the same planar shape. This is a game This is because the edge film GI and the protective film PSV1 are patterned using the same photomask. For this reason, a conductive film g1 that is not as strong as the above-described source electrode SD1 must be resistant to etching of the protective film. In addition, the conductive film g1 and the transparent conductive film IT01 need to have good contact characteristics.
  • FIG. 14 is a plan view of a portion from the vicinity of the end of the data line DL on the TT substrate to the drain terminal DTM which is a connection portion with an external drive circuit, and FIG. It is sectional drawing in the 7-7 cutting line of a figure.
  • the drain terminal DTM is formed of the transparent electrode d2 for the same reason as in the case of the gate terminal GTM described above.
  • the protective film PSV 1 is removed together with the gate insulating film G 1 to have the same plane shape in order to connect to an external circuit.
  • the second conductive film d2 is formed in a wider pattern than the first conductive film d1.
  • FIG. 15 which is a cross-sectional structure
  • the i-type semiconductor layer AS is formed wider at the end of the data line DL than the data line DL, similarly to the above-described source electrode SD 1. Accordingly, the structure is such that the disconnection of the transparent conductive film IT # 1 at the step of the data line DL is reduced.
  • the contact hole CN portion is a single layer of the protective film PSV 1 similarly to the contact hole CN in the display portion of FIG. 3, and the data line DL thereunder is provided.
  • the protective film must be resistant to etching.
  • the data line DL needs to have good contact characteristics with the transparent conductive film IT 01, similarly to the source electrode SD 1.
  • FIG. 16 is a plan view showing a schematic structure around a display panel.
  • a plurality of gate terminals G T M are arranged side by side corresponding to each gate line to form a gate terminal group T g.
  • a plurality of drain terminals DTM are arranged side by side corresponding to each data tine, and constitute a drain terminal group Td.
  • IN J in FIG. 16 is a portion where the seal pattern SL for bonding the opposite substrate SU 132 is not provided, and after the two substrates are bonded, the liquid crystal is sealed therein.
  • red, green, and blue color filters FIL, protective film PSV2, common electrode ITO2, and orientation film 0PR12 are sequentially laminated. It is provided. Further, a polarizing plate P ⁇ L2 is laminated on the other surface of the transparent glass substrate SUB2, and the polarizing plate on the other surface of the TFT substrate TFTSUB on which the TFT is not formed.
  • the black matrix light shielding film BM is not formed on the glass substrate SUB 2 in the same figure. Actually, the area of the TFT shown in FIG. It is formed of a Cr sputtering film, a laminated layer of Cr oxide and Cr, or a resin material. ⁇ TFT substrate TFTSUB manufacturing method ⁇
  • FIGS. 1A and 1B and FIGS. Fig. 17 summarizes the flow of the manufacturing process as a flowchart using the names of each process.
  • Each process is They are grouped in sub-units and marked with (A), (B), (C), etc.
  • the cross-sectional structure in each of the sub-steps ( ⁇ ⁇ ) to (F) is shown in FIG.
  • the cross-sectional structure excluding the step (B) is the cross-sectional structure immediately after the thin film is etched in each step.
  • the photo resist used as a mask is placed on the thin film on each cross-section. Left unpeeled.
  • FIG. 18 The corresponding cross-sectional structure in the final step of FIG. 18 is FIG.
  • the sub-steps of steps (A), (C), (D), (E), and (F) each include a photoprocessing step.
  • the term “hot processing step” refers to a series of operations from application of a hot resist to development through a selective exposure using a mask.
  • the TFT substrate is manufactured through five hot processing steps as indicated by the f-edge.
  • a transparent glass substrate SUB 1 is prepared, and a Cr—Mo alloy film is formed on the entire surface on one side by DC sputtering.
  • the substrate temperature was 200 ° C.
  • the pressure was 0.2 Pa
  • the film thickness was about 200 nm.
  • the Mo composition was also set to 50 wt%, but it is important that the film stress is controlled to be more than 200 MPa and less than 500 MPa by adjusting the sputtering conditions. It is to do so.
  • the Mo composition is preferably not less than 20 wt% and not more than 55 wt%.
  • At least one selected from Nb, Ta, and W is selected so that crystal grains having a particle size of 200 nm or more are contained and the film stress is not less than 200 MPa and not more than 500 MPa.
  • An alloy film of one element and Cr may be deposited again by DC sputtering.
  • a mask of a predetermined pattern is formed on the deposited Cr-Mo alloy film by a hot treatment (first hot).
  • the Cr—Mo alloy film is selectively etched to form a conductive film g 1 having a predetermined pattern (step (A)). At this time, this constitutes the gate line GL and the light shielding electrode SKD.
  • the angle of the end surface of the gate line GL pattern with respect to the substrate is displayed vertically for simplicity.
  • an appropriate photo resist process is performed.
  • the tapered end face of the pattern was about 70 degrees.
  • the etching solution used was a 15 wt% ceric ammonium nitrate aqueous solution.
  • a Si nitride film GI, an i-type amorphous Si (a—Si) film AS, an N-type semiconductor are formed by a plasma CVD apparatus.
  • a layer d 0 is formed sequentially.
  • a Cr-0 (50 wt% in this embodiment) alloy film is formed by a sputtering method, and this is a first conductive film d1 (step (B)).
  • this material can make the film stress almost zero by adjusting the sputtering conditions. For this reason, it is easy to get over the gap of the base without disconnection.
  • the object of the present invention can be achieved if the film stress is set to be not less than 200 MPa and not more than 50 OMPa.
  • the Mo composition is preferably from 20 w L% to 55 w t%.
  • crystal grains having a particle size of 200 nm or more are contained, and the film stress is ⁇ 200 MPa or more.
  • An alloy film of at least one element selected from Nb, Ta, and W and Cr may be deposited by a similar method so as to be 500 MPa or less.
  • a pure Cr film is used as the drain line DL (d 1), the resistance is likely to increase due to a disconnection or a poor crossover at that portion. This is due to the high stress of the Cr film, and the film stress could not be reduced no matter how the sputtering conditions were adjusted. Instead, use a Cr-Mo alloy film with the composition described above. It turns out that such problems rarely occur. Furthermore, since the taper is provided at the end of the gate line GL (g 1) pattern described above, the problem of resistance increase due to disconnection of the drain line or poor crossing over can be almost completely prevented.
  • the Cr—Mo alloy film is selectively etched to form a conductive film d 1 of a predetermined pattern.
  • the N-type semiconductor layer d0 is removed by dry etching using the photo resist PRES (step (C)).
  • the etching end of the Cr-Mo alloy film is usually receded from the photo resist PRES end by about 0.5 to l Atm.
  • the N-type semiconductor layer d0 has a very small thickness of 50 nm or less, and uses a highly anisotropic dry etching as an etching.
  • the etching retreat amount is as small as about 0.3 ⁇ m, and the lower part of the source electrode SD 1 is not etched and does not have an eaves shape.
  • step (D) the i-type semiconductor layer AS is etched away (step (D)).
  • the i-type semiconductor layer AS is stopped at the gate insulating film G 1 by a selective etching with the gate insulating film G I.
  • the hot resist PRES pattern is wider than the source electrode at the end of the source electrode SD1 so that the transparent conductive film to be formed later does not break at the end of the source electrode.
  • the data line DL part, the gate line GL and the data line DL part shown in the figure are processed using the conductive layer d1 of the data line DL as a mask without forming the photoresist PRES.
  • the i-type semiconductor layer AS does not protrude from the data line, so that high-accuracy processing can be performed.
  • This has the effect of reducing the gate capacitance required for reducing the wiring delay time. Since the conductive layer d 1 is resistant to dry etching of the i-type semiconductor layer AS, there is no problem if it is used as a mask.
  • a protective insulating film PSV 1 made of a nitrided SiN film is formed by a plasma CVD apparatus. After forming a mask for the hot resist PRES by a hot treatment (fourth hot), the protective insulating film PSV 1 is etched to remove the contact hole CN and the protective film PSV 1 at the wiring terminal portion (step (E)). )).
  • the protection IPSV is applied to the gate terminal portion GTM (including the contact hole CN of this portion) and the drain terminal portion DTM. 1 and the gate insulating film GI have the feature that they are removed by etching all at once using the same photomask.
  • the thickness of the data line and the source electrode film d DL, gate one WINCH thickness d GI insulating film, a mixed gas of CF 4 data line and the source electrode film and ⁇ 2 or S Fs and O z When the dry etching rate for the mixed gas of the gate insulating film is r DL and the dry etching rate for the mixed gas of the gate insulating film is r GI,
  • the drain wiring D L (d 1) will be disconnected by dry etching at the contact hole C N.
  • deterioration of the drain wiring surface in that portion becomes severe, and defects such as line defects and the like, in which the electrical contact with the second conductive film d 2 made of an ITO film to be formed in a later step becomes insufficient. It has been found that this is likely to occur.
  • a second conductive film d2 composed of an IT0 film was deposited by a sputtering method.
  • the target had ffl a sintered body obtained by adding 1 0 wt% of the S n 0, the I n 2 0 a, sputtering conditions, the substrate temperature 2 1 5 ° C, 1 "to about 1% 0 2
  • the pressure was set to 0.67 Pa and the film thickness to 140 nm using a sputtering gas to which was added.
  • the second conductive film was formed.
  • the film d 2 is selectively etched to leave an ITO pattern on the transparent conductive film IT01 or the like (step (F)).
  • step (B) after sequentially depositing the nitrided Si film GI, the i-type amorphous Si film AS, and the N-type semiconductor layer d0 by plasma CVD, the sputtering is continued.
  • a Cr-Mo alloy film was deposited by a sputtering method.
  • the following method may be adopted. That is, three-layer film deposition by CVD
  • the i-type amorphous Si film AS is processed (corresponding to the second hot step, step (D)), and then a Cr—Mo alloy film is sputtered.
  • the Cr—Mo alloy film is selectively etched to form a conductive film d1 pattern. Then, the N-type semiconductor layer d O is dry-etched and removed using the same photoresist PRES (corresponding to step (C)).
  • the wiring material was deeply studied, and the TFT element structure, especially the structure over the step and the contact characteristics at the opening of the protective film were sufficiently considered. It has been confirmed that disconnection of the film and contact failure can be prevented, and the yield during manufacturing is improved.
  • a TFT substrate constituting a display panel can be manufactured in a simple process using five photo-resist steps, which is advantageous in that an inexpensive liquid crystal display device can be provided.
  • a feature of the present invention is that a bright liquid crystal display device with a high aperture ratio can be realized.
  • the liquid crystal display device according to the present invention is useful not only for reducing the number of manufacturing steps but also for preventing the occurrence of disconnection and improving the manufacturing yield.

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Abstract

On dispose à la surface du substrat d'un dispositif d'affichage à cristaux liquides, d'une pluralité de lignes de grille, d'une pluralité de lignes de données croisant les lignes de grille, d'une pluralité de transistors à couches minces formés près des intersections des lignes de grille avec les lignes de données et d'une pluralité d'électrodes de points-image reliées respectivement aux transistors. On dépose sur les lignes de grille un film isolant la grille et on forme les lignes de données sur ledit film isolant. On dépose un film isolant protecteur sur le film isolant la grille, sur les lignes de données et les transistors à couches minces. On relie les électrodes des points-image aux électrodes source de leurs transistors à couches minces correspondants par l'intermédiaire d'ouvertures ménagées dans le film isolant protecteur. Les sections latérales périphériques de la grille et des films isolants protecteurs ont la même forme plane. Afin de donner aux sections latérales périphériques des films isolants une même forme, on grave ces films isolants selon le même motif de masque de photogravure. L'électrode source de chacun des transistors à couches minces est composée d'un film métallique ayant une taille de grain supérieure ou égale à 200 nm.
PCT/JP1997/000062 1996-01-18 1997-01-16 Dispositif d'affichage a cristaux liquides et procede de fabrication associe WO1997026585A1 (fr)

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JP632196 1996-01-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149852A (ja) * 2005-11-25 2007-06-14 Tokyo Electron Ltd プラズマエッチング方法および半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172463A (ja) * 1987-01-09 1988-07-16 Mitsubishi Electric Corp 半導体装置
JPH0424925A (ja) * 1990-05-16 1992-01-28 Nippon Telegr & Teleph Corp <Ntt> 薄膜部品用配線材料
JPH04257826A (ja) * 1991-02-13 1992-09-14 Sharp Corp アクティブマトリクス基板の製造方法
JPH04303826A (ja) * 1991-03-30 1992-10-27 Nec Corp アクティブマトリックス基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172463A (ja) * 1987-01-09 1988-07-16 Mitsubishi Electric Corp 半導体装置
JPH0424925A (ja) * 1990-05-16 1992-01-28 Nippon Telegr & Teleph Corp <Ntt> 薄膜部品用配線材料
JPH04257826A (ja) * 1991-02-13 1992-09-14 Sharp Corp アクティブマトリクス基板の製造方法
JPH04303826A (ja) * 1991-03-30 1992-10-27 Nec Corp アクティブマトリックス基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149852A (ja) * 2005-11-25 2007-06-14 Tokyo Electron Ltd プラズマエッチング方法および半導体装置の製造方法

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