WO1997024764A1 - Systeme de boitier integre - Google Patents

Systeme de boitier integre Download PDF

Info

Publication number
WO1997024764A1
WO1997024764A1 PCT/GB1997/000008 GB9700008W WO9724764A1 WO 1997024764 A1 WO1997024764 A1 WO 1997024764A1 GB 9700008 W GB9700008 W GB 9700008W WO 9724764 A1 WO9724764 A1 WO 9724764A1
Authority
WO
WIPO (PCT)
Prior art keywords
components
electronic device
integrated circuit
electronic
circuit
Prior art date
Application number
PCT/GB1997/000008
Other languages
English (en)
Inventor
Kurt Orthmann
Peter Mittertrainer
Johann Hoffmann
Original Assignee
Texas Instruments Incorporated
Texas Instruments Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated, Texas Instruments Limited filed Critical Texas Instruments Incorporated
Priority to EP97900261A priority Critical patent/EP0812474A1/fr
Publication of WO1997024764A1 publication Critical patent/WO1997024764A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • This invention generally relates to electronic circuits and more particularly to an integrated system package having a plurality of overmolded electronic components.
  • PCB printed circuit board
  • IC integrated circuit
  • IC chips can function as certain electronic components.
  • an IC can serve as a resistor or a capacitor.
  • ICs are typically limited with respect to the number of electronic components which are incorporated in the IC. Such limitations result from many aspects of electronic circuitry including, without limitation, the complexity of the particular circuit being created.
  • one or more ICs are wired together on a PCB.
  • an IC is coupled with other non-IC circuit components on the PCB.
  • size limitations are still inherent in this technology. Additionally, other problems exist such as the time and cost involved in the assembly of a given circuit on the PCB.
  • an integrated system package which includes an electrical circuit consisting of one or more electronic components which are electrically connected and then overmolded as a single unit.
  • the electronic components may include IC and non-IC components,
  • the standard package may provide a desired electrical function by itself or may be connected with other components on a printed circuit board, for example, as an element of a larger overall circuit.
  • the integrated system package can also simplify, and standardize circuits which are too complex to be manufactured as an integrated circuit or otherwise do not lend themselves to assembly as integrated circuits. Other advantages will be recognized to those having ordinary skill in the art.
  • an IC chip is electrically coupled with two capacitors and an antenna to form a transponder.
  • the IC has an input/output option for data transfer.
  • the other components provide the electrical function of the transponder. All of the components are overmolded to protect the components from the environment and to provide a standard transponder package.
  • the transponder may be incorporated in a larger circuit via a printed circuit boar .
  • FIGURE 1 is an overmolded circuit according to an embodiment of the present invention.
  • FIGURE 2 is a side view of the overmolded circuit of FIGURE 1 in the direction of arrow A.
  • the present invention provides an integrated system package in which various electronic components are coupled together and overmolded to form a standardized package.
  • the package can provide a desired electrical function by itself or may be incorporated into a larger circuit by way of coupling the package with other components on a printed circuit board, for example.
  • one or more electrical components are coupled together on a lead frame.
  • At least one of the components is an integrated circuit chip (IC chip).
  • IC chip 10 is provided to perform a first electronic function.
  • a plurality of additional electronic components 20, 30 and 40 are provided and are electrically coupled together with IC chip I 0 to form a first electrical circuit.
  • IC chip 10 may function, for example, as a resistor. However, other types of IC chips may be incorporated into the present invention. Further, more than one IC may be incorporated into the first electrical circuit.
  • the plurality of additional electronic components are each non-IC components and may include such components as resistors, capacitors, inductors, antennas, and the like. Any passive device may be used.
  • component 20 is a resistor
  • component 30 is a capacitor
  • component 40 is an antenna.
  • the present invention is not so limited, however, and any electronic component which can be overmolded may be used.
  • the components are coupled together and overmolded to form a standard package. Any suitable over olding process may be used, including conventional overmolding processes.
  • the IC chip 10 and components 20, 30 and 40 may be coupled together via coupling medium 60.
  • Coupling medium 60 may be any conventional lead frame.
  • the coupling medium may be a lead frame which is customized and specifically adapted to receive both IC chips and non-IC components.
  • the coupling medium may be a printed circuit board or other medium suitable for coupling the components together.
  • IC chip 10 and the plurality of non-IC components may be coupled together on a lead frame by conductive glue, for example.
  • Conductive glue is manufactured by Epotek or Grace of Demetron/Degussa, for example, and is basically an epoxy filled with silver.
  • other suitable bonding processes may be used.
  • each of the IC and non-IC components may be bonded to a substrate by means of an epoxy, solder, or eutectic bond. Then the IC and non-IC components may be coupled by wire bonding using thermocompression or ultrasonic bonding techniques. The necessary leads to the resulting circuit are then connected to the conduction leads of the lead frame. The particular connections made will depend upon the circuit being created.
  • the first circuit 50 is preferably encapsulated by an overmolding layer 70.
  • Overmolding layer 70 may be formed by any suitable overmolding or encapsulation process.
  • the overmoldinj process is preferably conducted at a relatively low temperature and pressure so as to avoid subjecting the components to stress both during and after the overmolding process. Thus, transfer overmolding is preferable.
  • other types of overmoldincj processes may be used.
  • the package can be encapsulated in a resin using a direct dispensing method or by a screen printing method..
  • the circuit 50 may be placed in a mold, which is then injected with a suitable molten plastic compound.
  • the package may comprise its own discrete electronic circuit and may be used to provide a desired electronic function by itself Alternately, the package may be coupled with other similarly-formed packages, other IC components, and/or other non-IC components to form a larger second circuit.
  • the above-described techniques are used to provide an overmolded standard digital input/output transponder package.
  • This standard package may be used, for example, in the transponder arrangement described in U. S. Patent No. 5,053,774 issued to Schuermann et al.
  • a first circuit is formed as described above and preferably comprises an IC chi ' .
  • the IC chip should have an input/output option (110) to allow data transfer and can be accessed through the leads of a lead frame.
  • the IC chip may also have a memory section and an air interface system.
  • the I/O can handle incoming and outgoing data.
  • the memory section buffers the received data before sending or shortly after receiving so as to buffer the 110 channel.
  • the air transmittal system includes logic for transmitting data over the air to a receiver.
  • the IC chip may be coupled to a plurality of capacitors and antennas.
  • the IC chip may be connected to first and second capacitors having capacitances of 470pF and 120nF, respectively.
  • An antenna may also be incorporated into the circuit.
  • an antenna having an inductance of 2.5mH may be used.
  • these components are integrated in a standard DIL-14 housing.
  • the transponder package may thus provide interrogation and response functions associated with transponders.
  • the package may function as a contactless radio frequency identification device (RFID) for work tracking, object identification and similar applications. It may provide these electronic functions by itself with power being supplied by the capacitors.
  • a power supply may be incorporated in the transponder package.
  • the transponder package may be included as pact of a larger overall circuit as described above. It should be noted that the specifics of the above- described transponder package are provided by way of example only, and other transponder configurations are possible according to the present invention. For instance, the capacitance and inductance values will depend on the particular application and variables such as frequency range and environmental factors.
  • the standard overmolded transponder package can be coupled to sensors (e.g. , temperature, humidity, or pressure sensors) by way of a printed circuit board. Alternately, the sensors may be included in the standard package itself.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

L'invention concerne un boîtier standard dans lequel des composants (10) du type circuits intégrés et des composants (20, 30, 40) du type circuits non intégrés sont connectés ensemble électriquement et ensuite recouverts par moulage (70). Les composants peuvent être montés ensemble sur une grille de connexion (60). Le boîtier standard peut assurer seul une fonction électrique souhaitée, ou il peut être associé à d'autres boîtiers recouverts par moulage ou à d'autres composants électroniques additionnels, non recouverts par moulage.
PCT/GB1997/000008 1996-01-02 1997-01-02 Systeme de boitier integre WO1997024764A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP97900261A EP0812474A1 (fr) 1996-01-02 1997-01-02 Systeme de boitier integre

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US947996P 1996-01-02 1996-01-02
US60/009,479 1996-01-02

Publications (1)

Publication Number Publication Date
WO1997024764A1 true WO1997024764A1 (fr) 1997-07-10

Family

ID=21737907

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1997/000008 WO1997024764A1 (fr) 1996-01-02 1997-01-02 Systeme de boitier integre

Country Status (2)

Country Link
EP (1) EP0812474A1 (fr)
WO (1) WO1997024764A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000021032A1 (fr) * 1998-10-06 2000-04-13 Intermec Ip Corp. Systemes rfid integres dans des biens electroniques
DE102006033175A1 (de) * 2006-07-18 2008-01-24 Robert Bosch Gmbh Elektronikanordnung
EP1765146B1 (fr) * 2004-05-31 2009-04-29 Medigus Ltd. Tete de camera miniature reutilisable

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989447A (ja) * 1982-11-15 1984-05-23 Matsushita Electric Ind Co Ltd 半導体装置
JPS6114731A (ja) * 1984-06-29 1986-01-22 Nec Kansai Ltd 半導体装置
WO1994018700A1 (fr) * 1993-02-11 1994-08-18 Indala Corporation Procede de production d'un repeteur de frequences radioelectriques a boitier moule etanche a l'environnement
EP0615285A2 (fr) * 1993-03-11 1994-09-14 Btg International Limited Montage d'un circuit électronique sur un substrat
JPH0766356A (ja) * 1993-08-30 1995-03-10 Nec Corp チップ部品の実装構造
DE4410212A1 (de) * 1994-03-24 1995-09-28 Telefunken Microelectron Elektronische Baugruppe
JPH07306264A (ja) * 1994-05-13 1995-11-21 Chikusanyo Denshi Gijutsu Kenkyu Kumiai 個体管理用トランスポンダ

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989447A (ja) * 1982-11-15 1984-05-23 Matsushita Electric Ind Co Ltd 半導体装置
JPS6114731A (ja) * 1984-06-29 1986-01-22 Nec Kansai Ltd 半導体装置
WO1994018700A1 (fr) * 1993-02-11 1994-08-18 Indala Corporation Procede de production d'un repeteur de frequences radioelectriques a boitier moule etanche a l'environnement
EP0615285A2 (fr) * 1993-03-11 1994-09-14 Btg International Limited Montage d'un circuit électronique sur un substrat
JPH0766356A (ja) * 1993-08-30 1995-03-10 Nec Corp チップ部品の実装構造
DE4410212A1 (de) * 1994-03-24 1995-09-28 Telefunken Microelectron Elektronische Baugruppe
JPH07306264A (ja) * 1994-05-13 1995-11-21 Chikusanyo Denshi Gijutsu Kenkyu Kumiai 個体管理用トランスポンダ

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 008, no. 200 (E - 266) 13 September 1984 (1984-09-13) *
PATENT ABSTRACTS OF JAPAN vol. 010, no. 158 (E - 409) 6 June 1986 (1986-06-06) *
PATENT ABSTRACTS OF JAPAN vol. 95, no. 006 31 July 1995 (1995-07-31) *
PATENT ABSTRACTS OF JAPAN vol. 96, no. 03 29 March 1996 (1996-03-29) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249227B1 (en) 1998-01-05 2001-06-19 Intermec Ip Corp. RFID integrated in electronic assets
WO2000021032A1 (fr) * 1998-10-06 2000-04-13 Intermec Ip Corp. Systemes rfid integres dans des biens electroniques
EP1765146B1 (fr) * 2004-05-31 2009-04-29 Medigus Ltd. Tete de camera miniature reutilisable
DE102006033175A1 (de) * 2006-07-18 2008-01-24 Robert Bosch Gmbh Elektronikanordnung

Also Published As

Publication number Publication date
EP0812474A1 (fr) 1997-12-17

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