WO1997019463A3 - Chipmodul - Google Patents

Chipmodul Download PDF

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Publication number
WO1997019463A3
WO1997019463A3 PCT/DE1996/002194 DE9602194W WO9719463A3 WO 1997019463 A3 WO1997019463 A3 WO 1997019463A3 DE 9602194 W DE9602194 W DE 9602194W WO 9719463 A3 WO9719463 A3 WO 9719463A3
Authority
WO
WIPO (PCT)
Prior art keywords
contact layer
semiconductor chip
chip
contact
chip module
Prior art date
Application number
PCT/DE1996/002194
Other languages
English (en)
French (fr)
Other versions
WO1997019463A2 (de
Inventor
Detlef Houdeau
Peter Stampka
Original Assignee
Siemens Ag
Detlef Houdeau
Peter Stampka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Detlef Houdeau, Peter Stampka filed Critical Siemens Ag
Publication of WO1997019463A2 publication Critical patent/WO1997019463A2/de
Publication of WO1997019463A3 publication Critical patent/WO1997019463A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

Die Erfindung bezieht sich auf ein Chipmodul mit einer aus elektrisch leitendem Material gefertigten Kontaktschicht (2) mit mehreren Kontaktelementen (4) und einem Halbleiterchip (7) mit auf der Hauptfläche (5) des Halbleiterchips (7) angeordneten Chipanschlüssen, die jeweils elektrisch mit einem Kontaktelement (4) der Kontaktschicht (2) verbunden sind. Des weiteren ist auf der dem Halbleiterchip (7) zugewandten Oberfläche der elektrisch leitenden Kontaktschicht (2) eine dünne Isolationsfolie (10) aus elektrisch isolierendem Material vorgesehen, welche sowohl auf ihrer der Kontaktschicht (2) zugewandten Vorderseite als auch auf ihrer der Kontaktschicht (2) abgewandten Rückseite (8) eine Haft- bzw. Klebefunktion besitzt.
PCT/DE1996/002194 1995-11-21 1996-11-18 Chipmodul WO1997019463A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19543427A DE19543427C2 (de) 1995-11-21 1995-11-21 Chipmodul, insbesondere zum Einbau in eine Chipkarte
DE19543427.7 1995-11-21

Publications (2)

Publication Number Publication Date
WO1997019463A2 WO1997019463A2 (de) 1997-05-29
WO1997019463A3 true WO1997019463A3 (de) 1997-08-14

Family

ID=7778050

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/002194 WO1997019463A2 (de) 1995-11-21 1996-11-18 Chipmodul

Country Status (2)

Country Link
DE (1) DE19543427C2 (de)
WO (1) WO1997019463A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE29708687U1 (de) * 1997-05-15 1997-07-24 Siemens AG, 80333 München Klebeverbindung
DE19735170A1 (de) * 1997-08-13 1998-09-10 Siemens Ag Chipmodul, insbesondere für kontaktbehaftete Chipkarten, mit nebeneinander angeordneten Chips
US6630545B2 (en) 1997-09-15 2003-10-07 The Dow Chemical Company Polymerization process
US6150297A (en) 1997-09-15 2000-11-21 The Dow Chemical Company Cyclopentaphenanthrenyl metal complexes and polymerization process
US6806327B2 (en) 2000-06-30 2004-10-19 Dow Global Technologies Inc. Substituted polycyclic, fused ring compounds, metal complexes and polymerization process
DE60138708D1 (de) 2000-06-30 2009-06-25 Dow Global Technologies Inc Polyzyklische, kondensierte ringverbindungen, meta
DE10109993A1 (de) * 2001-03-01 2002-09-05 Giesecke & Devrient Gmbh Verfahren zur Herstellung eines Moduls
JP2002312746A (ja) * 2001-04-11 2002-10-25 Toshiba Corp Ｉｃモジュール及びその製造方法、並びに該ｉｃモジュールを装着した携帯可能電子装置
DE60204686T2 (de) * 2001-05-14 2006-05-18 Dow Global Technologies, Inc., Midland 3-arylsubstituierte zyklopentadienyl-metal-komplexe und polymerisationsverfahren
US6946531B2 (en) 2001-05-14 2005-09-20 Dow Global Technologies Inc. Low molecular weight ethylene interpolymers and polymerization process
AU2003216476A1 (en) 2002-03-14 2003-09-29 Dow Global Technologies Inc. Substituted indenyl metal complexes and polymerization process
FR2838850B1 (fr) 2002-04-18 2005-08-05 Framatome Connectors Int Procede de conditionnement de microcircuits electroniques pour carte a puce et microcircuit electronique ainsi obtenu
DE102004025911B4 (de) * 2004-05-27 2008-07-31 Infineon Technologies Ag Kontaktbehaftete Chipkarte, Verfahren zur Herstellung einer solchen
DE102004029585A1 (de) * 2004-06-18 2006-01-19 Infineon Technologies Ag Chip-Package
DE102006060411B3 (de) * 2006-12-20 2008-07-10 Infineon Technologies Ag Chipmodul und Verfahren zur Herstellung eines Chipmoduls

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4699842A (en) * 1985-10-17 1987-10-13 Minnesota Mining And Manufacturing Company Pressure-sensitive adhesive having broad useful temperature range
JPH0262297A (ja) * 1988-08-29 1990-03-02 Matsushita Electric Ind Co Ltd 集積回路装置およびそれを用いたｉｃカード
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
EP0513521A2 (de) * 1991-05-02 1992-11-19 International Business Machines Corporation Halbleiterpackung mit Drähten und eine Oberfläche mit planierter Dünnfilmdecke
US5221642A (en) * 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
DE4232625A1 (de) * 1992-09-29 1994-03-31 Siemens Ag Verfahren zur Montage von integrierten Halbleiterschaltkreisen
US5304842A (en) * 1990-10-24 1994-04-19 Micron Technology, Inc. Dissimilar adhesive die attach for semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579798B1 (fr) * 1985-04-02 1990-09-28 Ebauchesfabrik Eta Ag Procede de fabrication de modules electroniques pour cartes a microcircuits et modules obtenus selon ce procede
US5304513A (en) * 1987-07-16 1994-04-19 Gao Gesellschaft Fur Automation Und Organisation Mbh Method for manufacturing an encapsulated semiconductor package using an adhesive barrier frame
FR2645680B1 (fr) * 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg Encapsulation de modules electroniques et procede de fabrication
FR2673041A1 (fr) * 1991-02-19 1992-08-21 Gemplus Card Int Procede de fabrication de micromodules de circuit integre et micromodule correspondant.
DE9110057U1 (de) * 1991-08-14 1992-02-20 Orga Kartensysteme GmbH, 6072 Dreieich Datenträgerkarte mit eingeklebtem Schaltkreisträger

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4699842A (en) * 1985-10-17 1987-10-13 Minnesota Mining And Manufacturing Company Pressure-sensitive adhesive having broad useful temperature range
JPH0262297A (ja) * 1988-08-29 1990-03-02 Matsushita Electric Ind Co Ltd 集積回路装置およびそれを用いたｉｃカード
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5304842A (en) * 1990-10-24 1994-04-19 Micron Technology, Inc. Dissimilar adhesive die attach for semiconductor devices
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
EP0513521A2 (de) * 1991-05-02 1992-11-19 International Business Machines Corporation Halbleiterpackung mit Drähten und eine Oberfläche mit planierter Dünnfilmdecke
US5221642A (en) * 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
DE4232625A1 (de) * 1992-09-29 1994-03-31 Siemens Ag Verfahren zur Montage von integrierten Halbleiterschaltkreisen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 235 (M - 0975) 18 May 1990 (1990-05-18) *

Also Published As

Publication number Publication date
WO1997019463A2 (de) 1997-05-29
DE19543427A1 (de) 1997-05-22
DE19543427C2 (de) 2003-01-30

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