WO1996038912A1 - Circuit a retard variable - Google Patents

Circuit a retard variable Download PDF

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Publication number
WO1996038912A1
WO1996038912A1 PCT/JP1996/001482 JP9601482W WO9638912A1 WO 1996038912 A1 WO1996038912 A1 WO 1996038912A1 JP 9601482 W JP9601482 W JP 9601482W WO 9638912 A1 WO9638912 A1 WO 9638912A1
Authority
WO
WIPO (PCT)
Prior art keywords
effect transistor
circuit
delay circuit
variable delay
mos field
Prior art date
Application number
PCT/JP1996/001482
Other languages
English (en)
Japanese (ja)
Inventor
Hiroo Suzuki
Toshiyuki Okayasu
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to KR1019970700673A priority Critical patent/KR970705234A/ko
Priority to DE19680525T priority patent/DE19680525T1/de
Publication of WO1996038912A1 publication Critical patent/WO1996038912A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors

Definitions

  • the present invention relates to a variable delay circuit useful for, for example, generating various timing signals.
  • timing signals are required to generate a test pattern given to an IC under test and various control signals.
  • a conventional timing signal generator for generating various timing signals generally, a large number of delay elements are cascaded, and a desired delay time is provided between each stage of the cascade-connected delay elements or from each output side. delay circuit force s are used and configured to obtain a timing signal having a.
  • a logic element formed as an IC such as an IC having a MOS structure (MOS ⁇ IC) is generally used.
  • CMOS ⁇ IC CMOS integrated circuit
  • CMOS complementary MOS
  • a delay circuit for extracting a signal having a different delay time from each output side is conventionally known. The signal extracted from this delay circuit is used as various timing signals.
  • the delay time given to the input signal is determined by the number of connection stages of the logic elements, so that the delay time cannot be finely adjusted. Therefore, there is a disadvantage that the delay time cannot be set with a fine resolution. Disclosure of the invention
  • a delay circuit configured to extract a signal having a different delay time s from each stage or from each output side of a plurality of cascaded logic elements formed as an IC.
  • a series circuit composed of a field-effect transistor and a capacitor is connected between each stage of a plurality of connected logic elements or between each output side and a common potential point to continuously change a delay time.
  • a variable delay circuit is provided.
  • the plurality of cascaded logic elements are formed as CMO S ICs, and a CM 0 S electric field is applied between each stage of the cascaded logic elements or between each output and a common potential point.
  • a series circuit composed of an effect transistor and a capacitor is connected.
  • variable delay circuit According to the variable delay circuit according to the first aspect, a forward bias is applied to the gate electrode of the field effect transistor connected in series with the capacitance element, and the forward bias voltage is changed, so that the The resistance value between drain and source can be changed. Therefore, it becomes equivalent to a circuit configuration in which a variable resistor is connected in series with a capacitive element. By changing the resistance value of this variable resistor, the delay time of the logical element can be finely adjusted.
  • a p-type (p-channel) MOS field-effect transistor and an n-type (n-channel) MOS field-effect transistor are connected in series by connecting their drain electrodes in common.
  • the gate electrodes of these field effect transistors are connected in common, and the connection point is used as an input terminal, and the connection point of both commonly connected drain electrodes is used as an output terminal to constitute a polarity inversion type logic circuit.
  • a variable delay circuit that controls the delay time by changing the bias voltage applied to each substrate electrode of the p-type MOS field-effect transistor and the n-type MOS field-effect transistor Is provided.
  • variable delay circuit According to the variable delay circuit according to the second aspect, the delay time is continuously changed by changing the voltage applied to each substrate electrode of the p-type MOS field-effect transistor and the n-type MOS field-effect transistor. Can be done. As a result, the delay It is possible to provide a variable delay circuit that can maintain the delay time automatically at a constant value by the addition of automatic control means. Description
  • FIG. 1 is a circuit connection diagram showing a first embodiment of the variable delay circuit according to the present invention.
  • FIG. 2 is a circuit connection diagram electrically equivalent to the variable delay circuit shown in FIG.
  • FIG. 3 is a circuit connection diagram showing a second embodiment of the variable delay circuit according to the present invention.
  • FIG. 4 is a circuit connection diagram that is electrically equivalent to the variable delay circuit shown in FIG.
  • FIG. 5 is a block diagram showing an application example of the variable delay circuit shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a first embodiment of the variable delay circuit according to the present invention.
  • the variable delay circuit is composed of a plurality (two in this example) of logic elements LG, such as a buffer amplifier, connected in cascade between its input terminal 2 and output terminal 3. And a series circuit composed of a field effect transistor Tr and a capacitor C connected between the stages of the logic elements LG and the common potential point (ground point) G.
  • This variable delay circuit is formed as CMOS.IC.
  • the gate electrode of the field-effect transistor Tr is connected to a control terminal 4 provided outside the CMOS IC, and a control voltage is applied to the control terminal 4 so that the resistance value between the drain and the source of the field-effect transistor Tr is reduced. Set any resistance value.
  • the field effect transistor Tr of the variable delay circuit 1 can be regarded as a circuit element equivalent to the variable resistor VR as shown in FIG. Accordingly, the time constant of the capacitor C can be changed by changing the control voltage applied to the gate of the field-effect transistor Tr to change the resistance value between the drain and source of the field-effect transistor Tr. Therefore, the delay time between the input terminal 2 and the output terminal 3 can be continuously and finely changed. Therefore, the variable delay circuit 1 having the configuration shown in FIG. 1 is cascaded, and a delay signal is extracted from an arbitrary stage of the cascade-connected variable delay circuits. However, a slightly different delay signal can be obtained. That is, the delay time can be accurately set to the target value.
  • FIG. 3 shows a second embodiment of the variable delay circuit according to the present invention.
  • a p-type MOS field-effect transistor PMOS and an n-type MOS field-effect transistor NMOS are connected in series by connecting their drain electrodes D in common, and a gate electrode is formed. Gs are commonly connected, the connection point of the commonly connected gate electrode is connected to the input terminal 2, and the output terminal 3 is derived from the connection point of the commonly connected drain electrode D.
  • This series connection circuit of the p-type MOS field-effect transistor PMOS and the n-type MOS field-effect transistor NMOS is equivalent to a polarity inversion amplifier, also called an inverter.
  • variable delay circuit 1 is configured by connecting a capacitor C between a connection point of the commonly connected drain electrode D and a common potential point (ground point).
  • This variable delay circuit 1 is also formed as a CMOS IC.
  • the substrate electrodes 5 and 6 of the p-type M 0 S field-effect transistor PM 0 S and the n-type M 0 S field-effect transistor NMOS are separated from the source electrode, and the substrate bias voltage is applied to the substrate electrodes 5 and 6. + V BP and one V BN .
  • the substrate bias voltage + V BP and one VBN apply the voltage applied to the source of the P-type M 0 S field-effect transistor PM ⁇ S to + VDD, and the voltage applied to the source electrode of the n-type M 0 S field-effect transistor XM 0 S Voltage is 1 Vss,
  • VBP VDD + ⁇
  • VBN VSS (1).
  • FIG. 4 shows an electrical equivalent circuit of the variable delay circuit 1 of FIG.
  • the p-type MOS field-effect transistor PMOS and the n-type MOS field-effect transistor NMOS are it force regarded as a series circuit of respectively switch SW as shown in Figure 4 and the resistor R? can.
  • the substrate noise voltage + V BP and one V BN are changed, the threshold voltages of the field effect transistors PMOS and NMOS are changed, and the resistance value of the resistor R can be equivalently changed.
  • the resistance value is in equation (1).
  • Control can be performed in the direction in which the resistance value increases.
  • FIG. 5 shows an application example of the variable delay circuit shown in FIG.
  • a control circuit that automatically controls the variable delay circuit 1 shown in Fig. 3 to prevent the delay time s ' from changing due to temperature fluctuations and to maintain a constant delay time is added. It is.
  • the logic element denoted by reference numeral 10 is an in-phase amplification type (polarity non-inverting type) variable delay circuit configured by cascading two stages of the polarity inversion type variable delay circuit 1 shown in FIG. is there.
  • N in-phase amplification type variable delay circuits 10 are cascaded to form an N-stage variable delay circuit 11.
  • the N-stage variable delay circuit 11 is formed as CMOS ⁇ IC.
  • a pulse train CLK is applied to the input terminal 12 of the N-stage variable delay circuit 11 (the input terminal of the first-stage in-phase amplification type variable delay circuit 10).
  • the other input terminal of the phase comparator 13 is connected to the input terminal 12 of the N-stage variable delay circuit 11, and the pulse train CLK supplied to this input terminal 12 is directly supplied to the phase comparator 13 to perform phase comparison.
  • the phase of the pulse delayed by the N-stage variable delay circuit 11 is compared with the phase of the pulse that is not delayed in the device 13.
  • phase comparison result output of the phase comparator 13 is smoothed by the filter 14, and the smoothed phase comparison result output is supplied to the substrate bias generator 15. to generate a bias voltage + V BP and single V B N, the board Baiasu voltage + V B p and - giving each VBN to the substrate electrode 5 and 6 were derived from the phase-amplified variable delay circuit 1 0, the phase It is configured to control the delay time of the amplification type variable delay circuit 10. In this configuration, if the delay amount of the N-stage variable delay circuit 11 fluctuates in a direction to be shortened due to, for example, temperature change, the fluctuation of the delay amount appears in the phase comparison result output of the phase comparator 13.
  • the phase comparison result output is controlled so that the absolute values of the substrate bias voltage + V BP and 1 V BN generated from the substrate bias generator 15 increase.
  • the delay time of each phase amplified variable delay circuit 1 0 is controlled in a direction in which a long, original delay time Is returned to.
  • the phase comparison result output of the phase comparator 13 is opposite to the previous case (in the case of shifting in the direction of decreasing the delay time). Polarity, so that the substrate bias generator 15
  • the change in the substrate bias voltage controls the delay time of the N-stage variable delay circuit 11 to be shortened.
  • each output side of the N common-mode amplification type variable delay circuits 10 constituting the N-stage variable delay circuit 11 is connected to, for example, one input of a corresponding AND gate of the AND gate group G.
  • the N-stage variable delay circuit 11 connected to the terminal, and through an AND gate group G, the N-stage variable delay circuit 11 constitutes an N-stage in-phase amplification type variable delay circuit 10 so that a delayed signal is extracted between any one of the stages or from the output side.
  • each AND gate of the AND gate group G is connected to the control circuit, and only the AND gate to which a control signal is applied from this control circuit is in an operable state. It has been.
  • the output of the AND gate group G is configured to be output to the outside via the OR circuit.
  • the variable delay circuit is configured as one CMOS IC.
  • the present invention can be applied to a case where the variable delay circuit is configured by an integrated circuit other than the CMOS IC. Needless to say, an effect can be obtained.
  • the delay time of the delay circuit is changed by changing the time constant by using the resistance change of the field effect transistor. It can be changed continuously, and minute delay times can be set with good resolution.
  • automatic control can be performed so that the delay time of the delay circuit is always constant.
  • a stable and fine delay time can be set. Therefore, there is obtained an advantage that a desired delay time can be obtained with high accuracy, and the delay time can be maintained at a constant value for a long period of time.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

Circuit à retard variable à base de circuits logiques sous forme de circuit intégré CMOS comprenant une série d'éléments logiques (LG) sous forme de circuit intégré CMOS (LG) produisant un retard fonction de leur nombre. Un circuit en série comportant un transistor MOS et un condensateur (C) est connecté entre la jonction entre deux éléments logiques contiguës ou chacune des sorties, et un point à potentiel commun. Une tension de polarisation appliquée à la grille du transistor MOS peut être réglée de manière à faire varier la valeur de la résistance entre le drain et la source. On peut ainsi modifier la constante de temps du circuit en série et faire varier le retard en continu.
PCT/JP1996/001482 1995-06-02 1996-05-31 Circuit a retard variable WO1996038912A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019970700673A KR970705234A (ko) 1995-06-02 1996-05-31 가변지연회로
DE19680525T DE19680525T1 (de) 1995-06-02 1996-05-31 Veränderbare Verzögerungsschaltung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/136408 1995-06-02
JP7136408A JPH08330921A (ja) 1995-06-02 1995-06-02 可変遅延回路

Publications (1)

Publication Number Publication Date
WO1996038912A1 true WO1996038912A1 (fr) 1996-12-05

Family

ID=15174470

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/001482 WO1996038912A1 (fr) 1995-06-02 1996-05-31 Circuit a retard variable

Country Status (5)

Country Link
JP (1) JPH08330921A (fr)
KR (1) KR970705234A (fr)
DE (1) DE19680525T1 (fr)
TW (1) TW307955B (fr)
WO (1) WO1996038912A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100489587B1 (ko) * 1997-12-29 2005-08-23 주식회사 하이닉스반도체 시간지연회로
US7498865B2 (en) 2003-02-25 2009-03-03 Panasonic Corporation Semiconductor integrated circuit with reduced speed variations
US20050083095A1 (en) * 2003-10-16 2005-04-21 Tsvika Kurts Adaptive input/output buffer and methods thereof
JP4729251B2 (ja) * 2003-11-28 2011-07-20 株式会社アドバンテスト 高周波遅延回路、及び試験装置
US7382117B2 (en) * 2005-06-17 2008-06-03 Advantest Corporation Delay circuit and test apparatus using delay element and buffer
JP4928097B2 (ja) * 2005-07-29 2012-05-09 株式会社アドバンテスト タイミング発生器及び半導体試験装置
KR100955682B1 (ko) * 2008-04-28 2010-05-03 주식회사 하이닉스반도체 센싱 지연회로 및 이를 이용한 반도체 메모리 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272619A (ja) * 1986-05-21 1987-11-26 Hitachi Ltd 遅延回路
JPS63246916A (ja) * 1987-04-02 1988-10-13 Mitsubishi Electric Corp インバ−タ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352945A (en) * 1993-03-18 1994-10-04 Micron Semiconductor, Inc. Voltage compensating delay element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62272619A (ja) * 1986-05-21 1987-11-26 Hitachi Ltd 遅延回路
JPS63246916A (ja) * 1987-04-02 1988-10-13 Mitsubishi Electric Corp インバ−タ回路

Also Published As

Publication number Publication date
TW307955B (fr) 1997-06-11
KR970705234A (ko) 1997-09-06
JPH08330921A (ja) 1996-12-13
DE19680525T1 (de) 1997-07-24

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