Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S29/00—Metal working
  • Y10S29/012—Method or apparatus with electroplating
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Definitions

• the invention relates to a method for connecting an electrical connection of an unpackaged IC component to a conductor track on a substrate in accordance with the preamble of claim 1.
• WO 94/05139 describes a method for producing finely structured electrically conductive layers on a substrate, in which In order to improve the structure fineness and edge sharpness, a thin activation layer (nucleation) with the desired layer structure is applied, and then a thicker conductive layer of electrically conductive metal, for example copper (Cu) or nickel (Ni), is attached to the nucleation. The deposition takes place by the deposition from a galvanic bath or without current from a reduction bath.
• Cu copper
• Ni nickel
• connection techniques for mounting an IC component on a substrate conductor tracks have been applied to the side of the substrate facing away from the IC component and provided with contact areas.
• For connecting the IC component to the contact surfaces of the conductor tracks there are through holes in the substrate and the conductor tracks, on which the IC components are positioned with their connection surfaces. Thus, each connection surface covers the associated hole.
• the contact and connection areas are then chemically reinforced with a metal until the metal layers in the through-hole grow together and the electrical connection is established.
• a disadvantage of this connection technology is that only thin substrates can be used with moderate temperature loads. The production of the holes in the
• Substrate material is mechanically complex and expensive. Often only certain substrate materials can be used.
• the inventive method with the features of the main claim has the advantage that holes in the narrow arrangement of the IC connections in the substrate are omitted.
• the thickness of the substrate material that can be used is therefore not limited. Unilaterally structured substrates are possible. Thin substrates or film substrates do not suffer any weakening of the substrate workpiece.
• the method allows the use of all inaccurate integrated circuits (ICs), while other flip-chip techniques are mostly restricted to specially pretreated (bumped) ICs.
• Very short conductive connections with good thermal conductivity and improved high-frequency properties of substrates connected according to the invention with the associated components can be carried out. Damage to sensitive components due to heating during soldering is eliminated and plastic parts can get closer be arranged lying on the substrate.
• the process can be automated. By reducing the distance between adjacent connections of the IC component compared to packaged components, substrate material and material for the conductor track and the insulating layers can be saved with a comparable scope of use of the circuit.
• the contact surfaces of the conductor landing surfaces to be connected have to be pretreated in order to direct the reaction and crystallization preferentially to the parts to be connected and to avoid undesired competitive reactions.
• the application of large passivating layers improves the subsequent electrical insulation of the product
• FIG. 1c shows the positioning of the IC component on the substrate
• FIG. 1d shows an IC component on the substrate.
• connection 10 of an unpacked IC component 15 is drawn in FIG.
• the surface of the connection 10 to be contacted has a layer 20 that can be readily metallized.
• the surface of the connections 10 is surrounded by a passivating layer 25.
• FIG. 1b shows a substrate 30 with a conductor track 35 partially covering the surface, to which a spacer 40 is applied such that a free, electrically contactable surface remains as a landing surface 45 on the conductor track 35.
• FIG. 1 c shows an IC component according to FIG. 1 a on a substrate according to FIG. 1 b, the surfaces 20, 45 to be contacted facing one another.
• Positioning is achieved when substrate 30 and IC component 15 are placed on top of one another in accordance with the arrows in FIGS. 1 a and 1 b in such a way that the surfaces of the metallizable layer 20 and the landing surface 45 face each other without contact.
• FIG. 1d shows the connection of an IC component 15 to a substrate 30.
• the electrically conductive material 50 fills the free volume between landing surface 45 and layer 20 that can be metallized. example 1
• a paste containing palladium seeds is applied to the surface of an electrical connection 10 to be contacted using thick-film technology as a metallizable layer 20.
• the copper conductor track 35 is covered with an insulating layer, for example an epoxy resin layer, as a spacer 40, the thickness of which is precisely adjusted on the conductor track 35. It is positioned, as drawn in FIG.
• a conductive substance 50 by simultaneous chemical deposition of nickel on the metallizable layer 20 containing palladium seeds and the copper landing surface 45, according to a method described in WO 94/05139 .
• the deposition takes place until the opposite nickel deposits grow together and an electrical connection of the connection 10 to the conductor track 35 is created.
• the end of the growing together is checked, for example, by assessing the drop shape or measuring the resistance of the connection.
• another electrical component can also be used.
• Example 3 A plurality of connections 10 of the IC component 15 are connected to conductor tracks 35 at the same time, otherwise the procedure is as in Example 1.
• Example 3 A plurality of connections 10 of the IC component 15 are connected to conductor tracks 35 at the same time, otherwise the procedure is as in Example 1.
• the substrate 30 is coated only on one side, the uncoated side, in the case of a sufficiently thick substrate, forming the outer housing wall of a device, on the inner wall of which the IC component 15 is attached, otherwise production is carried out as in Example 1.
• the paste for germinating the metallizable layer 20 is applied with very small connection grids using the pad printing process.
• Precious metals such as Pt, Rh, Pd, Ru, Rh, Au, Ag, Ir, Os, Re or precious metal alloys can be used for seeding, otherwise the procedure is as in Example 1.
• electrical connection 10 AI, Cu, Ni, Ag, Au, Ag / Au-20 or alloy, graphite, Pd conductor 35 conductive plastic Ag / Pd, Sn, Pt, Rh, Ru, Ir, Os, Re
• Spacer 40 PVC, polyurethane, epoxy resin, insulating varnish, polyimide, acrylic resin, acrylic epoxy systems
• Substrate 30 aluminum oxide ceramic, epoxy, ceramic, polyamide, aramid, porcelain, Si, Pertinax, polyester, polyimide, circuit board material, ALN ceramic

Landscapes

• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Wire Bonding (AREA)
• Parts Printed On Printed Circuit Boards (AREA)
• Manufacturing Of Printed Wiring (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (1)

Family

ID=7762506

Family Applications (1)

Country Status (8)

Families Citing this family (3)

Citations (6)

Family Cites Families (11)

• 1995
  • 1995-05-20 DE DE19518659A patent/DE19518659A1/de not_active Withdrawn
• 1996
  • 1996-03-12 ES ES96905709T patent/ES2149454T3/es not_active Expired - Lifetime
  • 1996-03-12 US US08/727,541 patent/US5784779A/en not_active Expired - Fee Related
  • 1996-03-12 JP JP8534436A patent/JPH10503331A/ja active Pending
  • 1996-03-12 KR KR1019970700304A patent/KR970705171A/ko not_active Ceased
  • 1996-03-12 EP EP96905709A patent/EP0771472B1/de not_active Expired - Lifetime
  • 1996-03-12 DE DE59605642T patent/DE59605642D1/de not_active Expired - Fee Related
  • 1996-03-12 WO PCT/DE1996/000432 patent/WO1996036991A1/de not_active Ceased
  • 1996-03-16 TW TW085103252A patent/TW297937B/zh active

Patent Citations (6)

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