WO1996029734A1 - Circuit integre semi-conducteur et procede de fabrication - Google Patents

Circuit integre semi-conducteur et procede de fabrication Download PDF

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Publication number
WO1996029734A1
WO1996029734A1 PCT/JP1995/000501 JP9500501W WO9629734A1 WO 1996029734 A1 WO1996029734 A1 WO 1996029734A1 JP 9500501 W JP9500501 W JP 9500501W WO 9629734 A1 WO9629734 A1 WO 9629734A1
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WIPO (PCT)
Prior art keywords
circuit device
film
integrated circuit
semiconductor integrated
memory cell
Prior art date
Application number
PCT/JP1995/000501
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English (en)
Japanese (ja)
Inventor
Isamu Asano
Makoto Ogasawara
Toshihiro Sekiguchi
Shinji Shimizu
Original Assignee
Hitachi, Ltd.
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Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/000501 priority Critical patent/WO1996029734A1/fr
Publication of WO1996029734A1 publication Critical patent/WO1996029734A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same.
  • the present invention relates to a semiconductor integrated circuit device and a technology for manufacturing the same, and more particularly to a semiconductor integrated circuit device having a DRAM having a large capacity and capable of operating at high speed, and a technology for manufacturing the same.
  • DRAM dynamic random access memory
  • Such a capacitor structure has a structure in which electrodes between two layers of polysilicon are stacked.
  • a capacitor having a three-dimensional structure such as a so-called stacked capacity formed through a capacitive insulating film is employed.
  • a stacked capacitor generally has a structure in which the capacitor electrode is arranged on the memory cell selection MOS FET.In this case, a large storage capacity can be secured with a small occupied area, and a diffusion layer is required in the capacitor component.
  • the feature is that the rate of occurrence of soft errors can be greatly reduced because of the absence of the memory, and the required storage capacity can be reduced.
  • COB Capacitor Over B line
  • a DRAM having such a stacked capacitor is disclosed in, for example, Japanese Patent Application Laid-Open No. Heisei 4-322, 59, Japanese Patent Application Laid-Open No. Hei 5-210 It is described in JP-A-7.
  • a capacitor insulating film and a capacitor counter electrode in a memory cell portion and a gate insulating film and a gate electrode of a transistor in a peripheral circuit portion are made of the same material.
  • a technique for forming at the same time is disclosed.
  • Japanese Patent Application Laid-Open No. 5-120430 discloses a structure in which a peripheral circuit region is provided above a memory cell array region via an interlayer insulating film.
  • Japanese Patent Application Laid-Open No. 2-130957 discloses a method of storing a stack structure from the viewpoint of preventing the MIS • FET element characteristics in a peripheral circuit region from being degraded by heat treatment or the like when forming a stack structure storage capacitor.
  • a technique of forming a source region and a drain region of an MISFET in a peripheral circuit region after forming a capacitor has been disclosed.
  • the gate insulating film of the MOS FET in the peripheral circuit region of the DRAM is formed by the same material and in the same process as the gate insulating film of the selective MOS FET in the memory cell region.
  • dioxide silicon by thermal oxidation (S i 0 2) film is generally used.
  • the capacitance insulating film of the capacitor for example, a silicon nitride film or a laminated film formed by depositing SiO 2 on a silicon nitride film is used.
  • a silicon nitride film or a laminated film formed by depositing SiO 2 on a silicon nitride film is used.
  • the structure of the complex is complicated, the number of forming processes increases and the defect generation rate increases.
  • an object of the present invention is to improve the performance and operating speed of MIS • FET in a peripheral circuit area of a DRAM.
  • Another object of the present invention is to form a capacitor having a large storage capacity without complicating the structure of a capacity in a DRAM memory cell. It is another object of the present invention to form a capacitor having a large storage capacity S without reducing the number of processes for forming a capacitor in a DRAM memory cell.
  • Another object of the present invention is to improve the performance and operation speed of the MISFET in the peripheral circuit region of the DRAM and the like, and to increase the size of the capacitor in the DRAM memory cell without complicating the structure. It is to form a capacitor with storage capacity.
  • Still another object of the present invention is to improve the performance and operating speed of the MISFET in the peripheral circuit region of the DRAM and the like, and to reduce the number of processes for forming the capacity in the memory cells of the DRAM. It is to form a capacity with storage capacity.
  • the present invention relates to a semiconductor integrated circuit having a capacitor over bit line structure in which capacitors of a plurality of memory cells in a memory cell array of a DRAM arranged at least partially on a semiconductor substrate are provided above bit lines.
  • a ferroelectric material having a dielectric constant larger than the dielectric constant of a silicon nitride film, wherein the capacitance insulating film of the capacitor and the gate insulating film of the MIS • FET in a circuit region other than the memory cell array are formed. It consisted of a membrane.
  • the current drive capability can be improved by using a gate insulating film having a large dielectric constant, so that the performance and operating speed of the MISFET can be improved. Can be improved.
  • the capacity of a memory cell array by using a capacitor insulating film having a large dielectric constant, the storage capacity can be increased without making the structure of the capacitor a complicated three-dimensional structure. A capacitor having a large storage capacity can be formed without reducing the number of forming processes in the evening.
  • the present invention also provides a semiconductor integrated circuit device having a capacitor over bit line structure in which capacitors of a plurality of memory cells in a DRAM memory cell array arranged at least in part of a semiconductor substrate are provided above bit lines. , Comprising the following steps.
  • the forming process is simplified as compared with the case where these are formed separately. And the time required for the formation process can be shortened.
  • FIG. 1 is a configuration diagram for explaining a configuration of a semiconductor collecting circuit device according to one embodiment of the present invention
  • FIG. 2 is a main part circuit diagram of the semiconductor integrated circuit device of FIG. 1
  • FIG. FIG. 1 is a cross-sectional view of a main part of the semiconductor integrated circuit device
  • FIGS. 4 to 15 are cross-sectional views of a main part during a manufacturing process of the semiconductor integrated circuit device of FIG. 1
  • FIG. FIG. 2 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment.
  • FIG. 1 is a diagram for explaining a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 2 is a main part circuit diagram of the semiconductor integrated circuit device in FIG. 1
  • FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit device in FIG. 1
  • FIG. 2 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step;
  • the semiconductor integrated circuit device is, for example, a 64 Mbit DRAM.
  • FIG. 1 shows a semiconductor chip on which the DRAM is formed.
  • a memory cell array 2 is arranged and surrounding the memory cell array 2, such as a row decoder circuit 3, a column decoder circuit 4, an I / O control circuit 5, and a control circuit 6, etc.
  • Edge circuits are arranged.
  • a plurality of lead lines 2WL and a plurality of bit lines 2BL are arranged so as to cross each other.
  • FIG. 1 only one word line 2WL and one bit line 2BL are shown for easy viewing.
  • a memory cell 2 MC is arranged near the intersection of each word line 2WL and bit line 2BL. That is, a plurality of memory cells 2 MC are regularly arranged in the memory cell array 2 along the vertical and horizontal directions in FIG. As shown in FIG. 2, each memory cell 2 MC is composed of, for example, one MOSS FET 7 and one capacitor 8.
  • the row decoder circuit 3 shown in FIG. 1 is configured to select one of a plurality of read lines 2WL in the memory cell array 2 based on a row address input signal input to the row decoder circuit 3 from outside the semiconductor chip 1. This is a circuit for selecting the word line 2WL. Then, when a predetermined word line 2WL is selected by the row decoder circuit 3, the data of the memory cell 2MC connected to the word line 2WL is transferred to the bit line 2BL. .
  • the column decoder circuit 4 outputs a predetermined bit line from a plurality of bit lines 2BL in the memory cell array 2 based on a column address input signal input to the column decoder circuit 4 from outside the semiconductor chip 1. 2 This circuit selects BL. When a predetermined bit line 2BL is selected by the column decoder circuit 4, the data transferred to the bit line 2BL is transferred to the output side.
  • the I / O control circuit 5 controls a data read operation and a data write operation in the memory cell 2MC selected by the row decoder circuit 3 and the column decoder circuit 4.
  • the control circuit 5 transfers the data in the memory cell 2 MC to the output terminal in the case of a data read operation, and transfers and stores the input data in the memory cell 2 MC in the case of a data write operation. It has a structure.
  • the control circuit 6 is a circuit that controls the entire semiconductor transplantation circuit device S, performs chip selection control, and the like.
  • FIG. 3 shows a cross-sectional view of a principal part of such a semiconductor chip 1.
  • FIG. 3 is a cross-sectional view of a main part of the memory cell array 2 and the peripheral circuit area (circuit area other than the memory cell array) 9.
  • the semiconductor substrate 10 constituting the semiconductor chip 1 is made of, for example, a p-type silicon (Si) single crystal, and a p-well 11 is formed thereon.
  • p-type impurity boron is introduced into the p-well 11.
  • an n-well is also formed above the semiconductor substrate 10.
  • n-type impurities such as antimony, phosphorus, or arsenic (As) are introduced into the n-well.
  • the semiconductor substrate 10 has a recess array (Recess Array) structure. That is, the upper surface force of the semiconductor substrate 8 in the memory cell array 2 ⁇ , and the lower surface is formed at a position lower than the upper surface of the semiconductor substrate 10 in the peripheral circuit region 9.
  • silicon dioxide S
  • the element formation region surrounded by the field insulating film 12 includes the memory cell described above.
  • MOS ⁇ FET7 constituting 2 MC is formed.
  • the MOS FET 7 is, for example, an n-channel MOS FET, and has a pair of semiconductor regions 7 a and 7 b formed on the semiconductor substrate 10 and a pair of semiconductor regions 7 a and 7 b formed on the semiconductor substrate 10. And a gate electrode 7d formed on the gate insulating film 7c.
  • the semiconductor regions 7a and 7b are formed above the semiconductor substrate 10 so as to be interspersed with each other.
  • An operation channel is formed between the pair of semiconductor regions 7a and 7b.
  • Each of the semiconductor regions 7a and 7b is a low-concentration region 7 formed on the gate electrode 7d side. a 1. 7 bl and high concentration regions 7 a2 and 7 b2 formed outside. That is, an LDD (Lightly Doped Drain) structure is formed.
  • LDD Lightly Doped Drain
  • the low concentration regions 7a1 and 7bl for example, As of an n-type impurity is introduced, and in the high concentration region 7a2.7b2, for example, As of an n-type impurity is introduced.
  • Gate insulation ⁇ 7 c are made of, for example, S i 0 2.
  • the gate electrode 7d is a part of the word line 2WL, and is made of, for example, low-resistance polysilicon.
  • a side wall 13 and a cap insulating film 14 are formed on the side and top surfaces of the gate electrode 7d, respectively.
  • Sai Douoru 1 3 and Canon-up insulation ⁇ 1 4 is made of, for example, S i 0 2.
  • an insulating film 15 a made of, for example, BPSG (Boro Phosoho Silicate Glass) is deposited on the semiconductor substrate 10, thereby forming the gate electrode 7 d and the lead wire 2. WL covered? ! Have been. ⁇ The upper surface of the edge film 15a is formed flat.
  • the wiring 16 is formed on the upper surface of the insulating film 15a.
  • the wiring 16 is a wiring constituting the above-mentioned bit line 2BL.
  • a tungsten silicide (WSi 2 ) is formed on a conductor film 16a made of polysilicon or the like into which phosphorus is introduced.
  • the conductor film 16b is deposited.
  • the wiring 16 is connected in a compressive manner to the semiconductor region 7b of the MOS FET 7 through a connection hole 17a formed in the insulating film 15a.
  • an insulating film 15b made of, for example, BPSG is deposited on the insulating film 15a, and the wiring 16 is thereby displayed.
  • the upper surface of the insulating film 15b is also formed flat.
  • the capacitor 8 of the memory cell 2MC is formed on the insulating film 15b. That is, the semiconductor integrated circuit device of the present embodiment has a so-called C0B structure in which the capacity 8 is arranged on the bit line 2BL.
  • the capacity 8 has a lower electrode 8a, a S insulating film 8b formed on the upper side, and an upper electrode 8c formed on the upper layer.
  • the lower electrode 8a and the upper electrode 8c are made of, for example, a metal such as platinum (Pt).
  • the lower electrode 8a has a barrier film 18 provided thereunder and an insulating film 15a, It is electrically connected to the semiconductor region 7a of the MOS FET 7 through the connection hole 17b formed in the hole 15b and the conductor film 19 embedded in the connection hole 17b.
  • the barrier film 18 is made of, for example, tantalum (Ta) or titanium nitride (TiN), and the conductor film 19 is made of, for example, polysilicon into which phosphorus has been introduced.
  • Si atoms in the conductor film 19 move to the lower electrode 8 a side and bend out, and conversely, Pt atoms in the lower electrode 8 a move to the conductor film 19 side and deposit. It is a film to prevent rubbing.
  • the capacitor insulating film 8 b is, for example, barium ⁇ Su Bok port Nchiumu 'titanium (B a, -, S r , T i 0 3 ( hereinafter, referred to as B ST)), such as It consists of a barium titanate-based dielectric film.
  • B ST barium ⁇ Su Bok port Nchiumu 'titanium
  • X 0. 3 of the BST film, i.e., B a 0. 7 S r 0. 3 T i 0 3 film have been used
  • the relative dielectric constant is, for example, about 800.
  • the use of the ferroelectric film as the capacitance / edge film 8b of the capacitor 8 makes it possible to provide a capacitor having a simple structure having a large capacitance with a small occupation area. It is possible.
  • a cap insulating film P1 made of, for example, SiO 2 is formed on the upper electrode 8c.
  • MIS FET 20 constituting the above-described peripheral circuit is formed on the semiconductor substrate 10 in the peripheral circuit region 9.
  • the MIS • FET 20 is, for example, an n-channel MIS • FET 20, and includes a pair of semiconductor regions 20 a. 20 b formed above the semiconductor substrate 10, and And a gate electrode 20d formed on the gate insulating film 20c.
  • the semiconductor regions 20a and 20b are formed on the semiconductor substrate 10 so as to be spaced apart from each other.
  • An operation channel is formed between the pair of semiconductor regions 20a and 20b.
  • Each of the semiconductor regions 20 a and 20 b has a low-concentration region 20 al and 20 bl formed on the gate electrode 20 d side and a high-concentration region 20 a 2 formed outside thereof. 2 0 b 2 and. That is, an LDD structure is formed.
  • This low concentration area 2 For example, As of an n-type impurity is introduced into 0a1.20b1, and As of an n-type impurity is introduced into the high concentration region 20a2.20b2, for example.
  • the peripheral circuit is constituted by the gate insulating film 20 c of MIS ⁇ FET 20, for example, BST. That is, in the present embodiment, the gate insulating film 20 c of MIS ⁇ F ⁇ 20 is strong, and is made of the same material as the above-described capacitive insulating film 8 b of the capacity 8.
  • W is the gate width
  • C is the capacitance of the gate insulating film
  • VG is the gate voltage
  • Vth is the threshold voltage
  • VD is the drain voltage
  • L is the gate length.
  • the drain current I ds of MIS • FET 20 increases as the dielectric constant of the gate insulating film 20c increases. Therefore, in the present embodiment, the current drive capability of the MISFET 20 is improved by forming the gate insulating film 20c of the MISFET 20 with a high dielectric film such as BST. It is possible to make it. As a result, it has become possible to promote the operation speed of the semiconductor integrated circuit device.
  • the gate electrode 20d is made of a metal such as Pt, for example. As a result, the resistance of the gate electrode 20d can be significantly reduced, so that the operation speed of the semiconductor integrated circuit device can be improved.
  • the side surface of the gate Bok electrode 2 0 d in order to constitute the LDD structure, for example, cyclic Douoru 2 1 consisting of S i 0 2 is formed.
  • On the upper surface of the gate Bok electrode 2 0 d for example caps insulating film P1 consisting of S i 0 2 is formed.
  • a p-channel MIS • FET is also formed in the peripheral circuit region 9, and the p-channel MIS.FET and the n-channel MIS • FET are formed.
  • 20 forms a CMOS (Complementary M0S) circuit. Gate insulation film and gate electrode of this p-channel MISFET The gate insulating film 20c and the gate electrode 20d of the MIS. FET 20 are also made of the same material.
  • Such semiconductor substrate 1 0 on, for example, S i 0 2 made of an insulating film 2 2 a are compost ⁇ , this upper electrode 8 c of Yotsute capacitor 8, the insulating film 1 5 b and M 1 S ⁇ FE Ding 20 is coated.
  • first wiring 23a1 and 23a2 made of, for example, tungsten are formed on this insulating film 22a.
  • the first layer wiring 23 a 1 is electrically connected to the wiring 16 and the semiconductor region 20 a of the MISFET 20 through a contact hole 17 c formed in the insulating film 22 a.
  • the first eyebrow wiring 23 a 2 is electrically connected to the semiconductor region 20 b of the MIS FET 20 through a connection hole 17 c formed in the insulating film 22 a.
  • an insulating film 22b made of, for example, Si0 is deposited, thereby covering the first-layer wirings 23a1 and 23a2.
  • second S wirings 23b1 to 23b3 made of, for example, an A1-Si-Cu alloy are formed.
  • the second layer wiring 2 3 b 3 is electrically connected to the first layer wiring 2 3 a 1 through a conductor film 24 made of tungsten or the like embedded in a connection hole 17 d formed in the insulating film 22 b.
  • S i 0 2 surface protective film 2 5 made of are deposited, to the I connexion second layer wiring 2 3 b 1 ⁇ 2 2 b 3 which is covered I have.
  • a semiconductor substrate 1 0 on the main surface consisting of p- form of S i monocrystal, for example S i 0 2 consists pad film 2 6 a and for example nitride silicon co down
  • an oxidation-resistant film pattern 27 a covering the peripheral circuit region 9 is formed by etching away the film portion of the oxidation-resistant film in the memory cell array 2.
  • an insulating film 28 is formed on the region of the semiconductor substrate 10 exposed from the oxidation resistant film pattern 27a. Form selectively.
  • the pad film 26a and the insulating film 28 are removed by etching, as shown in FIG.
  • a recess structure is formed on the surface.
  • a smooth slope is formed in the boundary area between the memory cell array 2 and the peripheral circuit area 9. The recess step A in this boundary region is, for example, about 0.3 m.
  • a pad film 26 b is formed on the main surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 is subjected to a thermal oxidation treatment, as shown in FIG. As shown in FIG. 7, a field insulating film 12 is selectively formed in an element isolation region on a main surface of a semiconductor substrate 10.
  • a gate insulating film 7c is formed on the semiconductor substrate 10 in the memory cell array 2 by a thermal oxidation method or the like, and then, for example, a conductive film made of polysilicon into which phosphorus is introduced is formed on the semiconductor substrate 10. Is deposited by a CVD method or the like, and an insulating film made of, for example, SiO 2 is further deposited on the upper surface by the CVD method or the like.
  • a photo resist pattern is formed on the insulating film by photolithography technology, and then the semiconductor substrate 10 is subjected to dry etching or the like using the photo resist pattern as an etching mask. Then, a cap insulating film 14 is formed by patterning the insulating film.
  • the semiconductor substrate 10 is subjected to dry etching or the like using the cap insulating film 14 as an etching mask, and the lower conductive film of the cap insulating film 14 is patterned.
  • a lead line 2WL is formed. That is, a gate electrode 7d is formed.
  • a photoresist pattern 29a is formed in the peripheral circuit region 9, and then, for example, As of an n-type impurity is implanted into the semiconductor substrate 10 by ion implantation at a low degree of portability. Drive in.
  • a thin film made of, for example, SiO 2 is deposited on the semiconductor substrate 10 by a CVD method or the like, and the insulating film is dried by a dry etching method or the like.
  • a side wall 13 is formed on the side surface of the gate electrode 7 d (word line 2 WL).
  • As of an n-type impurity is implanted into the semiconductor substrate 10 by an ion implantation method or the like, and the semiconductor substrate 10 is formed.
  • semiconductor regions 7a1, 7a2.7b1, 7b2 are formed on the semiconductor substrate 10 above.
  • the MOS FET 7 having the LDD structure is formed.
  • connection holes 17a and 17b are formed in the film 15a so that the semiconductor regions 7a and 7b of the MOS FET 7 are exposed by a dry etching method or the like.
  • a conductor film made of, for example, polysilicon into which phosphorus is introduced is deposited on the semiconductor substrate 10 by a CVD method or the like, and a conductor film made of, for example, WSi 2 is deposited on the upper surface thereof by a CVD method or the like.
  • a conductive film made of introduced poly silicon of the Li down to form a bit Bok lines by patterning the conductive film made of WS i 2 by Huo Application Benefits lithography techniques.
  • the photolithography technique referred to here is a process in which a photo resist pattern is formed by using an exposure process, and the conductive film is patterned by a dry etching method or the like using the photo resist pattern as an etching mask. Process.
  • an insulating film 15b made of, for example, BPSG or the like is deposited on the insulating film 15a by a CVD method or the like to cover the bit lines, and the upper surface of the insulating film 15b is reflowed by heat treatment. To make it sufficiently flat.
  • connection hole 17b is formed in the insulating film 15b so as to expose the semiconductor regions a and 7b of the MOSS FET 7 by a dry etching method or the like.
  • a conductor film made of, for example, polysilicon into which phosphorus is introduced is deposited on the insulating film 15b by a CVD method or the like, and the conductor film is etched back by a dry etching method or the like.
  • c embed the conductive film 1 9 in contact ⁇ 1 7 in b, sputtering to ⁇ film 1 on 5 b, for example, a metal film made of T a or T i N
  • the barrier film 18 is formed by patterning the metal film by photolithography technology.
  • the barrier film 18 is formed by a photo resist pattern of a ridge smaller than the lower electrode 8a so that the barrier film 18 is not exposed from the side surface of the lower electrode 8a to be formed later.
  • the photolithography technique referred to here includes a step of forming a photo resist pattern using an exposure process, and a step of patterning a metal film by a dry etching method or the like using the photo resist pattern as an etching mask. Contains.
  • a metal film made of, for example, Pt is deposited on the insulating film 15b by a sputtering method or the like, and the metal film is patterned by photolithography to form the lower electrode 8a.
  • the photolithography technique referred to here is a process of forming a photo resist pattern using an exposure process, and patterning a metal film by a dry etching method or the like using the photo resist pattern as an etching mask. And the step of performing.
  • the dielectric film 30 made of BST having a ratio of about 800 is formed, for example, by the SOG (Spin On Glass) method, the sol-gel method, the sputtering method, the evaporation method, or the MOCVD (Metal Organic Chemi l Vapor deposition method).
  • the reason why the insulating film made of silicon nitride was formed on the exposed surface of the semiconductor substrate 10 before the formation of the dielectric film 30 was that the dielectric film 30 was formed on the exposed surface of the semiconductor substrate 10. This is to prevent the exposed surface of the semiconductor substrate 10 from being oxidized more strongly than necessary if formed directly.
  • a metal film 31 such as Pt is deposited on the dielectric film 30 by sputtering or the like, and an insulating film P is deposited on the upper surface by CVD or the like c .
  • the memory cell array 2 covers the upper electrode forming region of the capacitor!
  • a photo resist pattern 29 c 2 is formed in the peripheral circuit region 9 by photolithography technology so as to cover the gate electrode formation region. I do.
  • the step of forming a photo resist pattern involving a series of processes such as exposure, development, washing, and drying can be reduced, so that the upper electrode 8c of the capacitor 8 and the S insulating film 8b can be reduced. Therefore, the formation process can be simplified and the formation time can be shortened as compared with the case where the gate electrode 7 d and the gate insulating film 7 c of the MOS FET 7 are formed separately. I have.
  • the semiconductor regions 20a and 20b of the MIS FET 20 constituting the peripheral circuit are formed as follows, for example. This step will be described with reference to FIGS. 11 to 14. Note that in these figures, the p-channel type MIS FET described above in the peripheral circuit region 9 is also shown for easy understanding. Note that 11 n in FIG. 11 is n-well, and for example, contains phosphorus or As of an n-type impurity.
  • 20 p a 1.20 p b 1 is a low-concentration region of the channel type MIS ⁇ FET.
  • 20 pc is a p-channel-type gate insulating film of MIS • FET, and is formed of the same material at the same time as the gate insulating film 20 c of MIS′FET 20.
  • 20 pd is a p-channel type MIS / FET gate electrode and is formed of the same material at the same time as the gate electrode 0 d of the MIS / FET 20.
  • a photo-resist pattern 29 d for exposing, for example, an n-channel MIS / FET formation region is formed on the semiconductor substrate 10 by photolithography. Formed by technology.
  • the photo resist pattern 29d as a mask for ion implantation, for example, As ions of an n-type impurity are introduced into the semiconductor substrate 10 by an ion implantation method or the like.
  • the dose at this time is, for example, about 2 to 4 xl 0 15 atoms Z cm 2 .
  • a photo-resist pattern 29e for exposing a p-channel type MIS / FET formation region is formed as shown in FIG. It is formed by lithography technology.
  • boron ions of a p-type impurity are introduced into the semiconductor substrate 10 by an ion implantation method or the like. Dose at this time is, for example, 2 ⁇ 4 X 1 0 '5 at om sZcm 2 about.
  • the semiconductor after removing the follower Bok registry pattern 2 9 e for example, using C 0 2 gas laser or tungsten halogen lamp with a short wavelength region and Bok Chikara' wave length, for example more than 1 m of the light
  • the semiconductor substrate 10 is subjected to an annealing treatment by irradiating the entire main surface of the substrate 10.
  • the ion implantation region in MIS.FET20.20p has an amorphous state, and therefore has a larger light absorption coefficient than other regions.
  • the upper electrode 8c of the capacitor 8 and the gate electrodes 20d.20pd of the MIS FETs 20 and 20p reflect light because they are made of metal.
  • the semiconductor substrate 1 0 on, for example, after the S i 0 2 Tona Ru ⁇ film 2 2 a deposited by CVD method or the like, to flatten by heat treatment its upper surface.
  • the film forming temperature and the flattening temperature of the insulating film 22a are set to temperatures at which the dielectric constant of the capacitive insulating film 8b and the gate insulating film 20c made of a dielectric film does not decrease.
  • a connection hole 17c is formed in the insulating film 22a by photolithography so that the wiring 16 and the semiconductor region 20a.20b of the MISFET 20 are exposed. I do.
  • the photolithography technique referred to here is a process in which a photo resist pattern is formed using an exposure process, and the insulating film 22a is subjected to a dry etching method using the photo resist pattern as an etching mask. And the like.
  • a metal film made of, for example, tungsten or the like is deposited on the semiconductor substrate 10 by a sputtering method or the like, and the metal film is patterned by photolithography to obtain a structure shown in FIG. First layer wirings 23 ai and 23 a 2 shown in FIG.
  • the photolithography technique referred to here is a process in which a photo resist pattern is formed using an exposure process, and a metal film is formed by a dry etching method using the photo resist pattern as an etching mask. Patterning.
  • the wiring 16 constituting the bit line 2 BL of the memory cell array 2 is directly connected to the semiconductor region 20 a of the MISFET 20 in the peripheral circuit region 9. Since it is not possible to make this connection, it is structured to be electrically connected through the first wiring 23 al.
  • the ⁇ film 2 on 2 a for example, after the S i 0 2 made of an insulating film 2 2 b is deposited by a CVD method or the like, to flatten by heat treatment its upper surface.
  • the film forming temperature and the flattening temperature of the insulating film 22b are set to temperatures at which the dielectric constants of the capacitor insulating film 8b and the gate insulating film 20c made of a dielectric film do not decrease.
  • connection hole 17d for exposing the first-layer wiring 23a1 is formed by photolithography in the insulating film 22b, and a stainless steel is formed in the connection hole 17d.
  • a conductive film 24 such as
  • the photolithography technique referred to here is a process in which a photo resist pattern is formed by using an exposure process, and the edge film 22b is dry-etched using the photo resist pattern as an etching mask. And a step of etching by an etching method or the like.
  • a metal film made of, for example, an A 1 —Si—Cu alloy is deposited on the semiconductor substrate 10 by a sputtering method or the like, and the metal film is formed by photolithography.
  • the second S wirings 23 bl to 23 b3 are formed by patterning according to.
  • the film formation temperature and the flattening temperature are set so that the dielectric constants of the capacitor insulating film 8b and the gate insulating film 7c made of a dielectric film do not decrease.
  • the MISFET 20 and 20p gate insulating films 20c and 20pc that make up the peripheral circuit are made of a ferroelectric film with a large dielectric constant. Since the current drive capability of 0, 20 p can be improved, it is possible to improve the performance and operating speed of the MIS.
  • FET 20.2 Op that is, the CMOS circuit).
  • the MIS FETs 20 and 20p Since the gate electrodes 20d and 20pd of the MIS FETs 20 and 20p constituting the peripheral circuit are made of metal, the MIS FETs 20 and 20p (i.e. The performance and operating speed of CMOS circuits can be improved.
  • the ion implantation region selectively provides good light absorption and activation.
  • the capacitance insulating film 8b and the gate due to the formation of the semiconductor regions 20a, 20b, 20pa, and 20pb of the M1S.FETs 20 and 20p can be formed. It is possible to prevent the dielectric constant of the insulating films 20 c and 20 pc from lowering.
  • the upper electrode 8c of the capacitor 8 in the memory cell 2 and the gate electrodes 20d, 20pd of the MISFETs 20 and 20p in the peripheral circuit region 9 in the peripheral circuit region 9 are made of metal, MIS 'FET 20a, 20b.
  • the gate electrode 20 d. 20 pd reflects light, and the capacitance insulating film 8 b and the gate insulating film 20 d, 20 pd are hardly heated.
  • the decrease in the dielectric constant of the S insulating film 8b and the gate insulating films 20d, 20pd due to the formation of the semiconductor regions 20a, 20b, 20pa. It can be prevented.
  • the capacitor 8 having a large storage capacity S can be formed without increasing the number of processes for forming the capacitor 8.
  • FIG. 16 is a sectional view of a principal part of a semiconductor integrated circuit device according to another embodiment of the present invention.
  • no recess structure is formed in the semiconductor substrate 10. That is, the level of the main surface of the semiconductor substrate 10 in the memory cell array 2 is equal to the level of the main surface of the semiconductor substrate 10 in the peripheral circuit region 9:
  • the manufacturing process also has a recess structure. Except for the forming process, the embodiment is the same as the above-described embodiment, and the material of each component is also the same as the above-described embodiment. In this embodiment as well, it is possible to obtain the same effects as in the above embodiment. Next, another embodiment of the present invention will be described. This embodiment relates to the structure and manufacturing process of the semiconductor integrated circuit device described above with reference to FIG. 3 or FIG. This is equivalent to the embodiment.
  • the gate edge of the MIS • FET 20 that constitutes the capacitor insulating film 8b of the capacitor 8 and the peripheral circuit of the peripheral circuit region 9 in the memory cell array 2 of FIG. 3 or FIG. film 2 0 c materials unlike the above embodiment, for example, P b Z r T i 0 3 ( hereinafter, referred to as PZT) are formed by.
  • the dielectric film constituting the capacitor film 8b in this case has, for example, a solid bushing structure, and as a result, dielectric polarization occurs.
  • the surface of the lower electrode 8a is coated with a thin film made of, for example, ruthenium oxide (RuOx) or iridium oxide (IrOx). Is also good.
  • the gate insulating film 20c of the MISFET 20 has a non-oriented (amorphous) insulating film made of silicon nitride underneath, so that the crystallinity is in a random state. However, it does not have a perevskite structure. However, in this case, it is set so that a voltage in a range where dielectric polarization does not occur in the gate insulating film 20c is applied to the gate electrode 20d.
  • the insulating film 20c is composed of different ferroelectric films.
  • the capacitor insulating film 8 b is made of, for example, PZT
  • the gate insulating film 20 c of the MLS ⁇ FE 20 is made of, for example, BST.
  • the electrode 8c and the gate electrode 20d of the MIS * FET 20 are made of, for example, a metal film such as Pt as in the above embodiment.
  • the current drive capability of the MIS FET 20 is improved by forming the gate insulating film 20 c of the MIS FET 20 that constitutes the peripheral circuit with a ferroelectric film having a large dielectric constant. Since the power can be improved, the performance and operating speed of the MIS.FET 20 can be improved.
  • the upper electrode 8c of the capacitor 8 in the memory cell 2 and the gate electrodes 20d, 20pd of the MISFET 20.20p in the peripheral circuit area 9 in the peripheral circuit area 9 are made of metal, MIS 'FET 20 a, 20 b, 20 p a. During heat treatment using light to form 20 pb, the upper electrode 8 c and the gate are formed. The electrode 20 d.
  • the capacity 8 having a large storage capacity can be formed without reducing the number of processes for forming the capacitor 8.
  • a semiconductor integrated circuit device having a DRAM with high performance and high reliability can be manufactured with high yield without increasing the number of forming processes. .
  • the capacitance insulating film of the capacitor and the gate insulating film of the MIS / FET are constituted by BS or BS.
  • the present invention is not limited to this, and various changes are made.
  • titanium oxide Ti i 0 3
  • nitric acid potassium KN0 3
  • titanate burr ⁇ beam B a T i 0 3
  • titanium Sens preparative strontium S r T i 0 3
  • bismuth titanate B i 4 T i 3 0 12
  • Germa two ⁇ beam lead P b 5 G e 3 OH
  • lead titanate Pb T i 0 3
  • titanate zirconate two Umurantan lead P b L a Z r T i 0 3
  • other strong may be a dielectric material such as.
  • the capacitance insulating film of the capacitor is formed of PZT or the like and the gate insulating film of the MISFET for forming the peripheral circuit is formed of BST or the like will be described.
  • the present invention is not limited to this. That is, the capacity ⁇ film of the capacitor constituted by BST, etc., a gate one Bok ⁇ film MIS ⁇ FET for the peripheral circuit formation may be constituted by PZT, etc. c
  • gate insulating film Is formed in such a state that polarization does not occur, or a voltage in a range where polarization does not occur is applied to the gate electrode.
  • the present invention is not limited to this, and various applications are possible.
  • the present invention is applied to a semiconductor integrated circuit device in which a bipolar transistor and an MISFET are formed on the same semiconductor substrate. good.
  • the present invention can be applied to another semiconductor integrated circuit device such as a memory circuit with logic in which a DRAM and a logic circuit are formed on the same semiconductor substrate or a method of manufacturing the same.
  • a semiconductor integrated circuit device such as a memory circuit with logic in which a DRAM and a logic circuit are formed on the same semiconductor substrate or a method of manufacturing the same.
  • all or part of the MIS FET in the logic circuit area may be formed similarly to the MIS FET of the peripheral circuit configuration described in the above embodiment.
  • all or part of the gate insulating film of the MIS / FET for the logic circuit configuration is formed simultaneously with the capacitance insulating film formed of the capacitor dielectric film, and the gate of the MIS / FET for the logic circuit configuration is formed.
  • All or part of the electrode may be formed simultaneously with the upper electrode made of metal of the capacitor.
  • the present invention has the following effects because it is configured as described above.
  • the current drive capability can be improved by using a gate insulating film with a large dielectric constant.
  • the formation process is more complicated than when these are formed separately. Can be simplified, and the formation time can be shortened.
  • the semiconductor integrated circuit device according to the present invention and the manufacturing technology thereof
  • the present invention is effective for use in a semiconductor integrated circuit device provided on the same semiconductor chip and a method of manufacturing the same, and in particular, a semiconductor integrated circuit device having a DRAM that is large-scale and requires high-speed operation and a method of manufacturing the same. Suitable for use in methods.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un circuit intégré semi-conducteur à structure 'condensateur sur ligne de bits' dans laquelle les condensateurs (8) des cellules mémoires (2) de la mémoire RAM dynamique montées sur le substrat du semi-conducteur (10) sont placés au-dessus des lignes de bits (2BL). Le film d'isolation de capacité (8b) de chaque condensateur (8) est le film d'isolation de porte (20c) d'un MOSFET (20) utilisé pour former un circuit périphérique sont des films ferroélectriques en titanate de baryum. Le film d'isolation de capacité (8b) et l'électrode supérieure (8c) du condensateur (8) de même que le film d'isolation de porte (20c) et l'électrode de porte (20d) du MOSFET (20), qui sont situés dans la zone du circuit périphérique (9) sont gravés simultanément. Ce circuit intégré semi-conducteur à la fois performant et fiable est très facile à réaliser.
PCT/JP1995/000501 1995-03-20 1995-03-20 Circuit integre semi-conducteur et procede de fabrication WO1996029734A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/000501 WO1996029734A1 (fr) 1995-03-20 1995-03-20 Circuit integre semi-conducteur et procede de fabrication

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Application Number Priority Date Filing Date Title
PCT/JP1995/000501 WO1996029734A1 (fr) 1995-03-20 1995-03-20 Circuit integre semi-conducteur et procede de fabrication

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WO1996029734A1 true WO1996029734A1 (fr) 1996-09-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106434B2 (en) 2004-12-21 2012-01-31 Nxp B.V. Semiconductor device with a superparaelectric gate insulator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04322459A (ja) * 1991-04-23 1992-11-12 Nec Corp 半導体記憶装置およびその製造方法
JPH05243562A (ja) * 1991-11-06 1993-09-21 Ramtron Internatl Corp 電界効果トランジスタ、これに用いる誘電体積層構造およびこれらの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04322459A (ja) * 1991-04-23 1992-11-12 Nec Corp 半導体記憶装置およびその製造方法
JPH05243562A (ja) * 1991-11-06 1993-09-21 Ramtron Internatl Corp 電界効果トランジスタ、これに用いる誘電体積層構造およびこれらの製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTION ON ELECTRON DEVICES, Vol. 39, No. 9, September 1992, (New York, U.S.) R. MOAZZAMI et al., "Electrical Characteristics of Ferroelectric PZT Thin Films for DRAM Applications", p. 2044-2049. *
NIKKEI MICRODEVICE, No. 104, 1 February 1994, NIKKEI BUSINESS PUBLICATIONS, INC., (TOKYO), p. 99-103. *
NIKKEI MICRODEVICE, No. 117, 1 March 1995, NIKKEI BUSINESS PUBLICATIONS, INC., (TOKYO), p. 25, 41-45. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106434B2 (en) 2004-12-21 2012-01-31 Nxp B.V. Semiconductor device with a superparaelectric gate insulator

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