WO1996008868A3 - Circuit de temporisation et systeme de transmission utilisant un tel circuit - Google Patents
Circuit de temporisation et systeme de transmission utilisant un tel circuit Download PDFInfo
- Publication number
- WO1996008868A3 WO1996008868A3 PCT/IB1995/000739 IB9500739W WO9608868A3 WO 1996008868 A3 WO1996008868 A3 WO 1996008868A3 IB 9500739 W IB9500739 W IB 9500739W WO 9608868 A3 WO9608868 A3 WO 9608868A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- delay unit
- transmission system
- control signal
- signal controlling
- delay
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8510043A JPH09505966A (ja) | 1994-09-15 | 1995-09-06 | 遅延ユニット及びそのような遅延ユニットを用いた送信システム |
EP95929185A EP0729671A1 (fr) | 1994-09-15 | 1995-09-06 | Circuit de temporisation et systeme de transmission utilisant un tel circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94202662 | 1994-09-15 | ||
EP94202662.6 | 1994-09-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1996008868A2 WO1996008868A2 (fr) | 1996-03-21 |
WO1996008868A3 true WO1996008868A3 (fr) | 1996-05-30 |
Family
ID=8217197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1995/000739 WO1996008868A2 (fr) | 1994-09-15 | 1995-09-06 | Circuit de temporisation et systeme de transmission utilisant un tel circuit |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0729671A1 (fr) |
CN (1) | CN1137845A (fr) |
WO (1) | WO1996008868A2 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5974103A (en) * | 1996-07-01 | 1999-10-26 | Sun Microsystems, Inc. | Deterministic exchange of data between synchronised systems separated by a distance |
DE19908929A1 (de) * | 1999-03-02 | 2000-09-21 | Headroom Videotechnik Gmbh | Verfahren zur Synchronisation eines Übertragungsgerätes der Telekommunikationstechnik |
KR100624296B1 (ko) * | 2004-11-08 | 2006-09-19 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
DE102012211178B4 (de) | 2011-06-29 | 2022-06-30 | Skyworks Solutions, Inc. | Dynamische Zeitangleichung von Tonsignalen in Simultanausstrahlungsradioempfängern |
CN105262462B (zh) * | 2015-10-21 | 2018-03-20 | 圣邦微电子(北京)股份有限公司 | 一种用于集成电路的数字延时实现方法及电路 |
CN109900971B (zh) * | 2017-12-11 | 2023-01-24 | 长鑫存储技术有限公司 | 脉冲信号的处理方法、装置以及半导体存储器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922141A (en) * | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
US5015872A (en) * | 1988-07-06 | 1991-05-14 | Ant Nachrichtentechnik Gmbh | Method and circuit arrangement for generating a phase shifted clock pulse signal |
US5272694A (en) * | 1991-03-21 | 1993-12-21 | France Telecom | Synchronization of terminal stations in a multirate half-duplex tree-structured network |
-
1995
- 1995-09-06 EP EP95929185A patent/EP0729671A1/fr not_active Withdrawn
- 1995-09-06 WO PCT/IB1995/000739 patent/WO1996008868A2/fr not_active Application Discontinuation
- 1995-09-06 CN CN 95191080 patent/CN1137845A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922141A (en) * | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
US5015872A (en) * | 1988-07-06 | 1991-05-14 | Ant Nachrichtentechnik Gmbh | Method and circuit arrangement for generating a phase shifted clock pulse signal |
US5272694A (en) * | 1991-03-21 | 1993-12-21 | France Telecom | Synchronization of terminal stations in a multirate half-duplex tree-structured network |
Non-Patent Citations (2)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, Volume 19, No. 8, January 1977, W.F. MCCARTHY et al., "High-Frequency Analog Electronic Delay Using Phase-Locked-Loop Techniques", page 3131 - page 3132. * |
PATENT ABSTRACTS OF JAPAN, Vol. 13, No. 198, E-756; & JP,A,1 019 822, (NEC. CORP.), 23 January 1989. * |
Also Published As
Publication number | Publication date |
---|---|
CN1137845A (zh) | 1996-12-11 |
EP0729671A1 (fr) | 1996-09-04 |
WO1996008868A2 (fr) | 1996-03-21 |
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