EP0729671A1 - Circuit de temporisation et systeme de transmission utilisant un tel circuit - Google Patents

Circuit de temporisation et systeme de transmission utilisant un tel circuit

Info

Publication number
EP0729671A1
EP0729671A1 EP95929185A EP95929185A EP0729671A1 EP 0729671 A1 EP0729671 A1 EP 0729671A1 EP 95929185 A EP95929185 A EP 95929185A EP 95929185 A EP95929185 A EP 95929185A EP 0729671 A1 EP0729671 A1 EP 0729671A1
Authority
EP
European Patent Office
Prior art keywords
signal
control signal
phase
phase shift
delay unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95929185A
Other languages
German (de)
English (en)
Inventor
Hendricus Theodorus Gerard M Penning De Vries
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP95929185A priority Critical patent/EP0729671A1/fr
Publication of EP0729671A1 publication Critical patent/EP0729671A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's

Definitions

  • the invention is related to a delay unit for delaying digital symbols, com ⁇ prising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal.
  • the invention is also related to a transmission system and a secondary station for such a transmission system using such a delay unit.
  • a delay unit according to the preamble is known from KOKAI 64-19822, published at January 23, 1989.
  • Such a delay unit can be used in many applications in which a sequence of digital symbols has to be delayed over a certain amount of time. There exist several ways to delay a signal over a certain amount of time.
  • a very well known possibility is the use of analog all pass filters comprising of resistors, capacitors and/or inductors.
  • Such delay units may require the use of precision elements to avoid the inevitable spread of analog components. Furthermore it is difficult to construct such analog delay units which can be easily controlled. To avoid these problems, the delay unit according to the above mentioned
  • KOKAI 64-19822 uses a FIFO memory ( First In First Out ) in which the digital symbols are written under control of a write control signal, and from which the digital symbols are read under control of a read control signal. To obtain a certain delay the read control signal is derived from the write control signal by inhibiting a number of pulses using a gate. The number of pulses inhibited is counted by a (presetable) counter, and if the number of pulses to be inhibited is reached, the write pulses are passed by the gate.
  • FIFO memory First In First Out
  • the read address differs from the write address by the number of pulses inhibited, causing that the digital symbols are retrieved said number of inhibited clock pulses later than they were written into the FIFO memory, leading to the desired delay.
  • a problem of the known delay unit is that it is only possible to obtain a delay that is equal to an integer number times the symbol period. The reason for this is that the number of pulses to be inhibited can only be integer valued.
  • the object of the present invention is to provide a delay element according to the preamble in which it is also possible to obtain delay values being not an integer number times the symbol period.
  • the delay unit is characterised in that the delay unit comprises phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal.
  • phase shift means for obtaining a phase shift between the write control signal and the read control signal, it is possible to obtain any delay value corresponding to the phase shift introduced between the write control signal and the read control signal.
  • a preferred embodiment of the invention is characterised in that the phas shift means comprise a phase detector for deriving a phase error signal being dependent on the value of the phase shift between the read control signal and the write control signal, a controlled oscillator for generating the read signal or the write signal in dependence on the phase error signal, and means for offsetting the phase error signal with an offset value.
  • phase locked loop comprising of phase detector and controlled oscillator tends to produce a phase error signal which cancels the offset value.
  • an additional phase shift dependent on the offset value is introduced between the input signal and the output signal of the phase locked loop.
  • Use of a phase locked loop is a very easy way to obtain a (variable) phase shift between the write control signal and the read control signal.
  • the use of the introduction of an offset in a phase locked loop for obtaining arbitrary phase shift values between input and output signal as such is disclosed in IBM technical disclosure bulletin, Vol. 19, No. 8, January 1977, pp 3131-3132.
  • phase shift means comprise a first frequency divider for deriving a first input signal for the phase comparator from the write control signal, and a second frequency divider for deriving a second input signal for the phase comparator from the read control signal.
  • the use of the first and second frequency dividers allows the range of the phase shift value to be larger than the range of the phase error that can be tolerated by the phase detector. If the division factor of the frequency dividers is equal to N, the range of th phase shift is increased with a factor N.
  • the delay unit according to the invention can be advantageously be used in a Transmission system comprising a plurality of secondary stations coupled to a primary station via a transmission channel being at least partial in common for several secondary stations, said secondary stations comprise a delay unit for delaying digital symbols to be transmitted from the secondary stations to the primary station over an adjustable amount of time for preventing collision of data symbols from different secondary stations, said delay unit comprising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal, and phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal.
  • Such transmission systems are used for the communication between several secondary stations to a primary station via a transmission channel being, at least partially, common to some of the secondary stations.
  • Such transmission channel can comprise an optical fibre, a coaxial cable, or a radio link.
  • Application of such transmission systems can be passive optical networks, local area networks, systems for satellite communication and mobile radio systems.
  • transmission systems utilising a common channel for some secondary stations it must be ensured that no interference is caused by secondary stations simulta ⁇ neously transmitting information to the primary station.
  • a possibility to prevent such interference is to allot a predetermined time slot from a number of distinct time slots to each of the secondary stations. Because these time slots are non-overlapping, the primary station can distinguish the signals from different secondary stations.
  • said secondary stations have different distances from the primary station. In mobile radio systems these distances are even variable. Due to these different distances the propagation delay between these secondary stations and the primary stations may be different. This results in that signals which are transmitted in non overlapping time slots can collide at arrival at the primary station.
  • the delay value of the delay element is set to such a value that the sum of said delay value and the transmission delay value is equal for all secondary stations.
  • the duration of a time slot is only one or a few symbol periods. Having such narrow time slots, only a small overlap between such time slots can be tolerated, because otherwise the data in the time slot will be completely or partly lost.
  • guard spaces between the time slots the allowable tolerances of the total transmission delay could be relaxed, but this would lead to a less efficient use of the transmission capacity available.
  • the delay unit can be adjusted with a resolution being a fraction of the symbol period.
  • the delay unit according to the invention fulfils all requirements, and is very simple to construct.
  • Fig. l a block diagram of the delay unit according to the invention
  • Fig. 2 an embodiment of the phase shift means 8 to be used in the delay unit according to fig. 1 ;
  • Fig. 3 a first embodiment of the FIFO memory 4 in Fig. 1;
  • Fig. 4 a second embodiment of the FIFO memory 4 and the phase shift means 8 in Fig. 1;
  • Fig. 5 a timing diagram of some signals in the delay unit according to Fig. 4.
  • Fig. 6 a transmission network in which the delay unit according to the invention can be used
  • Fig. 7 a secondary station for use in the transmission system according to Fig. 6.
  • phase shifting means 8 In the delay unit 2 according to Fig. 1 digital symbols to be delayed are applied in serial form to an input of a FIFO memory 4.
  • An output of a clock generator 6 carrying as ou ⁇ ut signal the write control signal is connected to a write control input of the FIFO memory 4 and to an input of the phase shifting means 8.
  • the output of the delay unit 2 is constituted by an output of the FIFO memory 4.
  • the ou ⁇ ut of the phase shift means 8 carrying the read control signal is connected to a read control input of the FIFO memory 4.
  • the phase shifting means 8 has a further input to receive a control signal specifying the value of the phase shift.
  • the FIFO memory 4 is arranged to receive the data symbols to be delayed at the input. This data is stored in the FIFO memory 4 during a clock pulse generated by the clock generator 6. The frequency of the clock signal generated by the clock generator 6 is equal to the symbol frequency. At the ou ⁇ ut of the FIFO memory the stored symbols are retrieved in response to the read control signal at the ou ⁇ ut of the phase shifting means 8. The stored symbols are retrieved in the same order as they were written in the FIFO memory 4.
  • the input signal is applied to an input of a first frequency divider 10.
  • the ou ⁇ ut of the frequency divider 10 is connected to a first input of a phase comparator 12.
  • An ou ⁇ ut of the phase comparator 12 is connected to a first input of an adder 16.
  • An offset signal is applied to a second input of the adder 16.
  • An ou ⁇ ut of the adder 16 is connected to an input of a low pass filter 18.
  • An ou ⁇ ut of the low pass filter 18 is connected to a control input of a controllable oscillator 20.
  • An ou ⁇ ut of the controllable oscillator, carrying the read control signal, is connected to an input of a second frequency divider 14.
  • the ou ⁇ ut of the second frequency divider 14 is connected to a second input of the phase comparator 12.
  • the phase locked loop constituted by the first and second frequency dividers 10 and 14, the phase comparator 12 the adder 16 the low pass filter 18 and the controllable oscillator 20 will cause the input signal of the low pass filter to be equal to zero. If no offset signal is applied at the second input of the adder 16, the average value of the ou ⁇ ut signal of the phase comparator is also equal to zero. This is in general the case at a phase shift of 90 ° between the write control signal and the read control signal. If an offset value is applied at the second input of the adder 16 the phase locked loop will keep the average value of the ou ⁇ ut signal of the adder 16 equal to zero. This is only possible if the average value of the ou ⁇ ut signal of the phase detector 12 differs from zero.
  • phase shift can only be caused by an additional phase shift between write control signal and read control signal, said phase shift being dependent on the offset value.
  • the possible value of the additional phase shift is determined by the range of the phase comparator 12.
  • the first and second frequency dividers are introduced. The introduction of the frequency dividers 10 and 14 results in an N fold increase of the range of the additional phase shift.
  • the signal to be delayed is applied to a data input of a dual port RAM 22.
  • a number of ou ⁇ uts of a programmable counter 24 is coupled to corresponding address inputs of the dual port RAM 22.
  • the write control signal is applied to a clock input of the programmable counter 24.
  • the counters 24 and 26 comprise parallel inputs for enabling the transfer of a preset value into said counter 24 or 26 under control of a parallel load signal.
  • the ou ⁇ ut of the FIFO memory 4 comprises a data ou ⁇ ut of the dual port RAM 22.
  • a number of ou ⁇ uts of a programmable counter 26 is coupled to corresponding address inputs of the dual port RAM 22.
  • the read control signal is applied to a clock input of the programmable counter 26.
  • the counter 26 comprises parallel inputs for enabling the transfer of a preset value into said counter 24 under control of a parallel load signal.
  • a number is loaded into counter 24 and 26 under control of the corresponding parallel load input.
  • the delay value is determined by the difference between the numbers loaded in the counters 24 and 26 respectively.
  • an input symbol is written into the dual port RAM 22 at the address indicated by the counter 24 at every pulse of the write control signal.
  • the count of the counter 24 is increased.
  • An ou ⁇ ut symbol is read from the dual port RAM 22 at the address indicated by the counter 26 at every pulse of the read control signal.
  • the count of the counter 26 is also increased.
  • the difference D between the contents of the counters 24 and 26 determines a coarse delay value expressed in a number of symbol periods.
  • the delay of the delay unit according to Fig. 3 shows an ambiguity of the delay value of one symbol period. This ambiguity is caused by the unknown phase relationship between the read control signal and the write control signal during loading the counters 24 and 26. Such ambiguity can be avoided by setting the phase difference between the read control signal and the write control signal to a predetermined value during loading the counters 24 and 26. By introducing an arbitrary phase shift between the read control signal and the write control signal the delay value has not to be equal to an integer number of symbol periods. In the delay unit according to Fig.
  • the signal to be delayed is applied to an input of the FIFO memory 4, which input is constituted by an input of a series to parallel converter 30.
  • N parallel ou ⁇ uts of the series to parallel converter 30 are coupled to N parallel inputs of a latch 31.
  • N parallel ou ⁇ uts of the latch 31 are connected to N parallel inputs of a parallel to series converter 32.
  • An ou ⁇ ut of the parallel to series converter 32 constitutes the ou ⁇ ut of the FIFO memory 4 and of the delay unit 2.
  • a clock signal CLK is applied to an input of the phase shifting means 8, which input is constituted by a clock input of a frequency divider 34 and to a clock input of the series to parallel converter 30.
  • a first ou ⁇ ut of the frequency divider 34, carrying ou ⁇ ut signal CLK8, is coupled to a reference input of a phase locked loop.
  • a second ou ⁇ ut of the frequency divider 34, carrying an ou ⁇ ut signal BYTE, is connected to a clock input of the latch 31.
  • An ou ⁇ ut of the phase locked loop 38, carrying an ou ⁇ ut signal PCLK, is connected to a clock input of a frequency divider 36 and to a clock input of the parallel to series convener 32.
  • a first ou ⁇ ut of the frequency divider 36, carrying an ou ⁇ ut signal PCLK8, is coupled to a second input of the phase locked loop 38.
  • a second ou ⁇ ut of the frequency divider 36, carrying an ou ⁇ ut signal PLOAD, is connected to an parallel load input of the parallel to series converter 32.
  • the phase locked loop 38 has further a control input to receive a signal ⁇ representing the desired phase shift.
  • the frequency of the clock signal CLK applied to the delay unit 2 is equal to the symbol period.
  • This clock signal is displayed in Fig. 5a.
  • the symbols applied at the input of the series to parallel converter are clocked into said series to parallel converter in response to the clock signal CLK and are available in parallel format at the ou ⁇ uts of the series to parallel converter 30.
  • the parallel data remains available at the ou ⁇ uts of the latch 31 during 8 subsequent symbol periods.
  • a signal CLK8 ( Fig. 5d ) having a duty cycle of 50 % is applied to the phase locked loop 38.
  • the phase locked loop 38 generates an ou ⁇ ut clock signal PCLK having a frequency equal to the frequency of the clock signal CLK, but being phase shifted.
  • the ou ⁇ ut signal PCLK8 is phase shifted with respect to the clock signal CLK8 by the phase locked loop 38, due to the presence the signal ⁇ .
  • N 8 symbol periods
  • the delay value D of the delay element 2 is determined by the relative position of the falling edge of the signal PLOAD and the falling edge of the signal BYTE. By changing the position of the signal PLOAD by the introduction of the signal ⁇ into the phase locked loop 38 it is possible to obtain a variable delay value D. Said value delay is not restricted to inter symbol periods, because the phase shift between the signals CLK8, and PCLK8 can have any value between 0 and 8 symbol periods.
  • a primary station 40 is coupled via a channel 54 to a number of secondary stations 42 • • • 52. Parts of the transmission channel 54 are in common for some of the substations.
  • the transmission channel can be a passive optical network for a local loop transmission system, a cable for a local area network or the free space for a mobile radio system. If the so-called Time Division Multiple Access method is used, some or all of the active stations have to transmit its data on a corresponding time slot in a predetermined frame. Due to the difference in propagation delay between the several secondary stations and the primary stations, it may occur that signals which are transmitted at the correct time by said secondary stations collide on their arrival at the primary station.
  • the secondary stations are provided with delay means to delay their transmitted signals by such an amount that no collision occurs at arrival of said signals from several secondary stations at the primary station. If the size of the time slots is only one or a few symbol periods to limit the signal delay in the transmission system, it is required to be able to delay a signal over a non integer number of symbol periods if a guard space is not used due to efficiency reasons. To that end the delay unit according to the invention provides a simple and effective solution.
  • the transmission channel can be coupled to an input/ou ⁇ ut of a duplexer 60.
  • the ou ⁇ ut of the duplexer 60 is coupled to an input of a receiver 62.
  • An ou ⁇ ut of the receiver is coupled to an input of a decoder 64.
  • the ou ⁇ ut of the decoder 64 is coupled to a n input of a frame disassembler 66.
  • a signal representing the useful data is available.
  • the data to be transmitted is applied to an input of a delay element 2.
  • a second ou ⁇ ut signal of the disassembler 66, carrying a signal representing the desired delay value is coupled with a second input of the delay element 2.
  • an ou ⁇ ut of the delay element is coupled to an input of a coder 70.
  • An ou ⁇ ut of the coder 70 is coupled to an input of a transmitter 72.
  • An ou ⁇ ut of the transmitter 72 is coupled to an input of the duplexes 60.
  • a signal from the transmission channel is applied to the receiver 62 by the duplexes 62.
  • the receiver 62 processes the received signals and presents a base band signal representing the ou ⁇ ut symbols at its ou ⁇ ut.
  • the operations of the receiver 62 can comprise demodulation, equalisation, timing recovery and detection.
  • the ou ⁇ ut symbols of the receiver 62 are decoded by the decoder 64.
  • the received signal may be encoded for error protection or for secrecy reasons.
  • the frame comprising the symbols is separated into useful data and control data.
  • the useful data is made available at the ou ⁇ ut of the secondary station. A part of the control signals that determines the desired delay of the data transmitted in the time slot corresponding to said secondary signal.
  • a signal to be transmitted by the secondary station is delayed with the desired value and applied to the coder 70 for encoding.
  • the encoded signal is transformed into a signal that is suitable for transmission via the transmission channel by the transmitter 72. This transformation may include modulation and amplification to a desired signal level.
  • the duplexes 60 applies the ou ⁇ ut signal of the transmitter 72 to the transmission channel and prevents cross talk of the signal to be transmitted to the input of the receiver 62.
  • the delay value applied to the control input of the delay element 2 can comprise an integer part representing the integer number of symbol periods of the delay value and a fractional part representing the fraction of the symbol period of the delay value.
  • the delay element according to Fig. 3 is suitable for application with such control signals.
  • the integer part determines the difference between the numbers with which the counters are loaded at initialisation, and the fraction part determines the value of the phase shift.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Conformément à l'état antérieur de la technique, dans un circuit de temporisation (2) qui comprend une mémoire fonctionnant suivant la méthode du premier entré, premier sorti (FIFO) (2), la valeur du retard qu'il est possible d'obtenir ne peut être égale qu'à un nombre entier de fois la période élémentaire des symboles binaires. L'utilisation d'un déphaseur (8) pour introduire un déphasage arbitraire entre un signal de commande d'écriture dans la mémoire FIFO (2) et un signal de commande de lecture depuis cette même mémoire FIFO permet d'obtenir un retard dont la durée ne correspond pas à un nombre entier de fois la période élémentaire des symboles binaires.
EP95929185A 1994-09-15 1995-09-06 Circuit de temporisation et systeme de transmission utilisant un tel circuit Withdrawn EP0729671A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP95929185A EP0729671A1 (fr) 1994-09-15 1995-09-06 Circuit de temporisation et systeme de transmission utilisant un tel circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP94202662 1994-09-15
EP94202662 1994-09-15
EP95929185A EP0729671A1 (fr) 1994-09-15 1995-09-06 Circuit de temporisation et systeme de transmission utilisant un tel circuit
PCT/IB1995/000739 WO1996008868A2 (fr) 1994-09-15 1995-09-06 Circuit de temporisation et systeme de transmission utilisant un tel circuit

Publications (1)

Publication Number Publication Date
EP0729671A1 true EP0729671A1 (fr) 1996-09-04

Family

ID=8217197

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95929185A Withdrawn EP0729671A1 (fr) 1994-09-15 1995-09-06 Circuit de temporisation et systeme de transmission utilisant un tel circuit

Country Status (3)

Country Link
EP (1) EP0729671A1 (fr)
CN (1) CN1137845A (fr)
WO (1) WO1996008868A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974103A (en) * 1996-07-01 1999-10-26 Sun Microsystems, Inc. Deterministic exchange of data between synchronised systems separated by a distance
DE19908929A1 (de) * 1999-03-02 2000-09-21 Headroom Videotechnik Gmbh Verfahren zur Synchronisation eines Übertragungsgerätes der Telekommunikationstechnik
KR100624296B1 (ko) * 2004-11-08 2006-09-19 주식회사 하이닉스반도체 반도체 메모리 소자
DE102012211178B4 (de) 2011-06-29 2022-06-30 Skyworks Solutions, Inc. Dynamische Zeitangleichung von Tonsignalen in Simultanausstrahlungsradioempfängern
CN105262462B (zh) * 2015-10-21 2018-03-20 圣邦微电子（北京）股份有限公司 一种用于集成电路的数字延时实现方法及电路
CN109900971B (zh) * 2017-12-11 2023-01-24 长鑫存储技术有限公司 脉冲信号的处理方法、装置以及半导体存储器

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
EP0349715B1 (fr) * 1988-07-06 1994-01-05 ANT Nachrichtentechnik GmbH Procédé et circuit pour produire un signal d'horloge décalé en phase
FR2674393A1 (fr) * 1991-03-21 1992-09-25 Bourgart Fabrice Synchronisation de stations terminales dans un reseau a l'alternat et multidebit.

Non-Patent Citations (1)

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Title
See references of WO9608868A3 *

Also Published As

Publication number Publication date
CN1137845A (zh) 1996-12-11
WO1996008868A2 (fr) 1996-03-21
WO1996008868A3 (fr) 1996-05-30

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