Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes
  • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/33—Synchronisation based on error coding or decoding
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
  • H04Q11/0478—Provisions for broadband connections
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5672—Multiplexing, e.g. coding, scrambling
  • H04L2012/5673—Coding or scrambling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5672—Multiplexing, e.g. coding, scrambling
  • H04L2012/5674—Synchronisation, timing recovery or alignment

Definitions

• the present invention relates to a method and an apparatus for detecting a cyclic code, and further relates to a synchronization means convenient for cell synchronization in an ATM communication system encoded by a predetermined cyclic code.
• ATM A synchronous Tran sfer Mode; non-
• ISDN broadband Integrated Services Digital Network
• C is a method in which data containing voice and image information is divided into fixed-length blocks called cells, and the data is transferred at high speed with a header indicating the destination.
• cells used for data transfer include a header of 5 bytes and an information field of 48 bytes, for a total of 53 bytes. Furthermore, in this example, 5 bytes of the cell header, that is, 32 bits out of 40 bits are information points, and 8 bits are check points called HEC (Header Error Control).
• HEC Header Error Control
• cell synchronization it is necessary for the receiving side to correctly detect cells that are continuously transferred on the transmission path, and to find the cell delimiter. This process is called cell synchronization, and the beginning of the cell is called cell synchronization. In general, this is performed using a header added to. Specifically, since the shortened cyclic code that can be divisible by the generator polynomial, if the division by the generator polynomial a 4 ⁇ bit header at the receiving side as described above, X 6 obtained by adding a header on the transmission side + X 4 + X 2 + 1 is a remainder, so this property is used.
• this check is performed sequentially until the pre-synchronization state is reached, as in the case of performing the same check on the 40 bits shifted to the next bit by 1 bit. Furthermore, in the pre-synchronization state, the HEC at the position considered to be the header of the next cell is checked a specified number of times, and if it is correct, a complete synchronization state is established.
• the 8-bit feedback shift register shown in FIG. 2 used as the divider 1 will be described.
• the output of each shift register 3 at the time when 40 bits of the data received by the divider 1 composed of the 8-bit feedback shift register is just input becomes a remainder.
• the calculations performed here are all binary code calculations. Therefore, the adder 5 means an exclusive OR circuit, and the addition and the subtraction are the same exclusive OR.
• the first 40 bits received are input to the divider, and the remainder for 40 bits is obtained.
• the remainder will be 41 bits, which is not the remainder of the next 40 bits desired. In other words, in order to always find the latest remainder, it must be a method that is not affected by preceding bits.
• a 40-bit shift register consisting of a 32-bit shift register and a divider connected in series is constructed, and in this 40-bit shift register, one bit of data is stored. It is conceivable to take in 40-bit data in parallel each time the data is input, perform division processing in it, and check the output.
• the present invention has been made to solve the above-described problem of the conventional cyclic code detection or the ATM cell synchronization system using the same, and is simple and does not require a high-speed circuit. To provide a method and apparatus capable of finding the position of the n-bit cyclic code or the shortening of the cyclic code from a continuous bit sequence, and to provide an ATM cell synchronization system using the cyclic code. And
• a successively input bit sequence is divided by a generator polynomial, and n bits included in the bit sequence are divided based on the result.
• a residue of the generator polynomial is subtracted before performing the division.
• the second invention of the present application in a method for detecting an n-bit cyclic code or a shortened cyclic code based on a predetermined m-th order generator polynomial G (X) from a bit string inputted one bit at a time, Each time 1 bit is input, when the coefficient of the (n + 1) th bit Xn is not zero, the remainder ( Xn / G (X) of Xn / G (X)) obtained by dividing Xn by the predetermined generator polynomial G (X) ) Is subtracted from the latest ⁇ bit, that is, the remainder obtained by dividing the candidate ⁇ bit of the cyclic code bit string by G (X), and the result is zero or a specific bit code added to the cyclic code.
• the candidate ⁇ bit of the cyclic code bit sequence at that time is a cyclic code or a shortened cyclic code sequence by being a turn.
• An apparatus for detecting a delimiter comprising: a shift register having n or more stages for inputting bit data to be input; and an m-bit divider corresponding to the m-th order polynomial G (X).
• the output of the n-th bit stage is input to an exclusive-OR circuit arranged between the required stages of the divider, and each time one bit of data is input, the contents of each cell of the divider become zero or a specific value. It is characterized by comprising means for determining that the pattern is a bit pattern.
• FIG. 1 is a block diagram showing an embodiment for realizing the ATM cell synchronization system of the present invention
• FIG. 2 is a block diagram showing a configuration of an 8-bit feedback shift register forming a divider
• FIG. Configuration diagram for explaining the problem Fig. 4 solves the problem shown in Fig. 3, Configuration diagram for explaining the first method
• Fig. 5 solves the problem shown in Fig. 3
• FIG. 3 is a configuration diagram for explaining a second method.
• a generating polynomial G (X) is 8 bit (X 8 + X 2 + X + 1)
• the cell is a total of 53-by-Bok header 5 bytes information field 48 by Bok, further to The data is assumed to consist of a 32-bit information point and an 8-bit HEC.
• FIG. 1 is a configuration diagram showing a main part of an embodiment of a cyclic code detection device for implementing the ATM cell synchronization system of the present invention.
• This device performs an exclusive OR operation between the first and second stages, between the fifth and sixth stages, and between the sixth and seventh stages of the divider 1. While inserting circuits 12, 12 and 12, the output of the last stage of the 4-bit shift register 10 is input to the newly added exclusive OR circuits 12, 12 and 12.
• the decoder (DEC) 11 is configured to detect that the bit values in each register of the divider 1 are all zero or a specific pattern.
• the divider 1 by 40-bit data sequence generator polynomial G (X) (X 8 + X 2 + X + 1) is divided by further x 4 ° / G From the results The remainder of (X) (X 6 + X 5 + X) will be subtracted.
• each cell of the divider 1 is monitored by the decoder DEC 11 and if it is detected that the contents are all zero, the bit string at that time is searched for the cell to be obtained. It is da.
• the ATM cell synchronization method of the present embodiment is not limited to the ATM, and uses a cyclic code or a shortened cyclic code of a specific length from a continuous bit string, or a symbol obtained by adding a specific pattern to them. As a way to find out Widely available.
• the present embodiment employs a method of finding the position of the break of an n-bit cyclic code or a shortened cyclic code from a continuous bit sequence, by calculating the remainder when X n is divided by a generator polynomial. By subtracting from the divider, a high-speed circuit is not required, and a simple circuit can be realized.
• the present invention Since the present invention is configured and operates as described above, it has a remarkable effect in searching for the position of the delimiter of the n-bit cyclic code or the shortened cyclic code from the continuous bit sequence with a simple circuit. .

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Probability & Statistics with Applications (AREA)
• Theoretical Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Algebra (AREA)
• Pure & Applied Mathematics (AREA)
• Mathematical Physics (AREA)
• General Physics & Mathematics (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Error Detection And Correction (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

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Publications (1)

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• 1993
  • 1993-06-30 JP JP5186622A patent/JPH0787090A/ja active Pending
• 1994
  • 1994-06-22 WO PCT/JP1994/000998 patent/WO1995001683A1/ja not_active Application Discontinuation
  • 1994-06-22 KR KR1019950703747A patent/KR960701537A/ko not_active Withdrawn
  • 1994-06-22 EP EP94918549A patent/EP0740438A4/en not_active Withdrawn
  • 1994-06-22 SG SG9609232A patent/SG82556A1/en unknown
  • 1994-06-22 US US08/513,905 patent/US5764876A/en not_active Expired - Fee Related
  • 1994-06-22 TW TW083105674A patent/TW257908B/zh active

Patent Citations (1)

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