WO1994011936A1 - Agencement de commutation - Google Patents

Agencement de commutation Download PDF

Info

Publication number
WO1994011936A1
WO1994011936A1 PCT/GB1993/002249 GB9302249W WO9411936A1 WO 1994011936 A1 WO1994011936 A1 WO 1994011936A1 GB 9302249 W GB9302249 W GB 9302249W WO 9411936 A1 WO9411936 A1 WO 9411936A1
Authority
WO
WIPO (PCT)
Prior art keywords
fets
control
voltage
fet
arrangement according
Prior art date
Application number
PCT/GB1993/002249
Other languages
English (en)
Inventor
Dennis Malcolm Pryor
Michael Challis
Original Assignee
Raychem Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raychem Limited filed Critical Raychem Limited
Priority to BR9307421-2A priority Critical patent/BR9307421A/pt
Priority to AU53750/94A priority patent/AU5375094A/en
Priority to PL93308764A priority patent/PL308764A1/xx
Priority to EP93924148A priority patent/EP0669049A1/fr
Priority to JP6511821A priority patent/JPH08503357A/ja
Priority to SK626-95A priority patent/SK62695A3/sk
Priority to KR1019950701872A priority patent/KR950704844A/ko
Publication of WO1994011936A1 publication Critical patent/WO1994011936A1/fr
Priority to BG99627A priority patent/BG99627A/xx
Priority to NO951862A priority patent/NO951862L/no
Priority to FI952317A priority patent/FI952317A/fi

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems

Definitions

  • This arrangement relates to protection of electrical circuits from overcurrents, for example from overcurrents caused by equipment faults, electrostatic discharge or other threats.
  • the arrangement is preferably bidirectional, ie can deal with currents flowing in either direction through it, and can preferably deal with alternating currents.
  • the arrangement can act as a switch that is closed under normal operating conditions and that opens in response to an overcurrent fault.
  • the arrangement is particularly useful in communication lines that have a DC bias from which a voltage may be generated.
  • SUBSTITUTE SHEET protection switch employing a pair of field-effect transistors (FETs), preferably arranged so that for any voltage across the arrangement one is forward biased and one is reverse biased.
  • FETs field-effect transistors
  • the present invention provides an arrangement for connection in an electrical circuit, which comprises:
  • ( 1 ) a pair of FETs that are series connected in a line of the circuit with their sources connected together or with their drains connected together and whose states can be altered by means of a voltage (generally by means of a replacement of one voltage by another) acting on their gates;
  • control being responsive to an overcurrent on the line thereby altering the states of the FETs.
  • the arrangement is preferably not merely current-limiting (ie allowing increased current with increased voltage drop across the arrangement up to a certain voltage drop beyond which the current remains constant), but rather causes a reduction in current once some threshold voltage across it has been reached. That voltage drop will in general result from a current flowing through the resistance of the arrangement, and then an overcurrent will produce a significant reduction in subsequent current flow. This behaviour may be regarded as "foldback", although the degree of foldback may be less than 100%.
  • VQS gate-source voltage
  • the function of the control is preferably to make VQS more negative (in the case of an n-channel FET) as V ⁇ s increases (and therefore as current flowing through the arrangement increases) thus shifting the operating point from one Ip - Nos curve to another as the current increases.
  • the result is to cause foldback behaviour.
  • enhancement-mode and depletion mode n-channel FETs require a bias for normal conduction, and hence the function of the control will be to remove this bias, for example reducing N ⁇ s from, say, 5 volts to zero volts.
  • the control may comprise a switch that applies a negative voltage (in the case of n-channel depletion mode FETs) or that shorts or otherwise removes a positive voltage (in the case of n-channel enhancement mode FETs), and it may do this substantially instantaneously gradually depending on the speed of foldback required.
  • the control may comprise a transistor whose resistance comprises the switch.
  • the gate or base voltage of the transistor the value of which determines that resistance, can be made automatically dependent on
  • the foldback process may involve positive feedback and therefore be very rapid.
  • the channel resistance of a FET increases as the gate voltage is made more negative, in the case of an n-channel FET, or more positive in the case of a p-channel FET.
  • the voltage drop across the FETs which is itself a function of channel resistance, which forms the input into the control, the output of which is the value of VQS -
  • an overcurrent is registered by the control as a voltage drop across the FETs and this causes VQS to be altered.
  • An alteration in VQS results in a greater channel resistance, which increases the voltage drop across the FETs, which in turn further alters VQ - and so on.
  • any such resistor preferably has a resistance of less than 100 KO and more preferably is substantially 0 ⁇ .
  • the FETs be arranged with their sources, rather than drains, connected together since that allows their gates to be connected together for control by a single voltage signal. This is because it is the gate-source (rather than gate-drain) voltage that controls the source-drain resistance and hence the resistance of the arrangement. If the drains are connected together, the sources will be at mutually different voltages, and if each gate-source voltage is to be correct then the two gate voltages will, in general, be different.
  • the arrangement is preferably used for overcurrent protection and/or remote switching in a telecommunications line, such as a telephone line, or other communications line.
  • a telecommunications line such as a telephone line, or other communications line.
  • the arrangement may
  • SUBSTITUTE SHEET comprise a first pair of FETs ( 1) and control (2) connected in one conductor of the line, and a second pair of FETs ( 1) and control (2) connected in a second conductor of the line.
  • a shunt switch may be provided that will interconnect conductors of the line, thereby for example shunting an overvoltage across a telephone or other load in the circuit, or that will connect either conductor to an earth. Such a shunt switch may be activated by the or another control.
  • the invention also provides a telecommunications system or other system comprising a communications line and an arrangement of the invention in which the voltage is generated from a DC bias on the line.
  • the invention further provided terminal equipment, for example a telephone, computer, network interface device or exchange switch, incorporating an arrangement of the invention.
  • each FET of the pair may comprise an enhancement mode FET or each may comprise a depletion mode FET, either of which may be an n-channel or p-channel FET.
  • An enhancement mode FET will be normally switched off, and a voltage will normally be needed to bias it into conduction.
  • the control may then serve to remove that bias voltage in response to an overcurrent and optionally also in response to a separate gating signal. This may be done by opening a switch that connects the bias voltage to the FETs or by shorting the gates and sources of the FETs.
  • Depletion mode FETs are normally switched on and in this case the control may serve to connect a bias voltage to the FETs in response to an overcurrent and optionally also in response to a separate gating signal.
  • a mixture of one enhancement mode and one depletion mode FET is not at present preferred since the control required will have to
  • SUBSTITUTE SHEET act in opposite sense for each FET and will therefore be more complex.
  • an arrangement that can be series connected in a line of an electrical circuit for protecting the circuit from an overcurrent which comprises:
  • control transistors being biased into conduction when the arrangement experiences an overcurrent so that the FETs are switched off.
  • the invention has the advantage that the voltage drop appearing across the arrangement can be low, that the arrangement can deal with current in either direction and in preferred embodiments that the switch can be actuated remotely by altering the output of the voltage source.
  • SUBSTITUTE SHEET drop across the parasitic diode is only about 0.1N.
  • the parasitic diodes exhibit substantially linear characteristics rather than a typical non-linear diode characteristic.
  • the arrangement can be employed directly in a.c. circuits, thereby obviating the need for a rectifying bridge (which would increase the voltage drop by a further 1.3V).
  • the arrangement preferably exhibits a "foldback" characteristic, that is to say, one in which the current that passes through the arrangement increases with increasing voltage difference across it until a certain voltage, referred to as the threshold voltage, is reached whereupon the current through the device decreases to a lower value.
  • the threshold voltage a certain voltage
  • the ratio of the maximum leakage current of the device in its off state to the maximum current of the device in its on state (trip current) is not more than 0.5, more preferably not more than 0.1 and especially not more than 0.01. In may cases the ratio can be lower than 10 -4 . It is possible, depending on the mechanism of operation of the device that biases the FET, for the arrangement to have a "slow” or a "fast” foldback characteristic.
  • the arrangement switches quickly from its on state to its off state, for example in less than 100 microseconds, then it can be said to exhibit a fast foldback characteristic, whereas if the transition between the on state and the off state takes longer it can be said to exhibit a slow foldback characteristic.
  • Which characteristic is preferred will depend on the application of the circuit. For example an arrangement that exhibits a fast foldback characteristic will generally let through less energy to the load when subjected to a current transient, whereas arrangements exhibiting slower foldback characteristics may be preferred if the circuit has a load having a significant inductance or if the arrangement needs to be insensitive to short current transients due, for example to equipment being switched on.
  • control transistors may be either bipolar transistors or FETs.
  • the base or gate of each control transistor is normally held in a voltage divider that spans the arrangement. In this way, the voltage appearing across the arrangement due to the channel resistance etc. of the switching FETs will be passed to the base or gate of each control transistor.
  • the arrangement may be controlled remotely if desired, or it is possible for it to be connected to a fixed voltage source, in which case the arrangement will act merely as an overcurrent protection switch.
  • the voltage source may, for example, be fixed by tying it to the line voltage (or a fraction of the line voltage) and optionally inverting it by means of a voltage doubling circuit or the like.
  • the arrangement defined above need only be a two terminal arrangement, it is possible also to form three terminal arrangements according to the invention where the third terminal switches on when an overcurrent is experienced in order to shunt the current across the load or to an earth terminal.
  • Five terminal protection arrangements for protecting a pair of lines may be formed employing a pair of overcurrent protection devices as described above which can employ either two devices for shunting the overcurrent to an earth terminal, and/or a single shunting device across the lines.
  • MTU maintenance termination unit
  • That application claims a switching arrangement that can be connected in a communications channel that comprises a pair of lines between sets of terminal equipment, which comprises:
  • ( 1 ) a series switch for connection in each of the lines, and preferably controlled by a voltage generator that takes its power from voltage appearing between the lines, the voltage generator preferably being controlled by a control circuit;
  • control circuit (3 ) the control circuit, the control circuit being able to actuate the series switches and the shunt switch on receipt of a signal sent along the channel;
  • control circuit can actuate both the shunt switch and the series switches on receipt of a single signal, but the shunt switch will remain closed over a different time period than that during which the series switches remain open, in order to allow different tests to be performed on the channel;
  • the series switches will preferably close before the shunt switch opens.
  • Figure 1 is a circuit diagram of an arrangement employing two enhancement mode FETs
  • FIG. 2 is a circuit diagram of an arrangement employing two depletion mode FETs
  • Figure 3 is a circuit diagram of an arrangement employing two pairs of FETs and two controls.
  • Figure 4 is a circuit diagram showing the use of charge pumps.
  • a switching arrangement for a circuit line 1 comprises a pair of n-channel enhancement-mode field effect transistors Ql and Q2 arranged with their sources connected together so that one of these transistors is always forward biased and the other is always reverse biased (but which is forward and which is reversed biased will depend on the polarity of the voltage on the line).
  • Ql and Q2 n-channel enhancement-mode field effect transistors
  • Ql and Q2 n-channel enhancement-mode field effect transistors
  • the gates of the two FETs Ql and Q2 are connected together and this node is connected to a positive voltage source 2.
  • the node is also connected to the sources of the two FETs Ql and Q2 via a 10MO resistor Rl in order to prevent the gate terminals floating.
  • the bases of the bipolar transistors are held in a pair of voltage dividers formed from resistors R2, R3, R4 and R5, each voltage divider spanning one of the FETs Ql and Q2.
  • the FETs Ql and Q2 are biased into conduction so that current can flow in the line, current flowing through the parasitic diode of the reverse biased FET. If an overcurrent is experienced, the base-emitter voltages of the control transistors Q3 and Q4 will rise to about 0.7V and these transistors will be switched on, thereby shorting the gates and sources of FETs Ql and Q2 and switching them off, thus breaking the line and protecting any equipment connected to it.
  • the current flow may also, if desired, be controlled by altering the voltage of the voltage source 2.
  • the arrangement will remain in the off state even when the overcurrent has passed because the whole system voltage will then be dropped across the arrangement, thereby ensuring that the control transistors remain on.
  • the only leakage current is that due to the four series connected resistors R2 to R5. This leakage current may be reduced to a satisfactorily small value by
  • SUBSTITUTE SHEET chosing high resistances such as 1 M ⁇ for each of resistors R2 to R5.
  • the arrangement may be reset simply by removing the line voltage, which will cause the control transistors Q3 and Q4 to turn off.
  • Capacitors may be connected in parallel with resistors R2 and R4 in order to prevent the arrangement switching off when power is initially applied to the line and to prevent spurious current spikes that normally appear on the line from activating the overcurrent control transistors Q3 and Q4.
  • Figure 2 shows an arrangement comprising two depletion mode FETs Q2 and Q3, and a control.
  • the arrangement is inserted in a line 1.
  • the control 3 comprises a rectifier Dl, D2, D3, D4, a regulator 4 and a negative voltage generator 5.
  • the regulator 4 is made up of a FET Q l and a resistor Rl, and the negative voltage generator is based on a 7660 integrated circuit plus capacitors Cl and C2.
  • a variable resistor RV1 is included so that the degree of foldback can be chosen by regulating the negative voltage applied to the gates of the FETs Q2 and Q3.
  • SUBSTITUTE SHEET A fault that results in an overcurrent causes a greater voltage to be developed across the FETs Q2 and Q3, and this is supplied to the negative voltage generator 5 of the control 3. Due to the rectifier Dl, D2, D3, D4 the negative voltage generator operates whichever direction of current flow occurs in the line 1 , and the arrangement will operate on AC lines.
  • the negative voltage generator 5 supplies the required negative bias to the gates of the FETs Q2 and Q3, turning them off. Thus, the line 1 is broken, protecting equipment connected to it.
  • Figure 3 shows a circuit comprising two arrangements substantially as shown in figure 1 , one in each of two lines, for example the tip and ring lines of a telecommunications system.
  • the bias voltages for the FETs are generated by opto ⁇ electronic devices 6.
  • the bias voltages are provided by the use of voltage doublers or charge pumps, if necessary in conjunction with a voltage divider etc.
  • a suitable circuit which fulfils our present preference for low current consumption is shown in figure 4, where the charge pump is shown as 7.
  • the FETs preferably have a current rating of greater than 1 mA, more preferably greater than 10 mA, especially greater than 100 mA, and preferably less than 500A, usually less than 10A, and often less than 1A.
  • Various types of FETs including MOSFETs and JFETs and n-channel and p-channel types, including mixtures of these, can be used.
  • Preferred voltage ratings are 1500V to 20V, especially 400V-20V, and preferred power dissipation in between 1 KW and 200 mW, more usually from 1W to 100 mW.
  • a preferred gate threshold is between 10V and 0.8V, especially from 1 -4 V.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Protection Of Static Devices (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Networks Using Active Elements (AREA)

Abstract

Agencement de connexion dans un circuit électrique, comprenant: (1) une paire de transistors à effet de champ connectés en série dans une ligne du circuit, leurs sources ou leurs drains étant connectés ensemble, et leurs états pouvant être modifiés par l'intermédiaire d'une tension agissant sur leurs grilles; et (2) un dispositif de commande connecté à la grille d'au moins l'un des transistors; ce dispositif de commande étant sensible à un courant de surcharge sur la ligne, modifiant les états d'au moins l'un des transistors à effet de champ.
PCT/GB1993/002249 1992-11-12 1993-11-02 Agencement de commutation WO1994011936A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
BR9307421-2A BR9307421A (pt) 1992-11-12 1993-11-02 Arranjo de comutação
AU53750/94A AU5375094A (en) 1992-11-12 1993-11-02 Switching arrangement
PL93308764A PL308764A1 (en) 1992-11-12 1993-11-02 Switching equipment and communication system, especially a termal provided with such equipment
EP93924148A EP0669049A1 (fr) 1992-11-12 1993-11-02 Agencement de commutation
JP6511821A JPH08503357A (ja) 1992-11-12 1993-11-02 スイッチング装置
SK626-95A SK62695A3 (en) 1992-11-12 1993-11-02 Switching circuit
KR1019950701872A KR950704844A (ko) 1992-11-12 1993-11-02 스위칭 장치(switching arrangement)
BG99627A BG99627A (en) 1992-11-12 1995-05-11 Reswitching device
NO951862A NO951862L (no) 1992-11-12 1995-05-11 Koplingsanordning
FI952317A FI952317A (fi) 1992-11-12 1995-05-12 Kytkentäjärjestely

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB929223773A GB9223773D0 (en) 1992-11-12 1992-11-12 Switching arrangement
GB9223773.4 1992-11-12

Publications (1)

Publication Number Publication Date
WO1994011936A1 true WO1994011936A1 (fr) 1994-05-26

Family

ID=10725000

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1993/002249 WO1994011936A1 (fr) 1992-11-12 1993-11-02 Agencement de commutation

Country Status (21)

Country Link
EP (1) EP0669049A1 (fr)
JP (1) JPH08503357A (fr)
KR (1) KR950704844A (fr)
CN (1) CN1089403A (fr)
AU (1) AU5375094A (fr)
BG (1) BG99627A (fr)
BR (1) BR9307421A (fr)
CA (1) CA2148362A1 (fr)
CZ (1) CZ124695A3 (fr)
FI (1) FI952317A (fr)
GB (1) GB9223773D0 (fr)
HU (1) HUT73624A (fr)
IL (1) IL107573A (fr)
MX (1) MX9307078A (fr)
NO (1) NO951862L (fr)
PL (1) PL308764A1 (fr)
RU (1) RU95112565A (fr)
SK (1) SK62695A3 (fr)
TR (1) TR28861A (fr)
TW (1) TW280046B (fr)
WO (1) WO1994011936A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996014684A1 (fr) * 1994-11-02 1996-05-17 Raychem Corporation Dispositif transistorise reinitialisable assurant la protection contre les surintensites
EP0766362A2 (fr) * 1995-09-29 1997-04-02 Motorola, Inc. Elément de protection et méthode pour protéger un circuit
US5768341A (en) * 1992-11-12 1998-06-16 Raychem Limited Communications channel testing arrangement
US6160693A (en) * 1997-06-10 2000-12-12 Oy Lexel Finland Ab Short circuit protection for a semiconductor switch
US6617069B1 (en) 1998-09-16 2003-09-09 George Frederick Hopper Battery over-discharge protection
WO2015022017A1 (fr) * 2013-08-13 2015-02-19 Hewlett-Packard Development Company, L.P. Protection de lignes de communication contre les courts-circuits
EP3041103A1 (fr) * 2014-12-29 2016-07-06 Rockwell Automation Limited Protection de circuit
CN109462328A (zh) * 2018-10-30 2019-03-12 深圳市航天新源科技有限公司 一种具有多种输入保护功能的低损耗双向开关电路

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008001114A1 (de) * 2008-04-10 2009-10-15 Robert Bosch Gmbh Steuerschaltung und Steuerverfahren für Glühstiftkerzen zum Schutz vor Verpolung
US8169763B2 (en) * 2008-06-26 2012-05-01 Bourns, Inc. Transient blocking unit having an enhancement mode device in the primary current path
US9537326B2 (en) * 2009-04-16 2017-01-03 Valence Technology, Inc. Batteries, battery systems, battery submodules, battery operational methods, battery system operational methods, battery charging methods, and battery system charging methods
CN103280996B (zh) * 2013-06-28 2016-04-27 上海坤锐电子科技有限公司 多电荷泵结构的整流电路
TWI497867B (zh) * 2014-02-24 2015-08-21 台達電子工業股份有限公司 輸出電源保護裝置及其操作方法
JP6309855B2 (ja) * 2014-07-31 2018-04-11 株式会社東芝 レギュレータ回路
CN106611945A (zh) * 2015-10-21 2017-05-03 天地融科技股份有限公司 一种线路保护电路及通信设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0142128A1 (fr) * 1983-11-11 1985-05-22 Siemens Aktiengesellschaft Disposition d'un circuit pour le drainage de surtensions
US4618743A (en) * 1984-11-27 1986-10-21 Harris Corporation Monolithic transient protector

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0142128A1 (fr) * 1983-11-11 1985-05-22 Siemens Aktiengesellschaft Disposition d'un circuit pour le drainage de surtensions
US4618743A (en) * 1984-11-27 1986-10-21 Harris Corporation Monolithic transient protector

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768341A (en) * 1992-11-12 1998-06-16 Raychem Limited Communications channel testing arrangement
WO1996014684A1 (fr) * 1994-11-02 1996-05-17 Raychem Corporation Dispositif transistorise reinitialisable assurant la protection contre les surintensites
EP0766362A2 (fr) * 1995-09-29 1997-04-02 Motorola, Inc. Elément de protection et méthode pour protéger un circuit
US5684663A (en) * 1995-09-29 1997-11-04 Motorola, Inc. Protection element and method for protecting a circuit
EP0766362A3 (fr) * 1995-09-29 1998-04-01 Motorola, Inc. Elément de protection et méthode pour protéger un circuit
US6160693A (en) * 1997-06-10 2000-12-12 Oy Lexel Finland Ab Short circuit protection for a semiconductor switch
US6617069B1 (en) 1998-09-16 2003-09-09 George Frederick Hopper Battery over-discharge protection
WO2015022017A1 (fr) * 2013-08-13 2015-02-19 Hewlett-Packard Development Company, L.P. Protection de lignes de communication contre les courts-circuits
US20160180203A1 (en) * 2013-08-13 2016-06-23 Hewlett-Packard Development Company, L.P. Protection of Communication Lines
EP3041103A1 (fr) * 2014-12-29 2016-07-06 Rockwell Automation Limited Protection de circuit
CN109462328A (zh) * 2018-10-30 2019-03-12 深圳市航天新源科技有限公司 一种具有多种输入保护功能的低损耗双向开关电路

Also Published As

Publication number Publication date
FI952317A0 (fi) 1995-05-12
CN1089403A (zh) 1994-07-13
TR28861A (tr) 1997-07-28
KR950704844A (ko) 1995-11-20
IL107573A (en) 1996-09-12
AU5375094A (en) 1994-06-08
JPH08503357A (ja) 1996-04-09
CZ124695A3 (en) 1995-12-13
PL308764A1 (en) 1995-08-21
NO951862D0 (no) 1995-05-11
CA2148362A1 (fr) 1994-05-26
NO951862L (no) 1995-05-11
MX9307078A (es) 1994-05-31
IL107573A0 (en) 1994-02-27
BR9307421A (pt) 1999-08-31
FI952317A (fi) 1995-05-12
HUT73624A (en) 1996-08-28
HU9501359D0 (en) 1995-06-28
GB9223773D0 (en) 1992-12-23
TW280046B (fr) 1996-07-01
EP0669049A1 (fr) 1995-08-30
BG99627A (en) 1996-01-31
RU95112565A (ru) 1996-12-27
SK62695A3 (en) 1996-01-10

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