WO1992014217A1 - Processeur compatible avec des memoires prom et procede de lecture/ecriture correspondant - Google Patents

Processeur compatible avec des memoires prom et procede de lecture/ecriture correspondant Download PDF

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Publication number
WO1992014217A1
WO1992014217A1 PCT/JP1992/000105 JP9200105W WO9214217A1 WO 1992014217 A1 WO1992014217 A1 WO 1992014217A1 JP 9200105 W JP9200105 W JP 9200105W WO 9214217 A1 WO9214217 A1 WO 9214217A1
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WO
WIPO (PCT)
Prior art keywords
data
address
input
bit
output
Prior art date
Application number
PCT/JP1992/000105
Other languages
English (en)
Japanese (ja)
Inventor
Junichi Kodama
Hajime Nishidai
Susumu Ishiguro
Kazuhisa Shimizu
Fumikazu Imae
Original Assignee
Omron Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corporation filed Critical Omron Corporation
Publication of WO1992014217A1 publication Critical patent/WO1992014217A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format

Definitions

  • PROM p rog r ammab lere ad-on ly memo ry
  • the processors are the address bus, data, and data on the system. Connected to the nose and control nose. Then, the processor obtains input data from the circuit devices connected to these buses, executes a predetermined process, and executes processing of the other devices. By performing control, driving, and the like, execution of the predetermined processing of the above system is realized.
  • the purpose of the present invention is to make it possible to easily add a new processor without redesigning the circuit of an existing system. .
  • This invention also provides a processor and processor that can replace existing PROMs used in computer's systems.
  • the purpose is to provide a Gy processor.
  • This invention can be further replaced with existing PROMs.
  • the aim is to provide a PR0M compatible processor that does not drastically reduce the R0M space and can be used sufficiently even in small-scale systems. Target.
  • the present invention provides a method of reading data from such a processor, a method of transferring data Z, a method of transferring input data, and a method of writing data.
  • the purpose is.
  • the PR0M connector and the chip-fuzzy processor according to the first invention have a plurality of address input terminals, and address data. Simulated address data that includes data and input data and is input to the address input terminal, and is specified by the address data.
  • Ad The storage is provided with a storage means for storing the above input data in the lesson.
  • the PR0M connector, the ° fuzzer, and the processor include a plurality of address input terminals, a plurality of data input / output terminals, and a plurality of data input / output terminals.
  • Input data storage means for storing the type of input data corresponding to the address, and output data for storing the output data to be output corresponding to the address.
  • a bit representing the read light and address data or data in the case of the read is composed of address data and input data in the case of an it, and is included in the pseudo address given to the above address input terminal.
  • the PR ⁇ M compatible fuzzy processor above is additionally equipped with additional power, pre-configured runners and memberships. According to the function, the fuzzy inference is performed using the input data stored in the input data stage. It is provided with fuzzy inference operation means for performing processing and storing the result as output data in the output data storage means.
  • the PR0M connector and ° table have the same pin arrangement as the fuse processor power PROM.
  • pin number 1 is the program power supply
  • pin number 2 is the address input bit 12
  • pin number 2 is the address input pin 7
  • pin number 3 is the address input pin 7.
  • Bit, pin number 4 Bit 6 of the address input, pin 5 is bit 5 of the address input, pin 6 number 6 of the address input No. 4 bit, pin No. 7 force Address input, No. 3 bit, pin No. 8 force ⁇ Address input No. 2 bit, pin No. 9 force address Bit 1 of input, pin number ⁇ 0 is bit 0 of address input, pin number ⁇ is bit 0 of data input / output, pin number 12 is data No.
  • pin number ⁇ is the second bit of data input / output
  • pin number 14 is ground
  • pin number 15 is the third bit of data input / output
  • pin number 16 is data input / output 4th bit
  • pin number 18 is the data input / output bit 6
  • pin number 19 is the data input / output bit 7
  • pin number 2 G is a chip enable 1G bit with pin number 21 for address input, pin number 22 for output enable input, pin number 23 for address input 1 bit
  • pin number 24 are 9 bits for address input
  • pin number 25 is 8 bits for address input
  • pin number 26 is Address input bit 13 and pin number 27 are assigned to the address input bit 14 and pin number 28 to the power supply, respectively. It is.
  • the first invention can be applied not only to a fuzzy processor but also to a processor that performs processing other than fuzzy arithmetic processing.
  • a general processor includes a plurality of address input terminals, an address, data, and input data, and the address processor described above. Pseudo address data to be input to the address input terminal is fetched, and the input data is stored in the address specified by the address data. We have the means.
  • the general processor according to the first invention also has a plurality of address input terminals, a plurality of data input / output terminals, and an input / output terminal corresponding to an address.
  • Input data for storing and storing output data
  • output data storage means for storing output data to be output in correspondence with the address, and resources to be provided.
  • a bit representing a read Z light In response to a read instruction, a bit representing a read Z light, and address data or a write in the case of a read.
  • Including address data and input data The bit representing the read Z light included in the pseudo address data provided to the above-mentioned address input terminal is determined.
  • the output data at the storage location specified by the address data of the output data storage means is output to the data input / output terminal.
  • the input data is stored in the storage location specified by the address data in the input data storage means. Equipped with input / output control means for controlling storage.
  • the above processor preferably has a PR0M-compatible pin K arrangement.
  • the first invention also provides a method for reading Z-light of data to the processor by CPU.
  • the CPU and the processor are connected by an address bus and a data node.
  • the pseudo address data transferred on the bus is a bit representing a read / write, and if the pseudo address data is a read, the address data or It is composed of address data and input data in the case of light, and the above-mentioned processor is used to read data on the address node.
  • An input / output control unit for identifying Z-light bits is provided.
  • the CPU sets the pseudo address data on the address bus, and sets the pseudo-address data on the address bus. And outputs a read instruction, and includes the pseudo address, data, and power read bits described above.
  • the data transferred through the data bus is fetched, and when the pseudo address data contains a write bit, the data is read.
  • the input / output control unit ignores the data on the data bus, and the input / output control unit responds to the read command, and the input / output control unit reads the data on the address bus.
  • ⁇ When a bit is identified, the data to be transferred to the CPU is output to the data bus, and when a light bit is identified, the above pseudo code is output. It is characterized by taking in input data in address data.
  • the first invention also relates to a method for transferring data from a CPU to a processor connected by an address bus and a data bus.
  • a read-write method is provided, in which pseudo address data transferred on an address bus is read-z-right. , And address data in the case of lead or address data and input data in the case of light.
  • the CPU sets pseudo address data including a read bit on the address bus, and A read instruction is output, and then the data transferred via the data bus is fetched.
  • the write bit is written.
  • Set pseudo address data including address on address bus, output read instruction, and ignore data on data bus This is characterized by "?
  • the first invention further provides a data Z-reader for a processor connected to the CPU by an address bus and a data bus.
  • the above-mentioned processor has an input / output control unit for identifying a D-Z light bit on an address, and the above-mentioned processor is provided with the above-mentioned CPU or not.
  • the input / output control unit identifies the lead bit on the address bus. At that time, the data to be transferred to the CPU is output to the data base, and when the write bit is identified, the address bus is transferred. Further, the present invention is characterized in that the input data in the pseudo address data is fetched.
  • the processor has a PR0M compatible pinout.
  • PROMs are available in pin type and 32 pin type. If it is compatible with the PR0M with a processor power of 28 pins, the processor has 28 pins, and pin number 1 is the program number.
  • Ram power supply pin number 2 power ⁇ address input 12 bits, pin number 3 power ⁇ address input 7 bits, pin number 4 power ⁇ address Input 6 No. 5 bit, pin number 5 is address input No. 5 bit, pin number 6 is address input no. 4 bit, pin number 7 is address input. No. 3 bit, pin number 8 ⁇ Address No. 2 bit, pin number 9 is address input No.
  • pin number 10 is address Bit 0 of data input
  • pin number 11 is bit 0 of data input / output
  • pin number 12 is bit 1 of data input / output
  • pin number 13 Is the second hit for data input / output
  • pin number 14 is grounded
  • pin number 15 is third bit for data input / output
  • pin number 16 is data input / output.
  • No. 4 bit pin No. 17 is data input / output No. 5 bit
  • pin No. 18 is data input / output No. 6 bit
  • pin No. 19 Is the data input / output 7 Bit / Pin No. 20 is a chip. • Enable input, Pin No. ⁇ is an address input. Bit 10 and Pin No. 22 are outgoing.
  • pin input pin number 23 is address 1 bit 11
  • pin number 24 is address 9 bit
  • pin number 25 is address The 8th hit of the input
  • the pin number 26 is the 13th hit of the address input
  • the pin number 27 is the 14th bit of the address input, and so on.
  • pin numbers 28 are respectively assigned to the power supplies.
  • the first invention further provides a method of transmitting input data to a processor, which method comprises the steps of: providing a CPU with input data to be processed; The pseudo address data including the input data and the identification code of the input data is set on the address bus, and a read instruction is output to the CPU.
  • Ad In response to the above read instruction, the processor connected by the Lesnos has changed the input data on the address bus to the above identification code. Therefore, it is characterized in that it is taken into a predetermined storage means.
  • processor force PR0 is provided with a compatible pin arrangement.
  • the input and control of data to the processor according to the first invention uses pseudo address data, and the pseudo address data is stored in the address. ⁇ It is done by transferring on the bus. As a result, no special terminals are required for writing evenings to this processor. Therefore, the processor according to the first invention is
  • the processor according to the first aspect of the present invention can have the same size, the same number of pins, and the same pin arrangement as the existing PROM, so that the existing system can be used.
  • the circuit board of the item On the circuit board of the item
  • Input data to the processor according to the invention of You can control this by using the system's address bus. No special terminal is required for writing data to the processor according to the first invention.
  • the CPU makes the access to the port processor according to the first invention completely the same as the access to the PROM (control sequence). Signal and control timing), and the processor can be operated.
  • the PR0M connector according to the second invention.
  • the chip fuzzy processor is incremented each time a plurality of address input terminals and the first clock signal are supplied.
  • a memory device consisting of an address counter and a memory whose address is specified by the output of the address counter. And a control code and input data, and the pseudo-address data input to the address input terminal is fetched, and the control code is written to the memory. Is displayed, the address counter is reset in response to the input of the first pseudo address data, and the subsequent pseudo address data is reset.
  • the first clock signal is used to generate the address count in response to the first clock signal.
  • the input data included in the pseudo address data to be input is in the order in which it is input, because the input data is not incremented.
  • a control means is provided for controlling the writing to successive addresses of the above memory sequentially.
  • the control means may be arranged so that the control code is read from memory.
  • the resetting of the address counter is performed when the signal indicates the output, and thereafter, the address is reset by the first clock signal at regular intervals. Read the data from the above memory according to the order of consecutive addresses, while not incrementing the above address counter. Control.
  • the control means writes data to the memory or reads data from the memory in response to a given read command.
  • the pseudo address data is stored in a subordinate of the memory.
  • the above-mentioned memory device including the address data, is transmitted from the above-mentioned control means every time data is written to or read from the above-mentioned memory.
  • the given second clock signal is counted, and when the counted value reaches the number of addresses represented by the lower address data, the above-mentioned signal is counted.
  • the first clock signal is output and supplied to the above-mentioned address counter, and the counter is reset and the counting is restarted from the beginning.
  • the output of the above address counter specifies the upper address of the above memory.
  • the control means is configured such that each time the pseudo address data is input, the lower address data included in the pseudo address data is input to the lower address data included in the pseudo address data.
  • the input data included in the above pseudo address data is a rule data representing a rule or a member representing a membership function. It is shipping function data.
  • the PR0M connector and the Fuzzy processor have a plurality of address input terminals, a plurality of data input / output terminals, and a plurality of data input / output terminals.
  • Input data storage means for storing the input data of each type corresponding to the address and output;
  • output storage means for storing the output data to be output corresponding to the address;
  • a control code representing the evening read Z light, and address data or data in the case of data read.
  • the control code indicating the data read / write included in the less data is determined, and When it is identified as the data read control code, the output data specified by the above-mentioned address data in the output data storage means is output.
  • the data is output to the data input / output terminal, and when the data is identified as a data control code, the input data is stored in the above-mentioned address data of the input data storage means. ⁇
  • An input / output control means for controlling the storage in the storage location designated by the evening, and the knowledge data is stored in the given order according to the given order.
  • Knowledge data storage means and a control that represents a knowledge light in response to a given read instruction A knowledge line which is configured to include the code and the knowledge data to be written, and is included in the pseudo address data given to the address input terminal.
  • the control code representing the data is determined, and the knowledge data included in the pseudo address data is sequentially stored in the knowledge data storage means according to the input order. Equipped with knowledge writing control means for controlling storage.
  • the above knowledge data is composed of rule data and member function data.
  • the PR0M connector and the fuzzy fuzzy processor are further arranged in accordance with the knowledge data stored in the knowledge data storage means. Fuzzy inference processing is performed using the input data stored in the input data storage means, and the result is stored in the output data storage means as output data. A fuzzy inference operation means is further provided.
  • PROM compatible means that the processor and the processor have the same pin configuration as the PROM.
  • PR0M has a 28-pin version and a 2-pin version.
  • the above fuzzy processor is 28 Pin number 1 is for program power supply, pin number 2 is for address input bit 12 and pin number 3 is for address input pin number 7.
  • Bit, Pi Pin No. 4 is the 6th bit of the address input, Pin No. 5 is the 5th bit of the address input, and Pin No. 6 is the 4th bit of the address input , Pin number 7 is the third bit of the address input, pin number 8 is the second bit of the address input, and pin number 9 is the first bit of the address input.
  • pin number 10 are address input 0 bit, pin number 11 is data input and output bit 0, and pin number 12 is data input and output The first bit of power, pin number 13 is the second bit of data input / output, the pin number 14 is grounded, and the pin number 15 is the third bit of data input / output.
  • Bit 4 is the data input / output bit 4 and pin number 17 is the data input / output bit 5 and pin number 18 is the data input / output.
  • 6th bit, Pin number 19 is the 7th bit of data input / output, pin number 2Q is the chip enable input, and pin number 21 is 10 of the address input.
  • pin No. 23 is address input No. 11 bit
  • pin No. 24 is address Bit 9 of input
  • pin number 25 is bit 8 of address input
  • pin number 26 is bit 13 of address input
  • pin number 27 Are assigned to the address input
  • bit 14 and pin number 28 are assigned to the power supply, respectively.
  • the second invention can be applied not only to a fuzzy processor but also to a processor that performs processing other than fuzzy arithmetic processing.
  • a general processor is a memory, A plurality of address input terminals to which a pseudo address signal including a control code representing a light and input data are provided, and the input data are arranged in a given order. ! ⁇ A pseudo address signal input to the address input terminal in response to the Sci tk storage means and a given read command represents a memory light. When it is determined that the control code is included, control is performed such that the input data included in the pseudo address signal is sequentially stored in the storage unit in the order of input. Equipped with control means
  • the control means is responsive to a given read command, wherein the pseudo address signal input to the address input terminal represents a control code representing a memory lead. If it is determined that the data includes the data, control is performed so that the data stored in the storage means is read out in the order of the address.
  • the storage means stores the sync signal every time the first clock signal is supplied.
  • the address control memory includes the address and memory to be measured and the memory whose address is specified by the output of the address counter.
  • Means resets the address * counter in response to the input of the first pseudo-address release signal, and resets the subsequent pseudo-address signal.
  • the first clock signal controls the address counter to be incremented by the first clock signal.
  • the pseudo address signal includes lower address data of the memory.
  • the storage means further includes a second clock provided from the control means for writing data to the memory or reading data from the memory during the night.
  • the first clock signal is counted when the counted value reaches the number of addresses represented by the lower address data.
  • the counter includes a counter which outputs the signal and gives it to the above address / output terminal, and which is reset by being reset and restarted from the beginning.
  • the output of the address counter is configured to specify the upper address of the above memory.
  • the control means supplies the lower address data included in the pseudo address signal to the storage means.
  • the second clock signal is generated.
  • the storage means further stores one of the first address output from the address counter and the other second address.
  • a switching means for giving an address signal to the memory is provided.
  • the processor has a PR0M compatible pinout.
  • the second invention is also the PR0M connector described above.
  • the present invention provides a memory device used in a processor or a general processor described above.
  • This memory device has upper and lower address terminals, and the lower address terminal includes an incre- ment for each data light or read.
  • the lower address signal is given and returned to the minimum value when the maximum value is reached.
  • the initial reset by the memory and reset signals is given.
  • the first clock signal given to each data light or lead is counted, and it is determined that the counted value has reached the maximum value of the lower address.
  • the second counter signal is generated at the same time, the first counter that is reset and starts counting from the beginning again, and the reset signal
  • the second clock signal which is initially reset by the counter and output from the first counter, is counted.
  • the number output that provides a second Ka c te of Ru applied to the upper ⁇ Drain scan signal to Kuraia de Re scan terminals on said Note Li.
  • the above-mentioned memory device should further be supplied to an upper address signal supplied from the above-mentioned second counter and to a lower address terminal of the above-mentioned memory.
  • an upper address signal supplied from the above-mentioned second counter and to a lower address terminal of the above-mentioned memory.
  • Another memory device is an address signal for generating a first address signal sequentially incremented from an initial address.
  • Generating means and the above address signal Address switching means for selecting and outputting one of a first address signal generated from the generating means and a second address signal supplied from outside;
  • An address signal output from the address switching means is composed of a memory and a power applied to an address terminal.
  • the second invention further provides a method for reading and writing data to the processor by the CPU.
  • the CPU and the processor are addressless.
  • Pseudo-address / data-power-read which is connected by the address and data-noss and is transferred on the address bus And the input data in the case of a light
  • the above-mentioned processor includes a control code on the address bus.
  • Control part for identifying the Z-light control code, and the storage location of the data to be read or written according to the order of the addresses.
  • a memory section having an address generating means for specifying the pseudo address data.
  • the CPU stores the pseudo address data on an address bus. And outputs a read instruction. If the pseudo-address-data-power-read control code is included, the data is read.
  • the data transferred through the bus is fetched, and when the pseudo address data includes a light control code, the data on the data bus is read.
  • the processor ignores the data and the processor responds to the read instruction.
  • the control unit identifies the lead control on the address bus, the control unit causes the address generation means to specify the next address.
  • the data is read out from the memory unit and output to the data *, and when the light control code is identified, the address generation means is used.
  • the input data in the pseudo address data is stored in the memory unit. It is.
  • the light method according to the second invention is such that the CPU and the processor are connected by an address bus and a data bus.
  • the pseudo address data transferred on the bus includes control data representing a light and input data, and the above process is performed.
  • the control unit identifies the light control code on the address bus and the storage location of the data to be written according to the address order.
  • the CPU sets the pseudo address data on an address bus. , And outputs a cache instruction. If the pseudo address data includes a write control data, the data bus is output. If the processor responds to the read command and the control unit identifies the light control code, the address generation means will be ignored.
  • the above pseudo address directory is stored in the above memory section. It is characterized by storing the input data during the evening.
  • the second invention further includes a CPU for relocating data to the processor which is connected to the CPU by an address and a data bus. It offers a Z-lighting method.
  • This read-write Z-light method uses a control code in which pseudo address data on the address bus represents a read / write. And the input data in the case of a light, and the above-mentioned CPU, at the time of a read, reads pseudo address data including a read control data. It sets on the dress bus, outputs a read instruction, and then fetches the data transferred through the data bus. Sets the pseudo address data including the light control command on the address and the bus, outputs the force and output read instructions, and outputs the data on the data bus. It is characterized by neglecting the above data.
  • the second invention further includes a data storage device connected to the CPU and an address bus, and a data connection device to the processor connected by the data connection bus. It provides both a write and write method.
  • a method for reading / writing data wherein pseudo-address data transferred on an address bus is a read-Z line.
  • Control code that represents the And a control unit for identifying a read / write control code on an address bus.
  • a memory having an address generation means for specifying a storage location of data to be read or written in an order of addresses.
  • the processor recognizes that the control unit has identified the lead control code on the address bus in response to the read command.
  • the next address is designated by the above address generation means, so that the data is read from the above memory section and output on the data path, and
  • the control code is identified, the following address must be specified in the above address generation means.
  • the input data in the pseudo address data is stored in the memory section.
  • the CPU according to the second invention, the address bus, and the data write method for the processor connected by the data bus are as follows.
  • the pseudo address data transferred on the address bus includes a control code representing a light, and input data.
  • the processor includes a control unit for identifying a light control code on the address bus, and a data to be written using the sequential force of the address.
  • a memory unit having an address generation means for designating a storage location of the data storage unit. Is light-controlled
  • the code is identified, the following address is designated by the above address generating means, so that the above pseudo address data is stored in the above memory section. Characterized in that the input data in the data is stored.
  • the above-mentioned mouth sensor has a PR0M compatible pin arrangement.
  • PR0M P Available on PR0M are 28-pin type and 32-pin type.
  • pin number 2 is an address, a 1-bit input for a less input, pin number 3 is a 7-th address for an address input, and a 4 pin number.
  • Pin number 5 is the fifth bit of the address input
  • pin number 6 is the fourth bit of the address input
  • pin number 7 is the third bit of the address input.
  • pin number 8 is the second bit of the address input
  • pin number 9 is the first bit number of the address input 10 is the 0th bit of the address input
  • pin number 11 are data input / output bit
  • pin number 12 is data input / output bit 1 and pin number 13 is data input / output.
  • No. 2 bit, No. 14 pin is grounded, No. 15 pin No. 3 bit for evening input / output, No. 16 pin is No. 4 bit for data input / output No.
  • pin No. 1 7 is data input / output No. 5 c: cut, pin No. 18 is data input / output No. 6 bit, pin No. 19 is data input / output No. 7 bit
  • pin numbers 20 Chip input, pin number 21 is address input, Q bit, pin number 22 is output enable input, pin number 23 is address input. Bit 11 of address input, pin number 24 is bit 9 of address input, pin number 25 is bit 8 of address input, pin 4 Pin No. 26 is for address input 13 bits, Pin No. 27 is for address input 14 bits, and Pin No. 28 is for power supply. Each has been assigned.
  • the input and control of data to the processor according to the second invention uses pseudo address data including a control code and data to be input. This is done by transferring this pseudo-address data on the address bus.
  • the input data contained in the pseudo address data is stored in the memory in the order of the input. O No special terminals are required for writing data to this processor.
  • the processor according to the second invention into a PR0M and a computer that can be used only for reading CPU power data. it can .
  • the processor according to the second invention can have the same size, the same number of pins, and the same pin arrangement as the existing PROM. This makes it possible to mount the processor according to the second invention on a PROM socket on the circuit board of an existing system. . This allows for the installation of existing circuits. Without changing the system, you can replace the device and add or change some software for the CPU. O Function expansion and function addition are possible.
  • the input of data to the processor and the control thereof according to the second invention can be performed by using the address of the system. No special terminal is required for writing data evenings to the processor according to this invention. From the viewpoint of the CPU, the CPU makes the access to the port processor according to the second invention completely the same as the access to the PROM (control signal). , And control timing) and operate the processor.
  • the input data included in the pseudo address * data is written into the memory according to the order of the input. This eliminates the need to specify an address, and makes it possible to write large amounts of data to memory.
  • the PR0M compatible fuzzy processor according to the third invention has a control code assigned to a higher-order bit. Multiple address input / output terminals to which the signal is applied, multiple data input / output terminals, chip enable signal input / output terminals, and output enable The signal input terminal and the address terminal are connected to the address input terminal except for the input terminal to which the control code is given, and the data terminal is connected to the data input / output. Output terminal A data terminal connected to the output cable signal input terminal, and a chip enable signal supplied to the chip enable signal input terminal.
  • a light enable signal creating means for creating a light enable signal based on the light enable signal and giving the light enable signal to the light enable terminal of the data storage means, and When the control code given to the address input terminal is decoded, and the control code specifies the data storage means, the data storage means is read. And a chip select means for supplying a chip enable signal to the chip.
  • the light enable signal generating means generates a light enable signal in response to an output enable signal applied to the output enable signal input terminal. Is prohibited.
  • the PR0M compatible bus processor detects that the address signal supplied to the address input terminal has changed.
  • Address switching signal generating means for generating an address switching signal, wherein the light enable signal generating means includes a chip enable signal and a chip enable signal. A light enable signal is generated in response to the address switching signal.
  • the data storage means stores first input means for storing input data on input variables and output data representing an operation result.
  • You The light enable signal is supplied to the first storage means, and is supplied to the output enable signal input terminal.
  • the output enable signal is supplied to the second storage means, and the chip enable signal is supplied to the first or second storage means according to the control code. Given to the means.
  • the PR0M Compatible Processor, Fuzzy Processor is also used for pre-defined run-time and member-ship functions. Therefore, fuzzy inference processing is performed using the input data stored in the first storage means, and the result is used as the output data in the fuzzy inference processing.
  • the storage means of (2) is further provided with a fuzzy inference operation means to be stored.
  • the address terminal is the address except for the input terminal to which the control code is given.
  • the data input terminal is connected to the data input / output terminal
  • the output enable terminal is connected to the output enable signal input terminal
  • the member is connected.
  • a knowledge data storage means for storing data representing a sip function and a rule is further provided. And, when the light enable signal and the control code specify the knowledge data storage means, the chip output is output. The enable signal is provided to the knowledge data storage means.
  • a program power supply terminal is provided, and a program power supply terminal is provided to the program power supply terminal by a PROM writer. Since the program power is given to the knowledge data storage means, the knowledge data storage means of the data representing the membership functions and the rules is provided. Is written to.
  • PR0M compatible means that the processor and the processor have the same pin arrangement as the PROM.
  • Pin No. 1 is the program power supply
  • Pin No. 2 is the 12th bit of the address input
  • Pin No. 3 is the 7th bit of the address input
  • Pin No. 4 force ⁇ Address input No. 6 bit Pin No. 5 force Address input No. 5 bit
  • Pin No. 6 force Address input No. 4 Bit 3 pin number 7 is address input
  • bit 3 is pin number 8
  • pin number 2 is address input
  • pin number 9 is input.
  • Bit 1 and pin number 10 are bit 0 of the address input
  • pin number 11 is bit 0 of the data input and output
  • pin number 12 is the data input and output.
  • Pin Number one in power Bit and pin number 13 are data input / output bit 2, pin number 14 is grounded, pin number 15 is data input and output bit 3 and pin number 16 is data input and output.
  • No.4 bit for data input / output Pin No. ⁇ is the 5th bit of data input / output
  • Pin No. 18 is the 6th bit of data input / output
  • Pin No. 19 is the 7th bit of data input / output.
  • the chip and pin number 20 is the chip enable input
  • the pin number 21 is the address input 1 bit Q
  • the pin number 22 is the output port.
  • Cable input, pin number 23 is 11th bit of address input, pin number 24 is 9th bit of address input, and pin number 25 is address No. 8 bit of the less input
  • pin No. 26 is the No. 2 bit of the address input
  • no. 27 is the No. 14 bit of the address input
  • Pin numbers 28 are assigned to the power supplies, respectively.
  • the third invention is applicable not only to fuzzy processors but also to processors or other devices that perform processing other than fuzzy arithmetic processing. is there .
  • the general processor according to the third invention includes a plurality of addresses to which an address signal in which a control code is assigned to a high-order bit is given.
  • the above mentioned input terminals except for the input terminals to which the above-mentioned control code is given are input terminals, multiple data input / output terminals, chip * enable signal input terminals, and address terminals.
  • Data storage means connected to the dress input terminal, and the data terminal connected to the data input / output terminal, the chip enable signal input terminal A light enable signal is created on the basis of the chip enable signal given to the light enable signal, and the light enable signal of the data storage means is generated.
  • the chip storage means is provided with a chip select means for giving a chip enable signal.
  • This general processor also has an output enable signal input terminal, and the above-mentioned light enable signal generating means is provided with the above output enable signal input terminal. Prohibits the generation of the light enable signal in response to the output enable signal applied to the pin.
  • the above-mentioned general processor further detects that the address signal supplied to the above-mentioned address input terminal has changed, and outputs the address switching signal.
  • a means for generating an address switching signal to be generated is provided, wherein the light enable signal generating means responds to the chip / enable signal and the address switching signal. To generate a light enable signal.
  • a device having a storage means in which input data is written and lacking a light enable signal input terminal for writing data.
  • a light enable signal is created based on the chip enable signal supplied to the enable signal input terminal, and the light enable signal of the storage means is generated.
  • a means for creating a light enable signal to be applied to the unbalanced terminal, and decoding the control code given to the address input terminal to decode the control code Chip select means is provided for supplying a chip enable signal to the storage means when the storage means is designated.
  • the address input terminals except for the input terminal to which the control code is given out of the address input terminals are connected to the address terminals of the storage means. Connected o
  • the above device further includes an output enable signal input terminal, and the light enable signal generating means includes an output enable signal input terminal provided to the output enable signal input terminal. Disables the generation of the light enable signal in response to the cable enable signal.
  • the above-mentioned device detects an address and a change in the address signal applied to the above-mentioned address input terminal, and generates an address switching signal by generating an address switching signal.
  • the light enable signal generating means further includes a generating means, and the light enable signal generating means responds to the chip enable signal and the address switching signal in response to the light enable signal. Generates a enable signal.
  • the processor or device described above is preferably provided with a PR0M compatible pinout.
  • the third invention also provides a method for evening lighting on a processor or device.
  • a data writing method including a storage unit into which input data is written, and a light enable signal input terminal for writing data is omitted.
  • the control code included in the address signal is decoded, and if the control code specifies the storage means, a second chip I is stored in the storage means.
  • a light enable signal is created based on the first chip enable signal, and the light enable signal is generated.
  • the light enable signal is changed. Create a signal.
  • the control code and the address of the storage means are written.
  • An address signal comprising the specified address and data is used.
  • the above-mentioned processor does not have a light enable signal input, so the host CPU power supplies the received rat signal (light enable signal). ) Is not entered in the above process.
  • the above processor has a chip enable signal (chip select signal) given from the host CPU and the above address signal and the data to be written. Data is input.
  • the processor decodes the control code included in the address signal, and decodes the control code. If the above-mentioned control code specifies the above-mentioned storage means, the chip-level signal is given to the above-mentioned storage means and the above-mentioned input chip-level signal is inputted. Based on the above, a light enable number is created and given to the storage means. Since input data is given to the above-mentioned storage means data terminal, the chip given to the storage means is replaced by a signal of the upper end of the recording. ⁇ The input data in the storage means is written by the enable signal and the it enable signal. The input data can only be written to the memory location specified by the address signal.
  • the address signal changes every write cycle, so this change is detected and the write size is detected.
  • a light enable signal is created for each class.
  • the processor according to the third invention is capable of damaging data without having a light enable terminal.
  • the existing PROM is read-only. It does not have a light enable terminal. Therefore,
  • the processor according to the third invention can be made compatible with existing PROMs (ie, compatibility). That is, the processor according to the third invention can be used.
  • the processor can be exactly the same size, number of pins, and pin layout as the existing PROM. Therefore, the processor according to the third invention can be mounted on the PR0M socket on the circuit board of the existing system. . This allows for the replacement of devices and the addition or modification of a small amount of software for the CPU without changing the design of existing circuits. With this, system functions can be extended and functions can be added.
  • the PROM compatible processor of the first to third inventions described above has the same pin arrangement as a commercially available PROM.
  • the PROM socket is located on the PROM socket on the circuit board of the station. Chip It is possible to mount a le processor. This allows for the replacement of devices and the addition or modification of a small amount of software for the CPU without changing the design of existing circuits. This makes it possible to extend system functions and add functions.
  • PR0M is a PR0M compatible plug-in set-up that contributes to system expansion but has only a single PR0M or is small.
  • PR0M there is a problem that the original PROM will be lost or the R0M space will be reduced if it is replaced.
  • the fourth invention does not significantly reduce the ROM space even if it is replaced with an existing PROM, and is a PR0M compatible that can be sufficiently used even in a small-scale system. It provides a processor.
  • a PR0M connector In response to a read command given to the above read command input terminal, a predetermined bit of the address signal given to the above address input terminal issues a write command. While displaying the data, the data represented by the data bits included in the above address signal is fetched, The memory indicated by the address bit included in the above address signal when the above predetermined bit card command is indicated.
  • An internal processor that outputs data representing the processing result from the address to the above data output terminal, and responds to a read instruction given to the above read instruction input terminal.
  • An internal ROM for outputting data of an address specified by an address signal applied to the address input terminal to the data output terminal, and Responds to a predetermined state of at least one of the address signal given to the address input terminal and the read command given to the read command input terminal. Then, a switching circuit for selecting either the internal processor or the internal ROM is provided. For example we have that.
  • the switching circuit switches between the internal processor and the internal ROM in response to the length of a signal representing a read command supplied to the read command input terminal, or In response to detecting that the address signal applied to the address input terminal represents a specific address, the internal processor is configured to respond to the detection of the specific address. It is configured to switch between the processor and the internal ROM.
  • the switching circuit is configured to transfer a data bus from the internal processor to the data output terminal and a data bus from the internal ROM to the data output terminal. It is configured to include a switching multiplexer, or Are the address bus from the address input terminal to the internal processor, and the address bus from the address input terminal to the internal ROM.
  • the first demultiplexer that switches between the input and output lines, the line from the read instruction input terminal to the internal processor, and the read instruction input And a second demultiplexer for switching from the input terminal to the line to the internal ROM.
  • the PROM can be used as the internal ROM installed in the PR0M programmable processor according to the fourth invention.
  • a ROM that does not allow external electrical writing such as a mask programmable ROM, can be used.
  • the PR0M programmable processor when a PROM is used as the internal ROM, the PR0M programmable processor according to the fourth invention is configured as follows. It is done. That is, the PR0M programmable processor has a plurality of address input terminals, a plurality of data input / output terminals, a read instruction input terminal, and a program instruction terminal. In response to a read command given to the RAM power input terminal and the above read command input terminal, a predetermined bit of the address signal given to the above address input terminal is changed. When indicating a light command, the data indicated by the data bit included in the above address signal is fetched and the specified bit is read. Address bit included in the above address signal when the bit represents a read command.
  • An internal processor that outputs data representing the processing result from the memory address represented by the data input / output terminal to the above data I / O terminal, and the above read instruction input In response to the read command given to the terminal, the data of the address specified by the address signal given to the above address input terminal.
  • the internal ROM that outputs data to the data input / output terminals described above, and responds to the length of the signal representing the read command given to the read command input terminal and responds to the length of the internal program
  • the first switching circuit that selects either the setter or the internal ROM, and the program power supply voltage applied to the program power input terminal, Switches the data transfer direction of the data bus connected to the data input / output terminal
  • a second switching circuit is provided.
  • the first switching circuit and the second switching circuit preferably include a data bus between the internal processor and the data input / output terminal and the data bus between the internal processor and the data input / output terminal.
  • a bus switching circuit for switching the direction of the data bus between the section R0M and the data input / output terminal and for switching the output.
  • the processors according to the first, second and third inventions can be used.
  • the PR0M compatible is because it has the same pin assignment as the processor power PROM according to the present invention. There are 28-pin PROMs and 32-pin PROMs on the market. In the case where the processor according to the fourth invention is a 28-pin PR0M compatible, the above-mentioned PR0M compatible busole processor is provided. Has 28 pins, pin number 1 is the program power supply, pin number 2 is the address input bit, and pin number 3 is the address input. No. 7 bit, pin number 4 No. 6 bit for input of address address, No. 5 pin No. 5 bit for input of address address, pin No. 6 is address Input bit 4 and pin number 7 are address input bit 3 and pin number 8 ⁇ Address input bit 2 and pin number 9 are address bits No.
  • pin number 10 is bit 0 of the address input
  • pin number 11 is bit 0 of the data input / output
  • pin No. 10 Number 1 2 is data input / output bit 1
  • pin number 13 is data input / output bit 2
  • pin number H is ground
  • pin number 15 is data input
  • pin number 16 is the fourth bit of data I / O
  • the pin number ⁇ is the fifth bit of data input / output
  • the pin number 18 is data.
  • pin number 19 is bit 7 of data input / output
  • pin number 2G is chip enable input
  • pin number 2 1 is the 10th bit of the address input
  • pin number 22 is the output enable input (read instruction input)
  • pin number 23 is the 1 of the address input.
  • Bit 1 and pin number 24 are address input 9th bit, pin number 25 is address input bit 8 and pin number 26 force add response
  • the 13th bit of input and the pin number ⁇ are assigned to the 14th bit of the address input, and the pin number ⁇ is assigned to the power supply, respectively.
  • the fourth invention is applicable not only to the fuzzy processor, but also to a processor that performs processing other than fuzzy arithmetic processing. Not bad.
  • the PR0 compatible processor according to the fourth invention has an internal processor and an internal ROM. Then, depending on the external read instruction or the specific state of the address signal, either the internal processor or the internal ROM can be selectively used. It can be accessed externally.
  • the PR0M connector and the ° C 'processor according to the fourth invention have both a function as a processor and a function as a ROM. These can be selectively switched and used.
  • Figure 1 is a block diagram showing the outline of a nodeware (computer's system) that has a host CPU and PROM as circuit devices. It is a figure.
  • Figure 2 shows an example of the pin arrangement of the PROM.
  • Figure 3 is a memory map showing the data arrangement of the four PROMs.
  • FIG. 4 is a block diagram showing a hardware circuit configuration including a fuzzy processor and a host CPU according to the first embodiment of the present invention. is there .
  • FIG. 5 is a block diagram showing a configuration of a fuzzy processor according to the first embodiment of the present invention.
  • Fig. 6 is a graph showing an example of the membership function.
  • Figures 7a and 7b show the format of the signals used to write the membership functions. Shows the address signal, and Fig. 7b shows the data signal.
  • Fig. 8a and Fig. 8p are examples of the address and data signals used to write the membership functions shown in Fig. 6. It indicates that
  • Figures 9a and 9b show the rules for writing rules.
  • the format of the signal used is shown in Fig. 9a, where the address signal is shown, and Fig. 9b shows the data signal.
  • Figures 10a to f show examples of address and data signals used when writing rule data.
  • Figures Ila to Ud show the format of the pseudo-address signal, respectively.
  • Fig. 12 is a flow chart showing the processing procedure of the host CPU for the fuzzy processor.
  • Fig. 13 to Fig. 15 are flow charts showing the processing procedure of the arithmetic unit in the fuzzy processor.
  • Fig. 5 shows another example of the format of the pseudo address signal.
  • FIG. 17 is a block diagram showing the configuration of a fuzzy processor according to a second embodiment of the present invention.
  • the figure shows a part of the format of the pseudo address signal.
  • Figure 19 shows the remaining part of the format of the pseudo address signal.
  • Figure 20 is a block diagram showing the details of the control unit in the fuzzy processor.
  • Figures 21 and 22 are graphs showing examples of member function.
  • Figure 23 shows an example of the contents of the member function memory.
  • Figure 24 shows an example of the contents of the memory.
  • Figure 25 is a block diagram showing the configuration of the rule and memory device.
  • Fig. 26 is a block diagram showing the structure of the member function memory device.
  • Fig. 5 is a flowchart showing the procedure for writing intellectual data by host CPU.
  • Fig. 28 is a flow chart showing the procedure for writing knowledge data in a fuzzy processor.
  • Fig. 29 is a flowchart showing the processing procedure for the fuzzy-floor opening processor of the host CPU.
  • FIG. 13 is a block diagram showing a hard-wired circuit configuration including a fuzzy D-processor and a host CPU according to a third embodiment of the present invention.
  • FIG. 34 is a block diagram showing a configuration of a fuzzy processor according to a third embodiment of the present invention.
  • Figures 35a to 35d and Figures 36a to 36b show the format of the address signals.
  • Fig. 37 shows the memory map of the fuji-p ⁇ processor. It is an indication of
  • Fig. 2 is a time chart showing the operation of generating a light enable signal.
  • Fig. 39 is a block diagram showing a modification.
  • Fig. 4 is a flow chart showing the processing procedure for the host processor in the fuzzy processor.
  • FIG. 41 is a block diagram showing a circuit configuration of a PROM compatible processor according to a fourth embodiment of the present invention.
  • Figures 42a and 42b are time charts showing the operation of the PROM compatible 'processor shown in Figure 41.
  • FIG. 43 is a block diagram showing a circuit configuration of a PR0M compatible 'processor according to a modification.
  • FIG. 44 shows a PROM connector according to still another modified example.
  • FIG. 2 is a block diagram showing a circuit configuration of a chip processor.
  • FIG. 45 is a block diagram showing a circuit configuration of a PR0M compatible processor according to still another modified example. Best mode for implementation First embodiment The first embodiment in which the present invention is applied to a 28-pin PROM (256 K notes) and a compatible processor is described in detail below. To state.
  • FIG. 1 shows an example of a hardware configuration in which the host CPU and PROM are used as circuit devices.
  • MC 000 is used as the host CPU
  • 256K bits (32K words x 8 bits) PR0M are used as PR0M. ing .
  • the host CPU 2Q has a 24-bit address bus (AO, ⁇ 1 to ⁇ 15, ⁇ ⁇ to ⁇ 23) and a 16-bit data bus (D0 to D7, D8 to D15).
  • PROMs 31 to 34 are provided. These PROMs are 15-bit address inputs A0 to A14 and 8 bits, respectively. Data input / output I / O 0 to 1
  • the PROM also has power supply V C program power supply V pp and ground V SP pins (not shown in Fig. 1).
  • PROM is Ri tail possess ⁇ number of pins (the input and output terminals), pin number 1 Gapu Russia gram power supply V pp, pin number 2 there de 12th of Les scan input bit A ⁇ 2, pin number 3 is the 7th bit of the address input ⁇ 7, pin number 4 is the 6th bit of the address input ⁇ 6, pin number 5 is the address 5th bit A5 of the address input, pin number 6 is 4th bit A4 of the address input, pin number 7 force ⁇ 3rd bit A3 of the address input , Pin No. 8 Force Address input, 2nd bit A2, Pin No. 9 is address input, 1st bit A1 and Pin No. 1Q is address.
  • pin number 11 is data I / O bit 0 IZO
  • pin number 12 is data I / O bit 1 1 1
  • Pin number 13 is the second bit of data I / O IZ 0 2
  • Number 14 is ground
  • Pin number 15 is data input / output 3
  • X 0 3 Pin No. 16 is the 4th bit of data input / output
  • Pin No. 17 is the 5th bit of data input / output
  • Pin No. 21 is address No. 10 bit A10
  • Pin No. 22 is outgoing enable input 0 ⁇
  • Pin No. 11 is address No. 11 bit Bit A11
  • pin number 24 is the ninth bit A9 of the address input
  • pin number 25 is the eighth bit A8 of the address input
  • bin number 26 is the address input ⁇ ⁇ 3 of the less input Bit A13
  • pin number 27 is the address input
  • bit 14 is A14
  • pin number 28 is assigned to the power supply V (; (; .
  • the host computer is connected to the address input terminals A0 to A14 of the CPUs A to N.
  • the data node of the host CPU 20 is used by being divided into lower data (LD) DO to D7 and upper data (UD) buses D8 to D15. It is.
  • Lower data bus D0 to D7 power PROM 31 and 33 data input / output terminals ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ , upper data bus D8 to D15 PROM 32 and 34 are connected to the data input / output terminals I / 00 to I07, respectively.
  • the decoder ⁇ outputs chip enable signals CE1 to CE4 for selecting any one of PR0M31 to 34.
  • This decoder contains address data A 16 to A23, LDS (Lower
  • the LDS signal is equivalent to the address signal AO.
  • the UDS signal is the inverse of the LDS signal.
  • the address strobe signal AS is a kind of timing signal indicating that the address signal has been output.
  • the host CPU 2Q selects PR0M31 or ⁇ , it outputs OCh (h indicates a hexadecimal number) as the address signal ⁇ ⁇ to ⁇ 23.
  • PROM 31 When PROM 31 is selected, L is output as the LDS signal and H is output as the UDS signal. As a result, the chip enable signal CE1 is output from the decoder 38 and is applied to the chip enable terminal CE of the PROM 31. When the PROM is selected, H is output as an LDS signal from the L-host CPU 20 as a UDS signal. A pull enable signal CE2 is output and applied to the chip enable terminal CE of PR0M32.
  • select address signal AO representing an even number (LDS signal power ⁇ L, UDS signal power ⁇ H), and PR 0 M ⁇ .
  • Address signal AO (the LDS signal is
  • the H and U DS signals output L), respectively.
  • the decoder 38 outputs a chip enable signal.
  • CE3 or CE4 is output and applied to PROM or 34 chip enable terminals CE.
  • the host CPU 20 also outputs a read light signal RW.
  • This signal RZW is transmitted via inverter 39 Supplied to output enable pin 0E of PROMs 31-34.
  • the host CPU 20 power (read instruction)
  • the output enable pin 0E of the PROM is set to L level, Signal is given (mouth, active) o
  • the host CPU 20 when reading the data of the predetermined address stored in the PROM 31, the host CPU 20 indicates the address indicating the address. Output signals A1 to A15, and output signals A16 to A23, for outputting the chip enable signal CET from the decoder ⁇ . Outputs LDS signal and UDS signal, and outputs H read signal (read instruction). As a result, the data stored in the memory location specified by the address of the PROM 31 is read, and the data input / output terminals I / O 0 to
  • this data is transferred to the host CPU 20 through the data buses D0 to D7.
  • any one of the other PR0Ms 32 to 34 can be used, or the data stored there.
  • the data read from the PROMs 31 and 33 are read from the data nodes DO to D7.
  • the data read from PR0M and 34 The data is input to the host CPU 20 via the data buses D8 to D15, respectively.
  • FIG. 3 A memory map showing such a read operation and the data arrangement in PR0M 31 to 34 is shown in Fig. 3.
  • the fuzzy processor according to the first embodiment of the present invention has exactly the same size, the number of pins, and the pin arrangement as PROMs 31 to 34. Yes. In other words, this fuzzy processor has the same appearance as that shown in Fig. 2. You can replace the leveraged fuzzy processor with any of the PROMs 31-34.
  • FIG. 4 shows a state in which the phage 'processor 40 according to the first embodiment of the present invention is replaced with the PROM socket in place of the PROM. It is.
  • the fuzzy processor 40 is connected to the host CPU 20 in exactly the same way as the PROM. The host CPU 20 then accesses the fuzzy processor 40 in the same manner as the access to the PROM, as described in more detail below. Access and write the input data to the fuzzy processor by using a read instruction (do not use a light instruction). And output data can be read. When writing input data to the processor 40, the transfer of control signals, addresses, and input data to be written is performed by an address. ⁇ Use Nos. A1 to A15 Is done. Reading data from a fuzzy processor is not done in the same way as reading data from a PROM.
  • the host CPU 20 becomes the decoder 3
  • the fuzzy and processor 40 can be selected.
  • Data read from the processor 4G is input to the host CPU 20 via the data buses D8 to D15.
  • FIG. 5 shows an example of the configuration of the fuzzy processor 40. And have you in view of this, the power supply V c c your good beauty ground V e. The terminals of are not shown.
  • the fuzzy processor 40 includes an input / output control unit 41, an input / output canister 42, a start decoder 43, an input register 44, and an output register. It has data 45, memory 46, processing control unit 47, operation unit 48, and 0R circuits 49a, 49b, and internal buses.
  • the input / output buffer 42 is used for address signals input to the address input terminals A0 to A14 from the PR0M light card and data input / output terminals 1 0.0 to 1/07 Control of the direction of data and evening signals input to 7 and switching to the internal bus, host CPU 20 power, and address input terminals A0 to A Given to 14
  • the I / O control unit is a PROM writer or host.
  • the input signals are input signals from ⁇ to ⁇ 14, and control signals for controlling signal switching and direction control in the input / output buffer 42 in response to these input signals are output. It controls the writing of input data to the input register 44 and the reading of output data from the output register 45 while outputting.
  • the start decoder 43 detects a start command given from the host CPU 20 based on the upper two bits AU to A14 in the pseudo address signal. Output to the processing control unit as a start signal.
  • the input register 44 stores the input data given from the host CPU 20.
  • the output register 45 stores output data representing the operation result.
  • the memory 46 stores the PROM writer power, the provided membership functions, and data representing the rules. O
  • the processing control unit 47 takes in input data from the input register 44, latches output data to the output register 45, and stores various data from the memory 46. It controls the reading of data and the arithmetic processing in the arithmetic unit 48.
  • the calculation unit 48 receives the input of the member function stored in the memory 46 and the output of the runner. Fuzzy arithmetic processing is performed using the input data stored in the register 44, and the result is given to the output register 45 as output data.
  • the writing of data representing the membership functions and the rules to the memory 46 of the fuzzy processor 40 is performed by a PROM It is done by an iter (or a ROM writer). This writing can be performed in exactly the same way as writing data to a normal PROM.
  • the memory 46 is a non-volatile memory, for example, PR0M or R0M.
  • the membership function is determined by giving the coordinates of multiple inflection points, and connects adjacent inflection points with a straight line. It has a shape obtained by this. In this embodiment, eight inflection points can be given.
  • the membership functions shown in Fig. 6 are as follows. It is defined by the number of inflection points.
  • the horizontal axis is the coordinates of the input variables, and the vertical axis is the membership function value (grade).
  • the coordinates are represented by (horizontal axis, vertical axis). In this embodiment, the coordinates are represented by 8 bits on both the horizontal and vertical axes.
  • FIGS. 7a and 7b show the PROM writer power when writing data representing the membership function as described above to the memory 46.
  • FIG. 7a shows the format of the address signal
  • FIG. 7b shows the data signal, respectively.
  • the upper three bits A12 to A14 represent the mode, and are set to 0 in the case of writing a membership function. .
  • the eight bits of ⁇ 4 to ⁇ ⁇ 1 represent the member number indicating the type of member function. 256 types of member functions can be set. These membership functions are represented by MFO, MF1, MF2, MF3, ..., MF255. According to the three bits of ⁇ 1 to ⁇ 3, eight inflection points The numbers F1 to F8 are represented.
  • the least significant bit AO is a discrimination bit indicating whether the coordinate is on the horizontal axis or the vertical axis, and is set to 0 for the horizontal axis and to 1 for the vertical axis.
  • Figures 8a to 8p show the address signals and data when writing one membership function (numbered MF0 and shown in Figure 6). An example of the data signal is shown. Since the address of the memory 46 is specified by the address signals A0 to A14, one address is stored in the 16-byte memory area of the memory 46. Sixteen bytes of data representing the member function of the data will be stored. Since the inflection points F7 and F8 do not exist in the membership function shown in Fig. 6, the data of these inflection points is 0 Ohh force. ⁇ It is set (see Fig. 8m to Fig. 8P).
  • the program power supply Vpp is set to H, and the chip enable signal CE is set to L. Then, the output enable signal 0E is set to H respectively.
  • the input / output control unit 41 converts the address input terminals AO to A1 to the given address signals (memory / address signals MA0 to MA14).
  • the data input / output terminals IZOO to 4 ⁇ 07 are input to the address of the memory 4 ⁇ specified by ⁇ ⁇ ⁇ ⁇ * ⁇ * ⁇ * 0 to MD 7)
  • the I / O buffer 42 is controlled so that is written.
  • the above signals V pp, CE and OE are also given to the memory 46, which writes the input data.
  • x0, x1, 2, ⁇ 3, etc. are input variables
  • yl, y2, etc. are output variables.
  • Stables 0 to 2 make up rule 1
  • sables 3 to 5 make up rule 2.
  • Each sample is represented by four bytes of code data (rule data D0 to D7), and these n-codes are used.
  • mark code (1 byte) input variable number code (1 byte)
  • output variable number code (1 byte) member -Ship function numbers are arranged in order of code (1 byte).
  • the mark code indicates the position of each subrule in the rule to which it belongs and the position in all the rules, and is set as follows. It is.
  • the input variable number code represents the number of the input variable.
  • the output variable number code indicates the number of the output variable.
  • Membership function number code is Represents a number.
  • Figures 9a and 9b show the fuzzy processor when rules and data are written to memory 46 by a PROM writer.
  • Fig. 9a shows the format of the signal given to 40
  • Fig. 9a shows the address signal
  • Fig. 9b shows the data signal (rule data). , Respectively.
  • the upper three bits A12 to AH of the address signal indicate the mode, and when writing the normal data, 0 1 Is set to. A10 and All are not used.
  • the subroutine number is represented by eight bits A2 to A9. 256 sub-rails can be set.
  • the lower two bits are control codes, and data DO to D7 are used.
  • the above “mark 'code, input variable number code, output variable number code and Indicates which of the membership function number codes is represented. That is,
  • the data signals D0 to D7 are the rune data, that is, the mark code, input variable number code, and output variable number described above. Code and Membership Function Number Indicates either code.
  • FIGS. 10a to 10f show examples of address signals and data signals when the above-mentioned tables 0 to 5 are stored in the memory 46. Yes.
  • Figures Ida to 10f represent subroutines 0 to 5, respectively.
  • FFh is set for the unused codes in the data signal.
  • the data DO to D7 at the third note in Fig. 10a represent the output variable number code, but the output variable does not exist at the sub-zero 0.
  • FIGS. 11a to 11d show the format of the pseudo address signal.
  • Fig. 11a shows a pseudo-ad used to query the operating state of the fuzzy processor 40 (status information: indicating whether or not the processor is operating). Indicates a less signal.
  • the most significant bit A14 is set to 1 (meaning read), and the second most significant bit A13 is set to 1 (meaning status). . Since the status information (1 bit) is stored in a predetermined storage location in the output register 45, A0 to A12 (OA0 to OA in FIG. 5) The bit (represented by 12) is used to specify the storage location in the output register 45 where the status information is stored. .
  • One bit of status information read from the output register 45 (the output data is represented by OD0 to OD7 in FIG. 5) is data.
  • the signals are output from the input / output terminals I 0 to IZO 7 and transferred to the host CPU 20.
  • the lib diagram is used to read output data from the fuzzy processor 40, and the top bit A 14 is 1 (meaning the read 2nd bit A13 force ⁇ 0 (meaning the data) is set respectively. Read by other bits 0 to 812 (0800 to 0812) The address of the output register 45 in which the output data is stored is specified. The output data (OD0 to OD7) output from the output register 45 is output from the data input / output terminal IZOOIZO? And is sent to the host CPU 20.
  • FIG. 11c is for giving a start command to the fuzzy processor 40, and the most significant bit A 14 force ⁇ 0 (means light ), And the second place bit AU force 1 (meaning start) is set respectively.
  • the other bits AO to A12 (IAO to IA4 and IDC! To ID7) are not required and are not normally used, such as all 0s or 1s. It is set in the bit.
  • the upper two bits A13 and A14 of the pseudo address signal input from the address input terminals A0 to A14 to the fuzzy processor 40 are Supplied to the start decoder.
  • the start decoder supplies a start signal to the processing control unit 4 in the case of these two bit cameras 01.
  • FIG. 11 shows a pseudo address signal used when writing input data to the fuzzy processor 40, and shows the most significant bits A1 and A0.
  • the second bit A13 is set to 0 (meaning data), and the second place bit A13 is set to 0 (meaning data).
  • the five bits A8 to A12 (represented by the input addresses IA0 to IA4 in FIG. 5) write the input data.
  • Input register that should be included Specify the address, and write the 8 bits A0 to A7 (represented by the input data ID0 to ID7 in Fig. 5) to the input register 44. Indicates input data to be included.
  • the address to which the input data is to be written for each input variable is preliminarily determined, and the input address data IA 0 ⁇ IA 4 indicates the address.
  • the output register 45 there is a predetermined address to which the output data representing the operation result for each output variable is to be written. ⁇ ⁇ ⁇ 0 ⁇ ⁇ ⁇ ⁇ indicates the address.
  • the input / output control unit 4 ⁇ uses these two bits. Depending on the state of the unit, the bus can be switched, and the writing or reading of data to the input and output registers 44 and 45 can be controlled. ⁇
  • the input / output control unit 41 when input data is written to the input register, the input / output control unit 41 is configured to output the chip enable signal CEIR and the light enable signal.
  • the signal WEIR is output and supplied to the input register 44.
  • the chip enable signal CEIR is supplied to the input register 44 via the OR circuit 49a.
  • the input / output control unit 41 When reading output data from the output register 45, the input / output control unit 41 outputs the chip and enable signals CEOR and outputs the data. ⁇ Bull signal OEOR is output and given to the output register in the evening.
  • the chip enable signal CEOR is input to the chip register 45 via the OR signal 49b.
  • the processing control unit 47 also controls writing and reading of data to and from the input register 44 and output register 45 and the memory 46 in the same manner. .
  • the processing control unit 47 When reading the input data from the input register 44, the processing control unit 47 outputs the chip enable signal CEIR and the output enable signal OEIR to the input register. Give to 44.
  • the data ID0 to ID7 read from the input register 44 are input to the arithmetic section 48 via the bus.
  • the processing control unit 47 includes the chip enable signal CEOR and the light input signal CEOR. It outputs the enable signal WEOR and supplies it to the output register 45.
  • the reading of the data from the memory 46 is performed in the same manner, and the data representing the read member functions and the rules are read. Is supplied to the operation unit 48 via the bus.
  • the processing control unit 47 buses the address to read out the data of the input register 44, the output register 45, and the memory 46, and the address to be written. There is no point in specifying it through.
  • FIG. 12 shows a control processing procedure of the fuzzy processor 40 by the host CPU 20.
  • the pseudo address signal created in accordance with the pseudo address signal format shown in Fig. 1 1d is displayed on the data bus. Is set (step 101). Subsequently, the host CPU 20 outputs a read instruction (step 102). That is, various signals are output so that the decoder 38 outputs the L-level chip enable signal CE2, and the H level is output. Outputs a read signal.
  • the L-level chip enable signal CE2 is input to the chip * enable terminal of the fuzzy processor 40.
  • the H level read signal is inverted by the NOT circuit ⁇ , and is input to the fuzzy processor 40 as an L level output enable signal. Further, the host CPU 20 sets the program power supply Vpp to the L level.
  • the pseudo address signal output on the address and noise by the above processing is input to the input terminals AO to A14 of the fuzzy processor 40.
  • the pseudo address signal is set in the storage location of the input register 44 specified by the address signals IAO to IA4 in the pseudo address signal.
  • the input data IDO to ID7 are stored. Since the instruction output from the host CPU 2Q is a read instruction, some data is transferred on the data bus and transferred to the host CPU 20. However, the host CPU 2G ignores the captured data (Step 1 ( ⁇ )).
  • the host CPU 20 sets a pseudo address signal including a start signal according to the format shown in FIG. 11c on the address bus.
  • a read instruction is output (steps 105 and 106).
  • Host CPU 20 then ignores the data captured through the data bus (step 107).
  • the start signal is decoded by the start decoder 43 in the fuzzy processor 40, and the start signal is processed and controlled.
  • the processing control unit of the fuzzy processor 40 performs a predetermined fuzzy processing operation according to a processing procedure described later.
  • the operation unit 48 is controlled as described above.
  • the output data obtained by the fuzzy processing operation is temporarily stored in the output register 45.
  • the host CPU 20 executes a pseudo addressing process according to the format shown in FIG. 11a. Create a signal, set it on the address bus, and output a read instruction (steps 108 and 109). This pseudo address signal is input to the fuzzy processor 40 through address input terminals AO to A14. After the start signal is input, the processing control unit outputs a busy signal when the arithmetic processing is being executed. A bit representing the state of this busy signal is stored in a predetermined memory location of the output register 45. All arithmetic processing When the processing is completed, the busy signal stops, and the bit representing the busy signal of the output register 45 is changed to a bit representing the processing stop.
  • the input / output control unit 41 responds to the input of the pseudo address signal including the bit stored in the output register 45.
  • a read signal that indicates a stop signal or a bit indicating the end of processing is output to the data bus via the output terminals IZOO to IZ07 via the input / output buffer 42.
  • the host CPU 20 reads a bit representing the status output from the fuzzy processor 40 onto the data bus and reads the bit. It is determined whether or not the inference processing in the processor 4Q has been completed (step 0).
  • the host CPU 20 executes the format processing shown in FIG. 1b.
  • a read instruction is output (step 111).
  • the input / output control unit of the fuzzy-port sensor 40 calculates the operation result stored in the output register 45.
  • the output data to be displayed is read out and output to the data bus via the data input / output terminals I / 00 to IZO7.
  • the host CPU 20 takes in this data.
  • FIGS. 13 to 15 show the procedure of fuzzy inference processing in the operation unit 48.
  • This processing procedure is performed according to the microcode stored in advance in the arithmetic unit 48.
  • the arithmetic unit 48 is used to simplify the explanation.
  • the software processing represented by the microcode is to be performed, the arithmetic unit 48 must be connected to the hardware. It should be noted that it is also possible to implement the processing equivalent to the processing shown in FIG. U to FIG. Absent .
  • the ⁇ I ⁇ arithmetic circuit, the MAX arithmetic circuit, the adaptive value arithmetic circuit, the weight, the function circuit, and the like are dependent on the mark code. ⁇ will be controlled
  • Fig. 13 first, the rule is set and the RC power is initialized (step 12 1). As described above, one subroutine stored in the memory 46 is composed of four bytes. The rune counter R C is used to count the number of bytes in a single rule.
  • the table stored in the memory 46 is read out one byte at a time under the control of the processing control section 47 and transferred to the operation section 48. It is judged whether or not the contents of the rule / counter RC are strong (Step 1 22). If the content of RC is 0, it was read from memory 46 One byte of solenoid data representing a sub-rule is data representing a mark code, and this mark code data is stored in the memory. Data is temporarily stored in the register RA (steps 123 and 124). O The rule counter RC is subsequently incremented. (Step 125) o
  • the captured rule data for one byte is data representing the input variable number code. It is determined whether the mode is FFh (Steps 1, 127, 128). If the input variable number code is not FFh, the input data of the input variable specified by that code is read out from the input storage area 44, and the ⁇ It is stored in a predetermined storage location in the area (Step UQ). After this, or if the input variable number code is FFh, the rule counter RC is incremented and proceeds to the next step ( Step 129).
  • the mark code captured in the register RA determines whether the processing of the antecedent part or the processing of the consequent part is performed (step 1 3 8) 0 Mark code becomes D0 force 1 and until D1 force 1 is the antecedent processing, and mark code
  • the processing of the consequent part is between the time when the D2 force in the middle becomes 1 and the time when the D3 force becomes 1 in the middle.
  • the member ship function read out in step 1337 is a member ship function relating to the input variable of the antecedent part. Therefore, the input data stored in the predetermined storage location of the work area in step 13Q is first processed for this membership function.
  • the conforming value is calculated (step 1339).
  • D1 in the mark code that is captured in the mark code register RA It is determined whether or not the processing of the antecedent part has been completed. Step 14 ⁇ ). In the case of D1 0, since the antecedent processing has not been completed yet, the process returns to step 121. If D 1 is 1, it means that the processing of the antecedent part of one rule has been completed, so that all the operations included in the antecedent part calculated in step 139 The MIN operation of the compatible value in the table is performed, and then the process returns to step 121 (step 141).
  • step H2 If it is determined in step 138 that the consequent part is to be processed, the consequent part processing is performed in FIG. 15 (step H2).
  • the member function of the consequent part is cut (transformed) based on the MIN operation result calculated in step 141. .
  • the data representing the membership functions and rules to the memory 46 are written by the PROM writer. However, it can be written by the host CPU 20. In this case, the format of the pseudo address signal for writing data shown in Figs. 11c and lid would be as shown in Fig. 16, for example. It will be.
  • the most significant bit AH is set to 0, indicating that writing is to be performed.
  • Fig. 11d Represents the start or data in the same way as the A13 bit in the table.
  • the address of the memory MA0 to MA5 is specified by the 6 bits of A6 to ⁇ 1 ⁇ , and the addresses of A0 to A5 are specified.
  • the bits (MD0 to MD5) representing the normal or member function to be written to the memory 46 by the bit are expressed. .
  • the memory 46 will be a writable / readable memory such as a RAM.
  • the address data of A6 to A11 becomes unnecessary. Therefore, in this case, 12 bits can be used as data representing a rule or a membership function.
  • the upper three bits A12 to A14 of the address input in FIG. 5 are connected to the I / O controller 41 and the start decoder 43. I will be given.
  • a fuzzy processor is shown as a processor compatible with PR0M, but the type of processor is fuzzy. Needless to say, it is not limited to a processor. For example, a processor that performs a specific arithmetic process other than fuzzy processing can be made PROM compatible.
  • a 28-pin PR0M force (the force shown, a PROM with a pin, etc.) is compatible with other types of PROMs. There is no better way to realize a processor. These are the same as the other embodiments described below.
  • FIGS. 1 to 4 and the description referred to in the description of the first embodiment are also applied to the second embodiment as they are.
  • the PR0M compatible fuzzy processor in the second embodiment will be specifically indicated by reference numeral 24Q.
  • the fuzzy processor 240 in place of the RPOM, is also replaced with the PROM socket. Power.
  • the fuzzy processor 240 is connected to the host CPU 20 in exactly the same way as the PROM. Then, as described in detail later, the host CPU 2Q associates the fuzzy processor 240 in the same manner as the access to the PROM. Access and read instructions (without using light instructions), the knowledge data (members) to the fuzzy processor 240. Data representing a ship function and data representing a fuzzy relay), writing of input data, and reading of output data Do And can be done.
  • writing knowledge data and input data to the fuzzy processor 240 transfer the knowledge data and input data that should be written. This is performed using the Les buses A1 to A15. Reading data from the processor 240 is performed in the same manner as reading data from the PROM.
  • FIG. 17 shows an example of the configuration of the fuzzy processor 240. And have you in view of this, the power supply V c (;, the terminal of the ground V ss your good beauty profile gram power supply V pp is that has been shown is omitted.
  • the fuzzy processor 240 includes a control unit 241, an input buffer 242, an output buffer 243, an input register 244, an output register 245, and a loop. It has a memory device 2, a membership function memory device 247, an operation unit 248, and an internal bus.
  • the control unit 241 outputs a chip enable signal from the host CPU 20 to the chip enable terminal CE, and an output from the host CPU 20 to the output enable terminal OE.
  • the upper 5 bits A10 to A14 of the kine signal and the pseudo address signal to be described later are manually input, and the input register 244 and the output register 245 are used.
  • Rule memory device 246 and member function memory device 247 various control signals for reading and writing, and arithmetic unit 248. Outputs a control signal for.
  • Input buffer 2 is address input from host CPU 20. The control of the direction of the pseudo address signal supplied to the input terminals A0 to A14 and the switching to the internal bus are performed.
  • the output buffer 243 transfers output data input through the internal bus to the data input / output terminals IZO0 to I07.
  • the input register 244 stores input data relating to an input variable given from the host CPU 20.
  • the output register 245 stores output data representing the operation result.
  • the output register 245 also stores 1-bit status data (busy signal).
  • the rule and memory device 246 stores data representing a fuzzy * norle given from the host CPU 2Q. Membership function
  • the memory device 247 stores data representing the membership function given from the host CPU 20.
  • RAM for example, SRAM or electrically rewritable ROM (EEPROM)
  • EEPROM electrically rewritable ROM
  • Control of the fuzzy processor 240 by the host CPU 20 and writing of knowledge data and input data to the fuzzy 'processor 240 (write The reading (reading) of knowledge data, status information, and output data from the fuzzy processor 240 is all performed by address signals. This is performed using AO to A14. The address signal used for these operations is also called a pseudo address signal. The data to be read is output through the data bus.
  • the format of the pseudo address signal supplied to the address input terminals AO to A14 is shown in FIG. 19 and FIG.
  • the pseudo address signal is such that the upper bit is mainly used as a control code and the lower bit is used as an address. Or various data.
  • A14 represents a data read (read) or data write (light).
  • a 1 1, that is, the case of the lead will be described with reference to FIG.
  • the read means that the host CPU 20 reads various data from the input / output registers 244, 24 ° or the memory devices 246, 247. This is a read This is done when necessary.
  • A indicates that what should be read is status information or various data.
  • the data information is stored in a predetermined storage location in the output register 245.
  • the lower eight bits A0 to A7 (OA0 to OA7) specify the storage location in the output register 245.
  • A8 to A12 bit data can be anything (NO CARE) o
  • the data to be read includes knowledge data and input / output data.
  • knowledge data There are two types of knowledge data: runeol data and member function data.
  • Input / output data includes input data and output data.
  • knowledge data is sequentially and sequentially read from the internal memory device 246 or 247 from the first address, no address data is required. It is. That is, A0 to A7 are N0 CARE.
  • A8 and A9 are specified by the lower address specified later. For this reason, A10 is used for address counter reset. This may not be necessary depending on the configuration of the processing control unit 252 described later.
  • AO to A10 are NO CARE.
  • Input data is read from input register 244. It is specified by the input power AO to A3 (IA0 to IA3) of the input register 244 where the data to be read is stored.
  • A4 to A10 are NO CARE.
  • Output data is read from output register 245. The address of the output register in which the data to be read is stored is specified by AO to A7 (0A0 to 0A7).
  • A8 to A10 are NO CARE.
  • the light means that the host CPU 20 writes various data to the input register 244 or the memory devices 246, 24 ?. This is typically done prior to operating the fuzzy processor 240.
  • the second place bit A13 indicates whether the light should be related to the input item or the knowledge.
  • a 13-1 is the input item, and
  • a 13 0 is the knowledge.
  • Input items include start instructions and input data.
  • ⁇ ⁇ 1 force ⁇ Indicates a start command.
  • the start directive instructs the start of the fuzzy inference process for the fuzzy processor 240. It is shown. In this case, A0 to A11 are NOCARE.
  • the input of data is to write data to input register 2, and A8 to A11 (IA0 to A11)
  • the data to be written is represented by the lower bits A0 to A7 (ID0 to ID7).
  • the setting of knowledge includes setting of rules and setting of membership functions.
  • the rule is written to the rule memory device 246.
  • the rule memory device 246 includes an address counter, and the address counter is used to store the address counter.
  • the rule and the address of the memory device 246 are designated according to the count value.
  • AO to A9 are NO CARE.
  • AO to A9 represent run-out data (RD0 to RD7) and control codes. This rule 'data and control' code is described later.
  • Membership functions are membership functions. Written to location 247. This memory device 247 also includes an address counter.
  • A11 A10 11 instructs that all areas of the internal memory devices 246 and 247 should be erased.
  • FIG. 20 shows a configuration example of the control unit 241.
  • the control unit 241 includes an input / output control unit 251, a processing control unit 252, a memory write control unit, a start signal generation circuit 254, a NOR circuit 255 to 258, and an OR circuit ⁇ 9 It is composed of
  • the input / output control unit 251 controls the writing of input data to the input register 244 and the reading of output data from the output register 245.
  • a 0 to A 7 (ID 0 to ID 7) given to the address input terminal are stored in the memory location of the input register 244 specified by (IA 0 to IA 3).
  • the input data represented by 7) will be written.
  • the input / output control unit 251 When a control code is applied to the address input terminal (see Fig. ⁇ ), the input / output control unit 251 outputs the output register / chip / select signal CEOR1. Outputs the output register read signal OEOR (also L level).
  • the signal CEOR 1 passes through a NOR circuit 256 to become an output register evening / chip select signal CEOR, and the signal OEOR is directly applied to the output register 245, respectively. It is.
  • the memory write control unit 3 writes the knowledge data to the rule memory device 246 and the memory device 2 and the one-ship function memory device 2 when the host CPU 20 writes the knowledge data. This outputs a signal for controlling these memory devices 246 and 247.
  • the pseudo-ad dresses to be input are set.
  • the upper three bits A14A13A12 of the signal are 01.
  • the memory write control unit 253 When the level is 0 L, the memory write control unit 253 outputs a rule memory chip select signal CERM 2 and a knowledge memory write signal WEM. (Both L level).
  • the signal CERM 2 is passed through the NOR circuit 257 (as CERM), and the signal WEM is directly supplied to the rule memory device 246 respectively. If the pseudo address signal is 2 bits A11A10 and the output is 0, the reset signal RESET2 is output. Therefore, this signal RESET2 is an OR circuit. After passing through 259, the reset signal RES is provided to the rule memory device 246 as a reset signal RES. The address / counter included in this will be reset.
  • the upper 3 bits of the pseudo address signal to be input (13) are 00.
  • the control code is input and the chip enable signal CE is high and the output enable signal 0E is low, the memory is written.
  • the control unit 253 outputs a member function, memory chip, a select signal CEMM2, and a knowledge memory light signal WEM.
  • the signal CEMM 2 passes through a NOR circuit 258 (as CEMM), and the signal WEM is directly supplied to a member function memory device 247. It is. If the two bits A11A10 of the pseudo address signal are 0, the reset signal RESET2 is output. Therefore, this signal RESET2 is ORed.
  • the reset signal RES is supplied to the membership function memory device 246 via the circuit 259 as a reset signal RES, and the address count signal included in the memory 246 is included in the reset function RES. Power ⁇ reset.
  • a 11 A 10 force ⁇ 10 Outputs the two bits A8A9 in the pseudo address signal and provides the same to the memory device 246 with the function ⁇ one-ship function.
  • the main functions represented by AO to A7 included in the pseudo address signal are described.
  • the function data MD0 to MD7 are sequentially written to successive addresses of the member function memory device 247. .
  • the processing control unit 252 mainly controls the access of the input register 244, the output register 245, and the memory devices 246 and 247 in the execution of the fuzzy inference processing. It is a thing.
  • Rule memory device 246 Reads normal data from member memory or Membership function Reads memory function data from memory device 2
  • the processing control unit 252 includes the rule memory chip select signal CERM 1 or the main chip function memory 'chip' select. It outputs the signal CEMM 1 and the knowledge memory read signal OE (all at L level).
  • the signal CERM 1 or CEMM 1 is routed through a NOR circuit 257 or 258 to a run-through / memory / chip-select signal CERM or a main ship function. Mori chip 'select signal
  • the CEMM is provided to the rule memory device ⁇ 6 or the member function memory device 247, and the signal 0E is directly sent to these memory devices. 246, 247.
  • the processing control unit 252 Since the set signal RESET 1 is output, the reset signal RESET 1 is output as the reset signal RES via the OR circuit 255 to the memory device 246 or 247. Given to This resets the address / counter power in the memory device 246 or 2. Subsequently, the processing control unit 252 outputs an address signal A9A8 which changes to 0, 01, 10 and 11 for each reading of data, data, and data. , Memory device 246 or 247. As a result, rule data or member ship function data is read from the memory device 246 or 2 one byte at a time. Become .
  • the processing control unit 252 is also the same as described above when it is instructed to read data from the host CPU 2Q and the memory device 246 or 247. The same operation is performed. Referring to FIG. 18, this command is represented by the upper four bits A14 to All of the pseudo address signal. A 14 A 1 3 A 12 When A11 is 101, the readout of the rule data is performed, and the rule data is read out. When the value is 0, the membership function data is read out from the memory function device 247, and the main function data.
  • the chip enable signal CE is at the L level, and the output enable signal ⁇ E is also at the L level.
  • the processing control section 252 outputs the input register chip select signal CEIR (CEIR 2) and the input register * read signal OE, and Outputs an address signal indicating the memory location to be read.
  • the processing control unit 252 When writing the inference result (output data) obtained by the arithmetic operation in the arithmetic unit 248 to the output register 245, the processing control unit 252 includes the output register 252. 'Chip select signal CEOR (CEOR 2) and output register * Outputs the write signal WE and the output register to be written. Outputs an address signal specifying the memory location in the 245.
  • the processing control unit 252 outputs an input register evening / chip / select signal CEIR (CEIR 2) and a read signal OE of the input register.
  • CEIR chip / select signal
  • OE read signal
  • the main ship function is defined by giving the coordinates of a plurality of inflection points, and the adjacent variable It has a shape obtained by connecting curved points with straight lines.
  • the horizontal axis is the coordinates of the input variables, and the vertical axis is the membership function value (grade).
  • the coordinates are represented by (horizontal axis, vertical axis). Also in this embodiment, the coordinates are represented by 8 bits on the horizontal axis and the vertical axis.
  • the number of inflection points representing the membership function is set to four.
  • the membership function shown in Fig. 21 is trapezoidal and is defined by four inflection points F1 to F4.
  • the membership function shown in Fig. 22 can be specified by three inflection points, such as a force that is a triangular shape, and the second and third inflection points. It is assumed that the inflection points F2 and F3 are just common, and are represented by the four inflection points F1 to F4. .
  • the grades of the first and fourth inflection points F 1 and F 4 are always 0 (data is OOh; h indicates that it is a hexadecimal number).
  • We also promise that the grade of the second and third inflection points F2 and F4 is always 1 (data is FFh).
  • FIG. 23 shows a part of the contents of the memory in the member function memory device 247.
  • Four memory areas are prepared for one main class function, and the inflection points Fl and Fl are assigned to these memory areas in the order of addresses.
  • the horizontal axis coordinate data MD0 to MD7 of F2, F3 and F4 are stored.
  • the main ship functions have a main ship number. These member function numbers are MFO, MF1, MF2, ....
  • the memory in the memory device 247 is arranged in the order of the address in the order of the smallest function of the member function number and the address. Is memorized.
  • the main function number is represented by the upper 8 bits MA2 to MA9 of the address. In this embodiment, it is possible to set 256 kinds of main ship functions.
  • each subroutine is represented by 4 knots of code data (lele-> evening). These code days are the mark code, input variable number code, output variable number code, and main ship function number code. 8 bits each
  • the mark code indicates the position of each subrule in the rule to which it belongs and the position in all rules. As with the mark code, it is set as follows:
  • the input variable number code indicates the number of the input variable.
  • the output variable number code indicates the number of the output variable.
  • the member function number code indicates the member function number.
  • FIG. 24 shows a part of the contents of the memory in the rule memory device 246.
  • Four storage areas are prepared for one subroutine. Mark code and input variable number code are assigned to these storage areas in order of address. The code, output variable number code and member function code are stored. The subrules are assigned subrule numbers 0, 1, 2, ....
  • the memory in the rule memory device 246 is stored in the memory in the order of address, starting with the lowest power of the table number.
  • the address of the memory in the rule memory device 2.46 is also represented by 10-bit data RA0 to RA9.
  • RAO and RA1 represent the codes described above. That is,
  • the upper eight bits R A2 to R A9 of the address indicate the number of the table. In this embodiment, 256 types of tables can be set.
  • FFh is set for those that are not used in each code representing a table.
  • FIG. 25 shows an example of the configuration of the rule memory device 246.
  • the memory memory device 246 is located above the memory 246A such as RAM and EEPROM, and the address of the memory 246A. It consists of an address counter 261 and a quaternary counter 262 for designating the eight-bit position.
  • Address counter 261 and quaternary counter 262 are reset by reset signal RES.
  • a relay, memory, chip, and select signal CERM will be given.
  • This signal CERM repeats the inversion between the H level and the L level for each 1-kbyte transfer.
  • an output is generated from the quaternary counter 262, which is output to the address / power counter 261 as a clock signal.
  • the count value of the address * counter 261 is incremented.
  • the end signal A 9 A 8 changes from 0 to 01, from 0 to 10 to 10, from 10 to 11 or from 1 to 0 for each 1-byte transfer. Changes to 0.
  • This address signal A9A8 specifies the lower 2 bits of the address of memory 246A.
  • the address signals RA0 to RA9 of the memory 246A are sequentially input one by one for each one-byte transfer after the reset signal RES is input. As the data is incremented, its storage locations are specified in order from address 0 0 0 0 0 0 0 0 0 0 0 0 0 to address.
  • This operation is performed by the host CPU 20 writing run-time data, reading the normal data by the host CPU 20, and by the control unit 2. The same applies to both rules and data readout for performing fuzzy inference. Yes o
  • the write data is written from the memory write control unit 253 to the memory module 246A when the host CPU 20 writes the data to the memory 246A.
  • Two-bit A8A9 and reset signals in the memory chip select signal CERM, knowledge memory light signal WEM, and pseudo address signal RES is output.
  • Memory by host CPU 20 246 A memory by processing control unit 252 for reading runo data and executing fuzzy inference
  • the processing control unit 252 reads the rule memory, chip select signal CERM, and knowledge memory. Read signal 0E, address signal A8A9, and reset signal RES are output.
  • FIG. 26 shows an example of the configuration of the member function memory device 2.
  • Membership function Memory device 21 is a memory such as RAM, EEPROM, etc. 2A, address * Counter 271, quaternary counter ⁇ 2, quaternary It consists of a power counter 273 and a multiplexer 274.
  • the manoplexer # 4 reads and writes data to and from the memory 247A of the member function by the host CPU 20 overnight. Disconnects reading of membership function data from memory 247A during execution of fuzzy inference. It is a replacement.
  • the busy signal BUSY When writing and reading the main function data by the host CPU 20, that is, the busy signal BUSY is not output.
  • the multilevel Selector 4 selects input address signals AMA 9 to AMA 0 and outputs them to memory 24 as address signals MA 9 to! Provided as VI A 0.
  • the address signals AM A9 to AM A0 are generated by an address counter # 1 and a quaternary counter 272. The operation is the same as the operation of the address counter 261 and the quaternary counter 262 in the rule memory device 246 shown in FIG.
  • the reading of the membership function data is performed according to the rules set in the rule memory device. Is done. That is, when the membership function number code (data RD7 to RD0) is read from the rule memory device 246, this data is read. Input to the multiplexer 274 via the bus, and given as address signals BMA 9 to BMA 2
  • the quaternary counter 2 ⁇ has been reset by the reset signal RES at the start of the execution of the fuzzy inference, and thereafter, the main counter has been reset.
  • One-Ship Function Memory Chip ' The select signal is incremented for each CEMM, and the 2-bit output repeats 0, 0, 1, 10, and 11.
  • the output of the quaternary counter 273 is provided to the multiplexer 27 as input address signals BMA 1 and BMA 0.
  • the busy signal BUSY is at the H level.
  • the multiplexer 274 is an input address when the busy signal BUSY is at the H level and the memory read signal from the processing control unit 252 is at the 0E power L level. Select the signals BMA0 to BMA9 and give them to the memory 2A as the address signals MA0 to MA9.
  • the membership type specified by the membership function number code read from the rule's memory device 246.
  • Four-byte data representing the function is read out from the memory 247A, and supplied to the arithmetic unit 248 via the data bus.
  • FIG. 27 shows the rule memory device 246 and the main ship function memory of the fuzzy processor 24Q by the host CPU 20. A processing procedure for writing rule data and member ship function data to the device 247 is shown.
  • the rule data RD0 to RD7 are generated in the order in which the data is written to the memory device 246.
  • These runo data ⁇ Let A0 to A7 be the control codes A8 to AH for writing the rule data created by using the format shown in Fig. 19.
  • a pseudo address signal for writing rule data is created.
  • the pseudo address signal representing this data is written to the membership function memory device 247. They are created in the proper order.
  • a pseudo address signal including a control code indicating an address counter reset is provided at the beginning of the series of pseudo address signals, and an E address is provided at the end.
  • Each pseudo address signal including a control code indicating a command is set.
  • a pseudo-address signal including the created address counter reset control code is set on the data bus.
  • the host CPU 20 outputs a read instruction. That is, various signals are output so that the L-level chip enable signal CE2 is output from the decoder 38, and the H level is output. Output the read signal.
  • the L-level chip enable signal CE2 is the chip enable pin of the free processor 24 ⁇ .
  • the ⁇ level read signal is inverted by the ⁇ 0 39 circuit 39 and is output to the fuzzy processor 240 as the L level output enable signal ⁇ ⁇ . input .
  • the pseudo address signal output on the address bus by the above processing is applied to the input terminal of the fuzzy processor 24 ⁇ . Input to the memory A0 to A14, and the address signal A1 (! To A #) of the pseudo address signal is given to the memory write control unit 253. In accordance with the operation of the rewrite control unit 253, the reset signal RES is output, and the address counter 261 and quaternary of the rule memory device 246 are output. Power counter 262 The power is reset.
  • the host CPU 2Q sets the first pseudo address signal including the created rule data on the data bus ( Then, a read instruction is output (step 301) (step 302). Since the pseudo address signal is given to the memory write control unit 253, the first rule is output according to the operation of the memory write control unit 253.
  • Note data RD0 to RD7 (A0 to A7) are the first address of memory 2A in rule memory device 246 0 0 0 0 0 0 0 0 0 0 0 0 0 Is written to Since the instruction output from the host CPU 20 is a read 'instruction', some data is transferred on the data bus and transferred to the host CPU 2G. However, the host CPU 2Q ignores the captured data (step 103).
  • Step 304 When writing of all rule data is completed (the pseudo address signal including the end control code is output last). (Step 304), and in the same manner, the member function data is stored in the memory in the member function memory device 2 in the same manner. At 247 A, the data is sequentially written from address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (steps 305 to 308).
  • Figure 28 shows the memory write control unit 253 that controls the writing of the rule's data and the membership function data into the memories 246A and 247A. The processing procedure of the memory devices 246 and 247 is shown.
  • the upper bits A1 (! To A14) in the pseudo address signal to be input are used to write the rule data or to execute the member ship function. It is determined whether writing is to be performed (step 311).
  • the reset signal RES is output from the memory write control unit 253, so that the address.
  • the quaternary counter 262 is reset (steps 312 and 313).
  • the address 261 is output to the address RA2 to RA9, and the output of the memory write control unit is output to the address RAO, RA1 (A 8, A 9)
  • the output address specifies the start address of the memory 246 A by the output (steps 314 and 315), and furthermore, the signal CERM and the signal CERM. Since WEM is output from the memory control unit 3 (step 316), the pseudo address is output.
  • the data of the memory 246A is represented by the lower bits A0A7 in the signal and passed through the data * in the fuzzy processor 240. Rule data given to the data input terminal is written to the storage area specified by the address (step 317).
  • step 318 the quaternary counter power is incremented by the signal CERM (in step 318), and the process returns to step 314.
  • the output address of the address counter 261 does not change, but the addresses RA0 and RA1 change depending on the change of the bits A8A9.
  • the next address is specified, and the next rule data is written to the next storage area of memory 246A (step 314).
  • One write is written to memory 246A by writing the 8-bit knowledge data four times.
  • the data is written to all the memory and data memory 246A sent from the host CPU 20. This will be.
  • the writing of the membership function data is performed in exactly the same manner (steps ⁇ 2 ⁇ to ⁇ 3 ⁇ ).
  • the multiplexer 274 is switched to select an address signal including the output address of the address counter 271.
  • FIG. 29 shows a control processing procedure for causing the host CPU 20 force fuzzy and the processor 240 to perform a predetermined fuzzy inference calculation processing. This processing is almost the same as the processing in the first embodiment shown in FIG. It is assumed that the normal and member functions have already been written to the memory devices 246 and 247.
  • the input data is written to the input register 244.
  • input data ID0 to ID7 are assigned to lower bits A0 to A7, and addresses IA0 to IA3 are assigned to middle bits.
  • the address signal is set on the data bus (step 341).
  • the host CPU 20 outputs a read instruction (step 342). That is, various signals are output so that the L-level chip enable signal CE 2 is output from the decoder 38, and the H level is output.
  • the L level chip enable signal CE2 is input to the chip enable terminal CE of the fuzzy processor 240.
  • the H level read signal is inverted by the NOT circuit 39, and is output to the fuzzy processor 24Q as the L level output enable signal. input .
  • the pseudo address signal output on the address bus by the above processing is input to the input terminals A0 to A14 of the phage and processor 240.
  • Data ID 0 to ID 7 are stored.
  • the instruction output from the host CPU 2Q is a read instruction, and any data is transferred on the data bus and taken into the host CPU 2G. However, the host CPU 2G ignores the captured data (step 343).
  • the input data relating to all input variables used in the fuzzy processor 240 is obtained.
  • the data is stored in the input register 244 of the fuzzy * mouth sensor 240 (step 344).
  • the host CPU 2Q sets a pseudo address signal including a start signal according to the format shown in FIG. 19 on the address bus. And also outputs a read instruction (Steps 345, 346). Then, the host CPU 20 ignores the data captured through the data bus (step 3). As a result, the start signal is decoded by the start signal generation circuit 254 in the fuzzy processor 240, and the start signal START is processed. It is given to Gobu 252.
  • the processing control section 252 of the fuzzy processor 240 outputs various control signals in accordance with the processing procedure described later, and also outputs the various control signals.
  • the arithmetic unit 248 is controlled to perform a predetermined fuzzy processing operation. The output data obtained by the fuzzy processing operation is temporarily stored in the output register 245.
  • the host CPU 20 In order to read the status of the fuzzy processor 240, the host CPU 20 follows the format shown in FIG. 18 to read the status of the fuzzy processor 240. Creates a pseudo-address signal containing a read control code, sets it on the address bus, and outputs a read instruction (state). Pp. 348, 349). This pseudo address signal is input to the fuzzy processor 240 through the address input terminals A0 to A14.
  • the processing control unit 252 After the start signal is input, the processing control unit 252 outputs a busy signal BUSY when the arithmetic processing is being executed, and outputs the busy signal BUSY to a predetermined signal of the output register 245. It is stored in a storage location. When all arithmetic processing is completed, the busy signal B and SY stop, and the busy signal of the output register 245 is output. The bit representing the signal is changed to a bit representing the processing stop.
  • the input / output control unit 251 stores the video stored in the output register 245. Reads out a jig signal or a bit indicating the end of processing and outputs it to the data bus via output buffers 243 through output terminals 100 to 107. Control.
  • the host CPU 20 reads a bit representing the status output from the fuzzy processor 240 onto the data bus, and reads the bit. It is determined whether or not the inference processing in the G-processor 240 has been completed (step 35Q).
  • the host CPU 2Q stores the data in the output register 245.
  • a dress signal is output and a read command is output (step 351).
  • the input / output control section 251 of the fuzzy processor 240 stores the performance stored in the output register 245.
  • the output data representing the calculation result is read out and output to the data bus through the data input / output terminals IZ00 to IZO7.
  • the host CPU 20 takes in this data.
  • FIGS. 30 to 32 show the procedure of the fuzzy inference processing in the arithmetic unit 248.
  • This processing procedure is performed in accordance with the microcode stored in the arithmetic unit 248 in advance.
  • the arithmetic unit 248 performs software processing represented by a microphone code. It is also possible to configure the arithmetic unit 248 with hardware and realize the same processing as shown in FIGS. 30 to 32 with hardware. There is no end to what you can do. In such a nodeware configuration, the MIN operation circuit, the MAX operation circuit, the adaptive value operation circuit, the center-of-gravity operation circuit, and the like are controlled by a mark code. Will be.
  • the processing shown in FIGS. 30 to 5 is basically the same as the procedure of the fuzzy inference processing in the first embodiment shown in FIGS. 13 to 15.
  • the runner's counter RC force is first initialized (step 3).
  • one subroutine stored in the rule memory device 246 is constituted by four bits.
  • the rule 'counter RC' is used to count the number of bytes in a single subrule.
  • the rules stored in the rule memory device 246 are read out one byte at a time under the control of the processing control unit 252 and transferred to the operation unit 248. .
  • the reading of the reference data from 246 is performed sequentially from address 0 0 0 0 0 0 0 0 0 0. It is determined whether the content of the rule counter R C is 0 or not (Step 2). If the content of the counter * counter RC is 0, the rule memory device 246 outputs the 1 byte worth of the subroutine read out.
  • the data is the mark code, and the mark code data is taken in and the data is stored in the register RA. It is temporarily stored (Step 3, 374). Then, the rule counter R C force is incremented (step 2).
  • the captured data for one byte of rule 'data represents the input variable number code. Then, it is determined whether or not the code force is FFh (steps # 6, 377, 378). If the input variable number code is not FFh, the input data of the input variable specified by that code is read from the input registry. And stored in a predetermined storage location in the work area (step). After this, or in the case of input variable number code power FFh, the rule * counter RC is incremented and the next step is performed. Step Go to (Step (9).
  • the one-knowledge subroutine data taken from the rule memory device 246 is obtained. Since ⁇ represents the output variable number code, it is determined whether or not the force is FFFFh (381, 382, 383). If the output variable number code is not FFh, the data representing the output variable number code is temporarily stored in the register RB (step 385). ). Thereafter, or if the output variable number code is FFh, the rule counter RC is incremented and the process proceeds to the next step (step 384).
  • the one-byte subroutine data taken from the note memory device 246 is stored in the memory.
  • This is the data representing the non-ship function number code (step # 6).
  • Membership function number The data representing the membership function of the number represented by the code is read from the membership function memory 247. (Step 3).
  • the multiplexer 274 is connected to the data RD0 to RD7 read from the rule * memory device 246. The switch is made to select the address represented by the.
  • the mark code captured in the register RA determines whether the processing of the antecedent part or the processing of the consequent part is performed. (Step 388) o
  • the RDO in the mark code becomes 1 and the RD1 until it becomes 1 is the antecedent processing.
  • the processing of the consequent part between the time when RD 2 becomes 1 and the time when RD 3 becomes 1 during loading is performed.
  • the main function read out in step 387 is a member-ship function related to the input variable of the antecedent part. Therefore, the adaptation of the input data stored in the predetermined storage location of the work area in step 380 to this membership function is first performed. The value is computed (step 389).
  • Mark code 'RD1 in the mark code captured in the register RA The antecedent of one rule depending on 0 or 1 in the mark code It is determined whether or not the processing of the set has been completed (step 390). In the case of 101, the processing of the antecedent part has not been finished yet, and the process returns to step 371. In the case of RD 1 power ⁇ 1, the processing of the antecedent part of one node has been completed, so it is included in the antecedent part calculated in step 389. The MIN operation of the conforming value in all the tables is performed, and then the process returns to step 3 (step 391).
  • the processing in the input / output control unit 251, the processing control unit 252, and the memory write control unit 253 is also performed by using a microcode.
  • each of these control units 251 to 253 may be configured by a dedicated hard disk drive circuit.
  • the host CPU uses the pseudo address signal and the read instruction to have the right enable terminal. No data is being written to the PR0M connector or ° table processor.
  • the third embodiment relates to a configuration in which data can be written to a host CPU-powered PROM compatible processor using a write instruction. It is a thing.
  • FIG. 33 shows a case where the PFU 32 is replaced with the PFU socket of the fuzzy processor 440 according to the third embodiment of the present invention.
  • This is a view of the configured system and system, and corresponds to Fig. 4.
  • the same components as those shown in FIG. 4 are denoted by the same reference numerals.
  • FIG. 2 and FIG. 3 and the description thereof also apply to the third embodiment.
  • PROMs 31 to 34 do not have a light enable terminal. Therefore, generally, the host CPU 20 cannot write data to the PROMs 31 to 34. Data writing to the PR ⁇ M 31 ⁇ 34 is, In general, the profile gram power supply V pp that Re I a by Ri line to the PROM La Lee else have use the.
  • Host CPU 20 power ⁇ When writing data to another device (for example, RAM) connected to the host CPU 20, an L level read is required. Outputs the light signal RZW. This L level read light signal is output from other equipment. Supplied to the light enable terminal. Host CPU
  • the fuzzy processor ⁇ 440 mounted in place of PROM 32 is connected to host CPU 20 in exactly the same way as PROM. Then, as will be described later in detail, the host CPU 20 executes the fuji-pump by the read instruction in the same manner as reading the data from the PROM.
  • the data can be read from the processor "0", and the write instruction can be used in the same way as the data write to other devices described above. It is possible to write data to the processor 440.
  • Light instructions output from the host CPU 20 (light enable Signal that is not input to the fuse-box sensor 440 (the light-gap sensor 440 is also light-equivalent to the PROM).
  • the fuzzy processor 440 is specified so that it will be clear from the details that will be described later. That internal La wells Yi Ne one bull signal of Chi-up 'Lee Ne one pull signal C E 2 in full ⁇ di I-profile cell to have based Tsu support 44 Q is Ru is created.
  • FIG. 34 shows an example of the configuration of a fuzzy processor 440. ing .
  • the power supply V cc and ground V ss terminals are not shown.
  • the fuzzy processor 440 includes a write Z read control unit 441, an input / output buffer 442, a start decoder 443, an input register 4, It has an output register 445, a membership function rule memory 446, a processing control unit 447, a calculation unit 448, and an internal bus.
  • Address signals input to and output from the input / output buffer 442 are represented by AO to A14, and data signals are represented by DO to D7.
  • the address signals input to the decoder 7 of the start decoder 443 and the write Z read controller 441 are 441 to ⁇ 14.
  • the address signals supplied to the input register 444 and the output register 445 and the memory 446 are IAO to IAll, OAO to OA11 and ⁇ ⁇ ⁇ , respectively. ⁇ ⁇ ⁇ 11, which correspond to AO to All.
  • Data signals input to and output from the input register 444, output register 445, and memory 446 are ID0 to ID7, OD0 to OD7, respectively. They are represented by MDO to MD7, which correspond to DO to D7.
  • the I / O buffer 442 is an address signal and data input / output terminals that are input from the PR0M writer power to the address input terminals A0 to ⁇ . Control of the direction of the data and evening signals input to IZOO to ⁇ ⁇ 07, switching to the internal bus, host CPU 2Q power, control of the direction of the address signal given to the address input terminals A0 to A14, switching to the internal bus, input register The control of the direction of the input data given to the I / O terminals I / 00 to IZO7 to be stored in the 444, the switching to the internal bus, and the output register This is for controlling the direction of the output to the data input / output terminals IZO0 to IZ07, which is the output data representing the result of the arithmetic processing stored in the data 445.
  • the write / read control unit 441 includes a chip enable signal CE supplied to the chip enable input terminal, and an output signal supplied to the output enable input terminal. Cable signal
  • OE and address input terminals The address signals given to AO to A14 are used as input, input register 444, output register 445, and memory 446.
  • the chip enable signal CEI, CEO and CEM are output, respectively, and the input register's light enable signal.
  • the input data can be written to the input register 444, and the output register 445 and the memory 446 can be used. It controls reading.
  • the start decoder 4 starts the host CPU 2 (start state given from 1) based on the upper three bits A12 to A14 in the address signal. The command is detected and given as a start signal to the processing controller 44?.
  • the input register 444 stores input data relating to input variables provided from the host CPU 20.
  • the output register 445 stores output data representing the operation result.
  • the output register 445 also stores a busy signal (1 bit) given from the processing control unit 447.
  • the memory 446 does not store the data representing the membership functions and the rules given by the PROM writer.
  • the processing control unit 447 takes in input data from the input register 444, latches output data to the output register 445, and outputs data from the memory 446. It controls the reading of various data and the arithmetic processing in the arithmetic unit 448. In order to control the reading and writing of data from the input register 444, the output register, and the memory 446, various control signals (chips) are provided from the processing control unit 447. Power enable signal, light enable signal, lead enable signal, etc.) ⁇ Registration of these registers 444, 445, memory 446 Then, the necessary address signal is output. In addition, a control signal is supplied from the processing control unit 447 to the arithmetic unit 448 to control the arithmetic unit 448.
  • the processing control unit 447 is composed of a sequencer, a micro program memory storing the execution program thereof, and the like.
  • the arithmetic unit 448 is a memo under the control of the processing control unit 447. Use the input data stored in the input register 444 according to the membership functions and rules stored in the 44 ⁇ Then, a fuzzy arithmetic process is performed, and the result is given to the output register 445 as output data.
  • the arithmetic unit 448 is composed of an ALU group for performing addition, subtraction, multiplication and division, MAX, MIN operations, etc., according to the micro program of the processing control unit 4. It is.
  • the processing in this arithmetic unit 448 has been described with reference to the first embodiment described with reference to FIGS. 13 to 15, or with reference to FIGS. 30 to 32. It is the same as the processing in the second embodiment o
  • Figures 35a to 35d and 36a to 36b show the format of the address signal.
  • the upper 3 bits A12 to A14 of the address signals AO to AH are used as control codes.
  • A14A13A12-001 represents the status 'read' command.
  • the status data (the busy signal described above) is stored in a predetermined storage location in the output register 445. Address of All to AO ( ⁇ ⁇ 11 to ⁇ ⁇ 0) following this status 'read command' Data indicates the storage location of output register 445 where the status data is stored.
  • status data is read from the output register 445, and the status data is read via the data bus. It is output to the evening input / output terminals IZO 0 to IZO 7.
  • ⁇ 14 ⁇ ⁇ 0 ⁇ is a command to write the input data 44 to the input register 444.
  • the input data input to the data input / output terminal ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ is written to the input register 444 in response to this input register / write command. It is.
  • A14A A12-011 is a command to read the output data from output register 445.
  • Address following this output register read command Data All to AO (OAU to OA 0) should read the output data of output register 445 Specify the dress.
  • the output data is stored in the storage location specified by address data of output register 445 ⁇ ⁇ 11 to ⁇ ⁇ 0 The output data is read from this, and output to the data input / output terminals IZOO to IZ07.
  • M A O Specifies the address of the memory 446 read or write location that should be written.
  • FIG. 37 shows a memory map in a fuzzy processor 440 defined by such a control code A14A13A12. .
  • Input register 444 Input register 444, output register 445, and memory
  • the write Z read control unit 441 includes a decoder 4 and NAND circuits 454, 455, and 456.
  • One output terminal of each of these NAND circuits 454 to 456 is provided with three outputs of the decoder 457, and the other input terminal is provided with a chip enable. signal
  • the upper three bits of the input address signal such as the control code A 14 A ⁇ A ⁇ , are input to the decoder 457.
  • the decoder 457 refers to FIG. 35a, the address signal format in FIG. 36b, or the memory map in FIG. 37. As can be understood from the comparison, the NAND circuit 454 is supplied with an L-level output signal at A14 AUA 12-0 10. Therefore, the chip enable signal at this time
  • the NAND circuit 454 outputs the L level chip enable signal CEI and provides it to the input register 444.
  • the decoder 457 supplies an L-level output signal to the NAND circuit 455. Therefore, at this time, if the chip enable signal is at CE level ⁇ L level, the NAND circuit 455 level and the chip enable signal at the next level CE 0 is output and provided to output register 445.
  • the write / read control unit 441 further includes an address switching signal generation circuit 451 and a timer for generating a light enable signal WE for the input register 444. It includes an image 452 and a NAND circuit 453. The operation of these circuits is shown in FIG.
  • the input data A0 to A14 are given to the address switching signal generation circuit 451.
  • the address switching signal generation circuit 451 generates an L-level clock and pulse (address switching detection signal) when the input data A0 to A14 change. appear .
  • This address switching detection signal is supplied to one input terminal of the NAND circuit 453.
  • the other input terminal of the NAND circuit 453 is supplied with a chip enable signal CE. Therefore, the NAND circuit 453 outputs the chip enable signal CE signal at the L level and outputs the L level signal when the address switching detection signal is input.
  • a lock pulse is generated and applied to the set input terminal of timer 452.
  • the timer 452 starts a timekeeping operation, and then for a fixed time T (the fixed time T). Outputs a low-active write enable signal WE when the data write cycle is shorter than the data write cycle.
  • the light enable signal WE is supplied to the input register 444.
  • the light enable signal WE for the input register 444 is generated based on the chip enable signal CE, and the control code is output.
  • the data specifies the input register 444, data is written to the input register 444.
  • CE2 is set to the L level, and an address signal indicating the address to be written (including a control code to specify the input register) is applied.
  • a data signal indicating the data to be written and output on the dress bus is output on the data bus, and a light instruction (the light instruction is As described above, by not outputting the signal to the fuzzy processor 44G, the signal is output to the inside of the fuzzy processor 440. Since the enable signal WE is formed, the address of the input register 444 indicated by the address signal is applied to the address of the input register 444 in accordance with the data signal.
  • the represented data will be written.
  • the host CPU 20 writes data to RAM, etc. The same sequence can be used to cause data damage to the input register 444 of the processor 440.
  • the host CPU 20 outputs an L-level output enable signal OE (read instruction) to read data from the output register 445 and so on. At this time, the output enable signal OE is supplied to the reset input terminal of the timer 452. Since the timer 452 is reset by this, the chip enable signal CE is at the L level and the address switch detection signal is generated. However, the output enable signal 0E from the host CPU 20 which does not output the bit enable signal WE is output register 445 and output register 445. Given to these for the reading of data from memory 446 o
  • the writing of the data representing the mastership function and the rule to the memory 446 of the processor 440 is performed by a PROM writer. (Or R0M night). This writing can be performed in much the same way as writing data to a normal PROM.
  • the platform memory 446 is a non-volatile memory, for example, Two
  • P R0M: is R0M.
  • the program power supply Vpp is set to H and the chip enable signal CE is set to L.
  • the output enable signal 0E is set to H respectively.
  • Data indicating the address to be written to the memory 446 as an address signal (A14A13A12 is one of 100 to 111) Is set on the address bus, and the data to be written is set on the data bus.
  • a chip * enable signal CEM designating the memory 446 is output from the write / Z-read control unit 441 and given to the memory. In this way, the above data will be written to the memory 446 at the location specified by the above address. By repeating the above operation, all the main function data and normal data are written.
  • the host CPU 2Q uses the input In the same sequence as writing the data to the register 444 (specifying the memory 446 by the control code included in the address signal) ), And member function data and rule data can be written to memory 4.
  • the output enable signal OE is set to the L level. As a result, data can be read out from a PROM or the like in the same sequence.
  • an output enable terminal should also be provided in the input register 444 so that the output enable signal OE is supplied. It is also possible to read out the data.
  • a light enable terminal is provided in the output register 445 so as to supply a light enable signal WE generated from the timer 452. By doing so, the host CPU 20 can write data to the output register 445.
  • FIG. 40 shows a control processing procedure of the fuzzy processor 44 ° by the host CPU 2 ⁇ ).
  • the input data of each input variable is written to the input register 444 (steps 501 to 5 ⁇ ). This is because the write enable signal from the write / read control unit 441 is transmitted as described above. It is executed by generating WE power. By repeating this process with the same address and data, all input variables used by the fuzzy processor 440 can be used. The associated input data will be stored in the input register 444 of the processor 440.
  • the processing control unit 447 in the fuzzy processor 440 causes the memory 446 According to the rule stored in the memory, the member function stored in the memory 6 and the input register 444 are set.
  • the fuzzy inference processing is performed using the input data (step 504).
  • the output data obtained by the fuzzy inference operation is temporarily stored in the output register 445.
  • the host CPU 20 outputs an address signal including control codes A14A A12-001 to read the status of the fuzzy processor 440. Create, set on the address and bus, and output the read instruction (Step 5D5).
  • the processing control section 4 After the start signal is input, the processing control section 4 outputs a busy signal when the arithmetic processing is being executed, and outputs the busy signal to a predetermined memory of the output register /. It is stored in the place.
  • the busy signal stops, and the bit representing the busy signal of the output register 445 is changed to a bit representing the stop of the processing. .
  • the busy signal stored in the output register 445 or the bit indicating the end of the processing is read out, and the output terminals 100 to 1 are output. Since the data is output to the data node through the address 07, the host CPU 20 reads the bit representing this status, and executes the phage * process. It is determined whether or not the inference processing in step 44Q has been completed (steps 506 and 507).
  • the host CPU 20 stores the result in the output register 445. Sequentially read output data
  • Step 508 When all the output data stored in the output register 445 has been read, the host CPU 20 completes all the processing (step 509).
  • PROM connector and the chip processor of the first, second and third embodiments described above can be replaced with an existing PROM by replacing the existing PROM. It contributes to the expansion of the function of the system.
  • PR0M may be replaced with a PROM-compatible processor.
  • PR0M there is a problem that the original PROM is lost and the ROM space is reduced.
  • the ROM can be replaced with the existing PROM.
  • This is a PR0M compatible processor that does not significantly reduce space and can be used in small-scale systems. is there .
  • the 640 is also attached to the computer system instead of the PROM 32.
  • FIG. 41 shows an example of the configuration of a PR0M compatible port sensor 640 according to the fourth embodiment.
  • the PR0M compatible solenoid and processor 640 are an internal port sensor 641, an internal R0M642, and a pulse length judgment circuit.
  • the configuration of the D-processor 641 is the same as that of the processor 40 of the first embodiment or the processor 240 of the second embodiment.
  • an address bus is connected from an input / output terminal A0 to A14, and an output enable terminal. 0 E The line that leads the force and lead signals is connected.
  • the internal processor "1" and the internal R0M642 data bus are multi-plexer
  • the multiplexer 647 is controlled by an output signal of the pulse length determination circuit 643.
  • the pulse length determination circuit 643 counts the internal clock signal while the oscillator 646 for generating the internal clock signal and the read signal (L level) are given.
  • the read signal becomes H level
  • the counter 644 to be cleared and the count value of the counter 644 are compared with a predetermined set value, and the comparison result is displayed. It is composed of 645 comparators that output signals and control the multiplexer 647.
  • the set value set in the comparator 645 is 4 in this embodiment.
  • FIGS. 42a and 42b The switching operation between the pulse length determination circuit 643 and the multiplexer 647 is shown in FIGS. 42a and 42b.
  • the multiplexer 6 normally connects the data bus of the internal ROM 642 to the data input / output terminals IZO-IZ07. As shown in Fig. 42a, the period during which the level of the read signal provided by the host CPU 20 is L level is short, and the count value of the counter 644 is 4 or less. In this case, the data and noise of the internal R0M642 are kept connected to the data input / output terminals I / O0 to I ⁇ 7 by the manoplexer 647. It is dripping.
  • the multiple multiplexing becomes Internal processor according to 647
  • the data bus is switched so that the 641 data bus is connected to the data input / output terminals 1 0 0 to IZ 07.
  • the multiplexer 647 returns to the state in which the data bus of the internal ROM 642 is selected.
  • the host CPU 20 is either a PROM connector, an internal processor 641 in the chip processor 640, or an internal R0M642. Either can be accessed selectively by controlling the length of the read signal (pulse length or time width).
  • the multiplexer 647 normally selects the internal ROM 642, and the time during which the read signal is at the L level is equal to or less than the internal counter value 4 of the power counter. Since is selected continuously, data can be read from the internal ROM 642 quickly.
  • the host CPU 20 accesses the internal processor 6U, it has to wait until the count value of the counter exceeds four. During this waiting time, the host CPU 20 can access the internal ROM 642 if necessary, but it needs to access the internal ROM 642. If not, the host CPU 20 preferably outputs an address signal representing a specific address during this waiting time. This particular address storage location in the internal R0M642 is not used. Lead message Host CPUs capable of changing the length, which is an L level, are already known.
  • the internal processor 641 is a program that defines its operation (including rules and member functions in the case of a fuzzy processor).
  • ROM or PROM
  • RAM memory
  • RAM memory
  • RAM memory
  • arithmetic unit for performing a predetermined arithmetic operation according to the above program, and control of data input / output and operation of the arithmetic unit.
  • a control unit a control unit.
  • Commands such as operation start to internal processor 641, data read or write command, data to be written and its address and data should be read. All of the memory location addresses, etc., are provided to the internal processor 641 by pseudo address signals via the address bus.
  • the most significant bit of the 15-bit data A14 to A0 represents the read command (1) and the light command (0). Used for It is also used to indicate whether the second bit is status (1) or data (0), such as an operation start command.
  • the remaining bits A 0 to A 12 represent the lead / dress.
  • the remaining bits ⁇ 0 to ⁇ 7 are used for writing data
  • ⁇ 8 to ⁇ 12 are used for the address of the memory location to be written Respectively.
  • the host CPU 20 controls the operation of the internal processor 641 using the address signal and the read signal (read instruction), and controls the internal processor. It is possible to input data to the processor 641 and output data from the internal processor 641.
  • the control section of the internal processor 641, in response to the input of the read signal, is represented by at least the upper two bits of the address signal.
  • the control code when the host CPU 20 that controls the start of operation and the input / output of data accesses the internal processor I as described above. Thus, there is a waiting time until the count value of the counter 644 exceeds 4. During this waiting time, a specific address signal output by the host CPU 2G accesses only a specific internal memory location as described above, and outputs an internal program.
  • the multiplexer 647 selects the internal ROM 642 according to the output of the pulse length judgment circuit 643. During this time, it is preferable that the operation of the internal processor 641 be stopped. Inside The control unit of the processor 641 controls the overall operation stop of the internal processor 641 in response to the output signal (operation stop) of the pulse length determination circuit 643.
  • At least the upper two bits of the address signal are used as control codes for defining the operation of the internal processor 641. It cannot be used to specify the address of the internal ROM 642. It is inevitable that the R0M space of the internal R0M642 will be narrowed.
  • the operation of the internal processor 6U is controlled by the output signal of the pulse length determination circuit 643. If all the 15-bit address signals are used to specify the address of the internal R0M642, the Wear .
  • FIG. 43 shows a modification.
  • An address decoder 648 and a T flip-flop 649 are provided instead of the pulse length determination circuit.
  • the address decoder 648 is provided with an address signal and a read signal.
  • the switching of the multiplexer 647 is controlled by the output of the T flip-flop 649.
  • a specific address for example, 00Oh
  • This particular address is available on both the internal processor 641 and the internal R0M642. It shall not be used.
  • the address decoder 648 upon detecting this particular address, provides a T input to the T flip-flop 649 and inverts it. As a result, each time the address decoder 648 detects a specific address, the internal processor is turned on by the multiplexer 7. The sal and the internal ROM 642 are alternately connected to the data input / output terminals IZOO to I07.
  • FIG. 44 shows still another modification.
  • the dress input terminals AO to A14 are connected to the internal processor 641 or the internal ROM 642 via the demultiplexer 651.
  • the output enable terminal 0E to which the read signal is applied is connected to the internal processor Ml or the internal ROM 642 via the demultiplexer 652. It is.
  • the data buses of the internal processor l and the internal ROM 642 are both connected to the data input / output terminals 100 to 107.
  • the lead signal is also supplied to a pulse length determination circuit 643, and the output signal of the determination circuit 643 is provided according to the length of the period in which the read signal is at the L level.
  • the demultiplexer multiplexers 651 and 652 are controlled by the CPU, and the internal processor 641 or the internal ROM 642 is locked in the same manner as the operation described above.
  • the dress nodes and the read signal lines are connected to the address input terminals AO to ⁇ via the demultiplexers 651 and 652. 3 2
  • an address decoder 648 and a T flip-flop 649 shown in FIG. 43 may be used instead of the pulse length determination circuit 643. Wear .
  • the internal R 0 M 642 in the above embodiment or the modified example may be either a mask programmable ROM or a PROM.
  • the internal ROM 642 is output by the PROM writer. It is preferable that predetermined data can be written to the memory. If the internal processor 641 also contains a PROM, programs (including knowledge data) and data can be written to this PROM with a PROM writer. It is preferred that you do so. Even when writing data with a PROM writer, it is preferable to be able to switch between the internal processor and the internal ROM. O
  • Figure 45 shows a PR0M compatible processor configured to be able to write data to the internal PROM 642 using a PROM writer. Shows a modification of It is.
  • the address input terminals A0 to A14 are connected to the internal processor 641 and the internal PR0M642 by an address / nos.
  • the chip enable terminal CE is connected via the demultiplexer 653 to either the internal processor 641 or the internal PR0M6. Lead signal
  • Output enable terminal 0E is supplied to the internal processor 641 and PR0M6, and is also input to the pulse length judgment circuit 643.
  • the input of the program power supply terminal V pp is given to the voltage comparator 654.
  • the voltage comparator 654 has a threshold voltage between 5 V and 12.5 V and between 12.5 V and 25 V, respectively, and inputs the voltage to the terminal Vpp. It determines whether the voltage is around 5 V, 12.5 V, or around 25 V, and uses the result of the determination as a demultiplexer 653 and bus switching circuit. To route 655 to control them.
  • Either the data bus of the internal processor 641 or the data bus of the internal PROM 642 is passed through the bus switching circuit 655 to the data input / output terminals 100 0 to 10 Connected to 7.
  • the bus switching circuit 655 has bidirectionality, can switch the data transfer direction (direction switching), and has the data input / output terminals IZOO to IZ07 internally. Switch and connect to either the processor 641 or the internal PR0M642 (input / output switching).
  • the direction switching is controlled by the output signal of the voltage comparator 654, and the input / output switching is controlled by the output signal of the pulse length determination circuit 643.
  • the demultiplexer 653 converts the input chip * enable signal into an internal processor 641 and an internal PR according to the output of the voltage comparator 654. 0 Give to both M642.
  • the output of the voltage comparator 654 is used to output data. The direction is switched in a direction that allows output.
  • either the internal processor 641 or the PROM 642 is determined by the pulse length determination circuit 643 to be a data input / output terminal.
  • the input / output of the bus switching circuit 655 is switched so as to be connected to I / O 0 to IZO 7, and the PROM connector and the internal processor of the chip processor are connected.
  • PR0M connector to write predetermined data to the PROM in the PROM 641 or the internal PROM 642 by a PROM writer. The following describes the operation when the camera is mounted on a PR0M line.
  • Either 12.5 V or 25 V is applied to the program power supply terminal Vpp.
  • the bus switching circuit 655 outputs the data according to the output of the voltage comparator 654. The direction is switched in a direction that allows input of data.
  • the output of the voltage comparator 654 makes the demultiplexer 653 Is controlled so as to apply the chip enable signal CE only to the internal PROM 642. This selects the internal PROM 642.
  • the demultiplexer 653 When a voltage of 25 V is applied to the program power supply terminal V pp , the demultiplexer 653 is driven by the chip comparator according to the output of the voltage comparator. Connect the enable signal CE to the internal The switching is controlled so as to give only to the mouth sensor 641. As a result, the internal processor 641 is selected.
  • the internal processor 641 or the internal PR0M642 is selected, and the bus switching circuit 655 is switched to the data input direction, and writing is performed.
  • data is written to the PROM in the internal processor 641 or the PR0M642 by the PROM writer.
  • the voltage applied to the program power supply terminal V pp is adjusted to a voltage suitable for the PROM to be written by an appropriate voltage adjustment circuit, and then the internal program voltage is adjusted. Supplied to the PROM in the processor 641 or the internal PROM 642.
  • PR 0 M Connector °
  • the processor must be used in place of the PROM mounted in the computer evening system. I can do it.
  • the computer system can have its own dedicated processor for fuzzy operation. Will be easier.
  • the PR0M connector according to the present invention in all fields of the computer utilization industry. Tibble ('Fuzzy') / Processor power ⁇ Available.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Read Only Memory (AREA)

Abstract

Processeur compatible avec des mémoires PROM ayant la même taille et présentant le même nombre de broches et la même disposition de broches que les PROMs classiques, mais sans terminal d'entrée de signaux d'écriture-de validation. Pour écrire des données dans un registre d'entrée (44), un signal de pseudo adresse est utilisé. Deux binaires A14, A13 de poids fort, du signal de pseudo adresse A14-A0 représentent des codes de commande, les binaires A12-A8 dudit signal représentent l'adresse du registre (44), et les binaires A7-A0 représentent les données à écrire. Le signal de pseudo adresse A14, A0 est transmis à une mémoire tampon (42) entrée/sortie. Les deux binaires A14, A13 de poids fort du signal de pseudo adresse sont transmis à une unité de commande (41) entrée/sortie. L'unité de commande (41) entrée/sortie décode les binaires A14, A13 si lesdits binaires représentent l'instruction d'entrée du signal de pseudo adresse, l'unité (41) stocke les données des binaires A7-A0 dans l'emplacement de stockage du registre d'entrée (44) spécifié par l'adresse représentée par les binaires A12-A8. Ainsi, l'entrée (l'écriture de données) est possible à partir d'une instruction de lecture.
PCT/JP1992/000105 1991-02-05 1992-02-04 Processeur compatible avec des memoires prom et procede de lecture/ecriture correspondant WO1992014217A1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP3525191 1991-02-05
JP3/35251 1991-02-05
JP4241691 1991-02-15
JP3/42416 1991-02-15
JP8938891 1991-03-29
JP3/89388 1991-03-29
JP8938791 1991-03-29
JP3/89387 1991-03-29

Publications (1)

Publication Number Publication Date
WO1992014217A1 true WO1992014217A1 (fr) 1992-08-20

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AU (1) AU1220792A (fr)
WO (1) WO1992014217A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0540175A2 (fr) * 1991-10-29 1993-05-05 Advanced Micro Devices, Inc. Appareil de traitement de signaux numériques

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Publication number Priority date Publication date Assignee Title
JPS56143049A (en) * 1980-04-04 1981-11-07 Komatsu Ltd Output circuit
JPS5844551A (ja) * 1981-09-09 1983-03-15 Fujitsu Ltd デ−タ書込み制御方式
JPS60177497A (ja) * 1984-02-23 1985-09-11 Matsushita Electric Works Ltd Ｅｐｒｏｍの読出・書込装置
JPS61148547A (ja) * 1984-12-24 1986-07-07 Canon Inc メモリ制御装置
JPH0189757U (fr) * 1987-12-03 1989-06-13
JPH01155594A (ja) * 1987-12-11 1989-06-19 Nec Corp 半導体メモリ回路

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Publication number Priority date Publication date Assignee Title
JPS56143049A (en) * 1980-04-04 1981-11-07 Komatsu Ltd Output circuit
JPS5844551A (ja) * 1981-09-09 1983-03-15 Fujitsu Ltd デ−タ書込み制御方式
JPS60177497A (ja) * 1984-02-23 1985-09-11 Matsushita Electric Works Ltd Ｅｐｒｏｍの読出・書込装置
JPS61148547A (ja) * 1984-12-24 1986-07-07 Canon Inc メモリ制御装置
JPH0189757U (fr) * 1987-12-03 1989-06-13
JPH01155594A (ja) * 1987-12-11 1989-06-19 Nec Corp 半導体メモリ回路

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NIKKEI ELECTRONICS, No. 457, (3 October 1988), (Tokyo), p. 157-165, Nikkei BP Corp. *
SYSTEM/CONTROL/INFORMATION, Vol. 34, No. 5, p. 295-299, (Tokyo), (1990), KATANORI KOGAI, "Fuzzy chip and development". *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0540175A2 (fr) * 1991-10-29 1993-05-05 Advanced Micro Devices, Inc. Appareil de traitement de signaux numériques
EP0540175A3 (fr) * 1991-10-29 1994-12-21 Advanced Micro Devices Inc

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