HU182970B - Equipment for implementing synchronous-asynchronous controls of stored program - Google Patents

Abstract

the invention is. that the apparatus has a memory, a memory address system, an instruction decoder and a control system, and has a reset coupler connecting the listed units. -1-

Description

The present invention relates to apparatus for implementing synchronous asynchronous controls with a stored program. The stored program apparatus 35262-541 / KK of the present invention is capable of performing various control operations, various internal data management or control operations, and various control operations. It is also suitable for controlling smaller systems that do not require a separate computer, or for performing local tasks in a larger system, such as data acquisition and control.

The use of stored program synchronous-asynchronous control devices has economic benefits. however, its application is not justified solely by economic considerations. Such control tasks are usually performed by a sledge machine, but a generic computer with unnecessary additional components for the purpose, and in many cases the accessibility problem does not meet the requirements. Nowadays, the features of the general machine do not meet the requirements of the given task, even the bus system of the ultra-high speed computer does not allow the transmission of horse bit words at 5 MHz, for example! However, in some cases linear vectors longer than > bits may be required, such as at 10 or 20 MHz. These problems are highlighted by Dr. Béla Sebestyén in the second paragraph of page 24 of the Computer-controlled Méi Öreiidszeiek Cinné Book (Technical Publishing House, 1976).

For example, electrically programmable read-only memories, hereinafter referred to as EPROMs, have similar problems. programmer and controller. Yak is expected from the programming and control device. to be able to program and control different types of EPROMs. , - \ z Depending on the type of EPROMs, the access time is 20 lianosce

Up to 2 pse. the pulse length of the typing programmer may vary from a few hundred ps-ec to a few hundred milliseconds, but a s / igotiu order must also be satisfied. \ piogianiozo and control device control should be chosen as a knoli progiam, since traditional methods can only be done very laboriously. Stored program control provides the opportunity. that the programming and control shall be carried out in accordance with the specifications established by the characteristics of the EPROM to be programmed and controlled, which specifications shall be stored per type stored.

It is an object of the present invention to provide a task-oriented, stored-program control device for performing the / predefined control task as quickly and economically as possible.

Based on the examination of the disadvantages of the known digital computing device and the reconciliation of the requirements thereof, it has been found that a realistic solution to the problem can only be achieved with such equipment. which satisfies the following conditions:

1. capable of performing synchronous, synchronous or synchronous control;

2. Suitable for implementing stored program controls.

3. Suitable for treating single-level 1NTERRUPT vector:

4. is capable of producing a wide variety of sequences:

5. Capable of implementing any fixed complexity chain of controls of any complexity;

6. solve the task assigned to him as easily as possible.

In addition, the equipment is like that

- simple in structure, small in size;

cheap compared to similar equipment; it does not require qualified manpower. The object of the present invention may be addressed by the design of a device which fully satisfies the above requirements.

The present invention is based on the discovery that the object of the invention is simply solved by making the device control unit capable of performing synchronous, asynchronous controls and serving requests from external devices.

The apparatus of the present invention is thus an improvement of a known apparatus having a chain-linked address-tile complex. programszámlálója. has a storage and ulasit Decoder. Further development, i.e. the invention, is there. further, the synchronous-asynchronous control unit has a mobile first and second control channel as well as a wiring system communicated between the control unit and the instruction decoder. The control unit outputs are the first. and the output of the ulasit codec is the second control channel. The prograin counter is zero / o. and my inputs, and the tarok selector input is the first control channel first. second. and a third wire is connected. Ín einnniihipleve beiro benien. and the second control channel first to the program counter select input. and a second wire is connected. The input / output of the unit is the wiring system.

Detailed Description of the Invention The invention will be described in more detail with reference to the drawings in which exemplary embodiments of the apparatus of the invention are shown. In the drawing it is

Fig. 1 is an exemplary embodiment of the apparatus of the invention, a

Figure 2 illustrates further exemplary embodiments of the apparatus of the invention, a

3. Further examples of the invention are further sub-examples, husiim11 multiplexes. the abra is the talalinanv seiinu equipment and other exemplary canoe embodiments, soios aiiliiielik.iv.il. the

Figure 5 is a wiring system for the apparatus, with some exemplary embodiments of the control unit, a. FIG. 4A is a few examples of a synchronous-asynchronous controller. embodiment, a

II. some examples of asynchronous controlled abrak; and

15 is a diagram of the operation of the apparatus.

In the drawing, like reference numerals denote similar details. If a part is repeated several times within the same solution, or if another part is distinguished, the reference number is supplemented by a letter and the reference letter is supplemented by a number. The channels with the most wires are marked with ABC upper case letters and the individual wires or outputs with ABC lower case letters. Unidirectional links are indicated by arrows and bidirectional links are indicated by double arrows.

As shown in FIG. 1, a circuit multiplier 34 of a device of the present invention, a program counter 35. It has a 3h storage and 37 instruction decoders. In addition, the device has a control unit 30, the channel A. furthermore, there are 38 cable systems between the first E and second E control channels and between the control unit 30 and the instruction 2168970 decoder 37. The first control channel E comprises at least three, first first, second e2 and third e3, and the second control channel F comprises at least two first fi, second f2 wires. The output of the control unit 30 is the address channel A and the first control channel E, and the output of the instruction decoder 37 is the second control channel F. The first front, second e2 and third e3 wires of the first control channel E are connected to the eraser, address enhancement (serial) input of the program counter 35 and the selection input of the storage counter 36. Connected to the address selector input of the address multiplexer 34 and the program counter 35, the first wire f1 and the second wire f2 of the second control channel F, respectively. The system input / output is formed by the wiring system 38. The data input of the program counter 35 via data channel B is the data output of the address multiplexer 34, the address output via the address channel C to the address input of the storage 36, the data output of the storage 36 via data channel D to the input of the instruction decoder 37 and the address multiplexer 34 connects to the address input of a multiplexer.

After the unit is started, the unit is switched on. When switched on, the first control line E of the first control channel E displays a reset (reset) which resets the storage elements of the unit. The reset initiates a storage read cycle with a time delay from the zero storage address.

If the instruction received at first reading is a waiting instruction, the control unit 30 will enter a wait state, anti will allow processing of service request signals arriving at the wiring system 38.

The control unit 30 remains on hold until a service request is received. Upon receipt of a service request to the control unit 30 from an external device via the wiring system 38, it generates a storage address vector at the address output of the control unit 30 and outputs the cimmultiplexer 34 through the address channel A. which is when the control unit 30 is idle. connected via data channel B to the input of program counter 35. In the idle state, the control unit 30 is provided with a write signal to the input of the program counter 35 via the second control channel F2, which causes the information of the data channel B to be written to the program counter 35. At the address displayed on the address channel C of the program counter 35, a selection read from the storage 36 is made by the selection signal appearing on the third wire e3 of the first control channel E. The data read from the storage 3b is displayed on the data channel D at the data input of the instruction decoder 37 and the address multiplexer 34. The instruction decoder 37 decodes the data associated with its input. The instruction displayed at the output of the instruction decoder 37 is connected through the wiring system 38 to the input of the control unit 38. If the operation defined in the instruction is synchronous, the control unit 30 provides the instruction decoder 37 with the wiring system 38 for synchronous actuator control signals to perform the operation.

If the operation specified in the instruction is a synchronous jump instruction, the instruction decoder 37 causes the synchronization actuator signal received on the wiring system 38 to assign data from the data channel D of the storage 36 to the data channel B of the address multiplexer 34 via a label assignment signal.

Upon completion of the synchronization operation, a new readout from the storage 36 is started, either from the storage address increased by one or from the storage address specified in the jump instruction. If the operation defined in the instruction is asynchronous or other rate synchronous, it provides the control decoder 37 with the control signals required to perform the operation at the output of the control unit 30 via the wiring system 38. Upon completion of the asynchronous cycle, the readout of the increased storage address begins with the storage 36. The synchronous or asynchronous operation described above is repeated until another waiting instruction is received from the storage 36 via the data channel D to the instruction decoder 37. When a waiting instruction is received in the control unit 30, the control unit 30 is put into a standby state and thus becomes capable of processing additional service requesting signals.

In a further exemplary embodiment of the apparatus of Fig. 2, the apparatus includes an instruction store 39 between the data channel D of the storage 36 and the data input of the instruction decoder 37 and the address multiplexer 34.

2-4. In order to simplify each of the drawings, it has been found desirable to omit the control wires of the first and second control channels F, which are connected to the inputs of each of the functional units described above, from the later figures. This means that the program counter 35 and the storage 36 in FIG. 2 receive the control signals from the first forward, second e2, third e3, or 'second f2 of the second control channel F as in FIG. although these wires are not shown in Figure 2. However, at the address multiplexer 34, the first fi line of the second control channel F, as will be seen, is omitted.

The instruction input data input 39 is connected to the data input D of the instruction store via the data output 36 of the storage and the data output via the data channel G to the data input of the instruction decoder 37 and the cimmultiplexer 34. The first front and fourth wires e4 of the first control channel e are connected to the first instruction store wiper or writer input 39. In this embodiment, a single first (label selectable) fi wire is no longer sufficient to configure the cimmultiplexer 34. Therefore, the address multiplexer 34 is controlled by a third control channel L. The second control output of the instruction decoder 37 is connected to the input of the address multiplexer controller 34 via the third control channel L. This third control channel L is comprised of a minimum of two to a maximum of three wires. This embodiment provides the option of entering the data read from the storage 3ö into the instruction store 39, which is a register, whereupon the storage can be deselected during the execution of the instruction. In this case, the information signals required for control are provided by the instruction store 39. Otherwise, the operation of the apparatus is the same as that shown in Figure 1.

In a further exemplary embodiment of the apparatus according to the invention, there is also a second instruction store 40 between the data channel D of the storage 36 and the second decoder 34 of the instruction decoder and the address multiplexer 34, which is also a register (Fig. 2). The data output of the second instruction store 40 is connected via data channel H to the second data input of the instruction decoder 37 and the address multiplexer 34 and to the first and fifth wires of the first control channel E5 to the erase and second instruction word input inputs. Ha cav

The instruction word -3182 970 is not sufficient to define the instruction, then an instruction supplement is needed, which in this case is provided by the second instruction store 40. When the instruction decoder 3 ⁷ interprets the data displayed on the data channel G of the first instruction storage 39 as a two-word instruction, the control unit 30 initiates a further reading of the next one increased by the selection signal given to the selection input 36 of the storage. The data of the next storage address, which is displayed on the data channel D of the storage 36. the signal appearing on the fifth line e5 of the first control channel E is written to the second instruction store 40. Execution signals from the control unit 30 transmitted by the wiring system 38 to the instruction decoder 37. in this case, they are created only after reading the second command word.

In yet another exemplary embodiment of the apparatus of the present invention, the apparatus further includes a denominator store register 41 between the address channel C of the program counter 35 and another third data input of the address multiplexer 34. The data output 41 of the register register 41 of the address book is via the data channel I to the third data input and the write and retract input of the second control channel F through the third channel 1'3. The fourth f4 wire is then connected.

If the instruction read from storage 36 determines a denomination stop and a hop, the input signal provided by the instruction decoder 37 on the third wire f3 of the second control channel F is stored in the address storage register 41 of the program counter 35. At the same time, the instruction decoder 37 overwrites the program counter 35 with the address assignment signal to the third control channel L and the write signal to the second control channel E2 on the first control channel E with the data (address) appearing on the first instruction store data channel G (address multiplexer 34).

If the read and decoded instruction determines a return to a stored address, the data output of the address multiplexer 34 will be assigned to the data channel I of the address storage register 41 as a result of the control signal appearing on the third control channel L. This ensures that the program counter 35 is fed to the input 35 of the denominator register by the bc signal provided on the second control line E2 of the first control channel E.

The instruction decoder 37, on the fourth control channel f4 of the second control channel F, provides a reverse signal to the reverse link input of the denominator register 41. so that the next return, the previously stored address is available on the data channel 1 of the denominator register 41.

In yet another embodiment of the apparatus, there is provided an address index register 42 between data channel D of storage 36 and another fourth data input of address multiplexer 34. The data output of the address index register 42 is connected via the data channel J to the fourth data input of the address multiplexer 34. The fifth input channel F5 of the second control channel F is provided at the wipe input of the address index register 42 at the first forward, write, address enhancer or address reduction input of the first control channel E. and a sixth wire f6, and an overflow or underflow j output is connected to an overflow or underflow input of the instruction decoder 37.

The address index register 42 is erased by the first forward signal of the first control channel E and entered, increased or decreased by the fifth, 5th, and 6th signaling, increasing or decreasing signals of the second control channel F, respectively. With the signal of the sixth wire f6, the address in the address index register 42 can only be increased or decreased. If both increment and decrement are required, this can be accomplished with two separate lines, one for address enhancement and one for address reduction.

The address index register 42 is responsible for assigning an auxiliary address located in the address index register 42 to a given base address. The base address, together with the additional address, provides the actual storage address that you want to access. The advantage of this solution is that it facilitates the execution of a more complex program task.

Further exemplary embodiments of the apparatus according to the invention are illustrated in Figure 3. In another exemplary embodiment of the apparatus, there is also a storage address multiplexer 43 between the address index register 42 of the address index register 42 and the address counter C of the program counter 35 and the storage address input 36 of the storage. The first address input of the storage address multiplexer 43 is connected to the address channel C of the program counter 35, the second address input is the data link J of the address index register 42, and the seventh line f7 of the second control channel F is connected. The 43-címinultip ^{storage, j} 'er címkimenete connected to Ki address channel 36 cimbeinenetcre storage. The data input of the address index register 42 is through the data channel D, the data output of the storage 36, the zero input of the first control channel E and the fifth control channel F of the second control channel F for the input, address enhancer or address reduction input. and a sixth wire of f6 is connected. The address index register overflow output j is connected to the instruction decoder overflow input 37.

The storage cinema multiplexer 43 can be used to directly communicate with each of the storage compartments of the storage compartment 36, of course also having regard to said base address and the deviation up or down provided by the address index register 42. The storage address multiplexer 43 thus provides direct access to a particular storage compartment.

In a further exemplary embodiment of the apparatus

Figure 3 - The apparatus has a bus multiplexer 46 and a read-write storage 36. The first data input of the busmultiplexer 4ö is connected to the data channel D of the read-write storage 36 and the second data input to the data channel J of the address index register 42. The bus input of the busmultiplexer 46 is connected via an additional fourth control channel P to the third control output of the instruction decoder 37 and the data output via N data channels to the data input 36 of the read-write storage. The 8th conductor 18 of the second control channel F is connected to the input of the read-write storage box 36.

The storage 36 in this embodiment is byte-organized and half is read-only storage (ROM) and half is partially read-write storage (RAM). The write-readable storage 36 is written by the instruction decoder 37 with a write signal to the eighth wire 18 of the second control channel F. By using busmultiplexer 46, an internal N data channel can be created to which one or more address index registers, or possibly one or more operation registers, can be linked. The busmultiplexer 46 is assigned through the fourth control channel P by the instruction decoder 37.

In a further exemplary embodiment of the device according to the invention, Figure 3 shows one embodiment of the device

It also has 182,970 second 44 address index registers. The data input of the second address index register 44 is connected via N data channels to the data output of the busmultiplexer 46, and its data output is connected via the K data channel to the third data input of busmultiplexer 46. The first forward line of the first control channel E is connected to the erase input of the second address index register 44, and the ninth f9 and tenth flO lines of the second control channel F are connected to the input, address enhancer or address reduction input of the second control channel E. The output of the second address index register overflow k is connected to the second overflow input of the instruction decoder 37.

The second address index register 44 is cleared by a wipe signal from the first forward line of the first control channel E. Input, address enhancement or reduction is performed by an entry, address enhancement, or address reduction signal from the ninth f9 and tenth flO lines of the second control channel F, respectively.

In a further exemplary embodiment of the device according to the invention, the device also has an operational register 45. The data output of the operational register 45 is connected via M data channels to the fourth data input of the busmultiplexer 46 and its data input via N data channels to the data output of the busmultiplexer 46. The first forward line of the first control channel E is connected to the wipe input of the operation register 45, and the eleventh fiii and twelfth fiy wire of the second control channel F is connected to its input, increase or decrease input. The output of operation register overflow 45 is connected to the third overflow input of instruction decoder 37.

The operation register 45 is cleared by a control signal 30 provided with a first wipe signal of the first control channel E. The operation register 45 is entered, increased or decreased by the decoder 37 in the second control channel F through the fourteenth and twelfth lines 12 and 12, respectively.

In a further exemplary embodiment of the apparatus according to the invention, the apparatus also has parallel arithmetic 47. The first and second data inputs of the parallel arithmetic 47 are connected, via data channels J and K, to the data outputs of the first address index registers 42 and 44, respectively. The data output of the parallel arithmetic is connected via data channel 0 to the fifth data input of the busmultiplexer 46 and to the control input via an additional fifth control channel R via the fourth control output of the instruction decoder 37. Parallel arithmetic 47 provides the ability to perform arithmetic and logical operations between the first and second address index registers 42 and 44 connected to its first and second data inputs via J and K data channels. The result of the operations can be coupled to data channel N through parallel data channel 0 of the arithmetic 47 and busmultiplexer 46. Parallel arithmetic 47 is assigned through the fifth control channel R by the instruction decoder 37.

Figure 4 illustrates a further exemplary embodiment of the apparatus of the present invention in which serial arithmetic is used instead of parallel arithmetic. For the sake of simplification, some of the functional elements shown in Figure 3 with the same function are omitted in Figure 4. However, this simplification does not affect the clarity of the description. The bus N of the busmultiplexer 46 is connected to the data inputs of two first and second operating registers 48, 49 and a secondary instruction store 50. The data output of the secondary instruction store 50 is connected via data channel S to the data input of a secondary instruction decoder 51. The serial p, s output of the first and second operating registers 48 49 are respectively connected to the first and second data ports of a serial arithmetic 52, respectively. The first three r1, second r2, and third r3 outputs of the secondary instruction decoder 51 are respectively serially offset to the first and second operation registers 48, 49 and to the serial input arithmetic selection input 52, respectively, and the serial data output w of the first operation arithmetic 52 Connects to serial data input of 48 registers. The first and second wires of the first control channel E are connected to the input of the first and second operating registers 48. 49 and the secondary instruction store wiper 50 and the thirteenth fl3, fourteenth f14, and fifteenth fi5 wires of the second control channel F respectively.

The first and second operating registers 48, 49 and the secondary instruction store 50 are cleared by the first forward signal of the first control channel E when the device is turned on. After start-up, the number of feedback loops 45 is inserted into the operation register 45 of FIG. 3 using the instruction decoder 37 and the control unit 30. Thereafter, the instruction decoder 37 assigns an input tag to the thirteenth fi 3 wire of the second control channel F! inserts one operand from the N data channels into the first operating register 48. At a later time, the instruction decoder 37 also writes the second operand to the second operation register 49 with a write to the fourteenth line 4 of the second control channel F. Then, at a later time, it writes the secondary instruction store 50 from the N data channel to the fifteenth line fi5 of the second control channel F. Then, as will be seen later, an asynchronous feedback state is created in the control unit 30 which oscillates until the operational register 45 of FIG. The underflow signal removes the asynchronous feedback state. The signals in the asynchronous delay chain in the control unit 30 with the signal at the third output r3 of the secondary decoder 5 1 indicate the operation to be performed and the first and second output nodes r1 and r2 provide offset signals to the first and second operating registers 48,49.

FIG. 5 illustrates a wiring system 38 located between the instruction decoder 37 and the control unit 30, constituting an input / output of the device, a wiring system 38 from service request channel B1, status channel D1, two first instruction channels G1 and second M1, management channels K2, and the sixth control channel II and the seventh Jl control channel. The service requesting channel B1, the status channel D1, the management channel K2, and the first instruction channel G1 are the inputs of the control unit 30, and the sixth control channel 11 is the output of the control unit 30. The sixth control channel II and the seventh control channel J1 are the inputs of the instruction decoder 37 and the first and second control channels G1 and M1 are the outputs of the instruction decoder 37.

Figure 5 shows the address channel A and the first control channel E, which also form the output of the control unit 30. Also shown are the second control channels F, the third L, the fourth P, and the fifth control R, each of the outputs of the instruction decoder 37, and the first G and second H data channels which form the first and second data inputs of the instruction decoder 37;

The service requesting channel B1 consists of n bl-bn wires. The K2 control channel has four, first off, second

It consists of -5182 970 k2, third k3 and fourth k4 wires. The first off wire can be used to turn the unit on, and the second k2 wire to stop the unit. The device operates in continuous mode with the third k3 wire and the step k4 with the fourth k4 signal.

Figure 6 illustrates some exemplary embodiments of the control unit of the present invention. The control unit 30 has a synchronous controller 31, an asynchronous controller 32 and a service requesting logic 33. The two first outputs f and the second k5 and the two inputs of the synchronous controller 31 are connected separately to the two inputs of the asynchronous controller 32 and the first two outputs c and the second b. The two inputs 33 and one output s of the service request logic 33 are separately connected to an output lead, an output t, and an input of the asynchronous controller 32. The asynchronous controller 32, located in the middle of the figure, is separated by a result line from the left synchronous controller 31 and the logic 33 requesting the right hand service.

The function of the synchronous controller 31 is to provide the synchronous controls required for the operation of the apparatus by means of the synchronous start signal received from the asynchronous controller 32 at the output b. The asynchronous controller 32 performs asynchronous control using the synchronous control signals received from the synchronous controller 31 and provides the control logic and gateway signals required to operate the service request logic 33 and the instruction encoder 37.

The service requester logic 33 has a chain-activated request wipe decoder 33a, a service requester register 33b, a request store 33c, and a priority encoder 33d (FIG. 6). The output of the service requester logic 33 is connected to the address output of the priority encoder 33d and the address input of the request wipe decoder 33a. It consists of the output of the address channel and the priority encoder 33d. The input of logic 33 is formed by the service request channel B1, which is connected to the input of the service requester register 33b and consists of n numbers b1 to bn, as well as an outgoing lead and an output t of the asynchronous controller 32. The output lead is connected to the wipe input of the service request register 33b, and the output t is connected to the wipe input of the request wipe decoder 33a and the disconnect input of the request store 33c. The output of the request eraser decoder 33a is connected to the erase input 33 of the service request register 33b via a erase V channel. The wipe V consists of n wires (vl-vn).

When the unit is idle, it becomes capable of serving signals on channel B requesting service. The received request signal is stored in the service request register 33b. If the address vector generation is not in progress, the received request signal is forwarded to the request store 33c and thereby to the priority encoder 33d.

Priority encoder 33d outputs s as a signal to asynchronous controller 32 that a service request has been received. Connects to the A output of the 33d priority encoder to produce the service request address vector. At the same time, the signal at the output t of the asynchronous controller 32 disconnects the request storage input 33c from the outputs of the service requesting register 33b and deletes the received request in the service requesting register 33b using the request eraser decoder 33a.

In a further exemplary embodiment of the apparatus according to the invention (FIG. 6), the synchronous controller 31 has a start logic 31a, a delay circuit 31b, and a synchronous actuator logic 31c. One of the inputs of the start logic 31a and the synchronous executing logic 31c is connected to the first output c of the asynchronous controller 32 and to the output f of the delay circuit 31b and to the output of the start logic 31a of the delay circuit 31b. A second input b of the asynchronous controller 32 is connected to an additional input of the start logic 31a and a third wire k3 and a fourth wire k4 of the control channel K2 are connected to the other two inputs. The two outputs f, k5 of the synchronous controller 31 are formed by the two outputs of the delay chain 31b.

Synchronous delay circuit 31b consists of seven chain-linked delay elements of equal duration. The delay chain 31b has seven branches from which signals which are increasingly delayed relative to the input of the delay chain 31b can be removed. Two junctions are not removed. The lags of the first junction may be removed from the first i, the second j, the third j third, k fourth from the fourth output f0, the fifth junction fi, the sixth from the sixth f2, and the seventh from the seventh output f. The fourth and sixth junctions and outputs are not used, therefore, they are not shown in Figures 6 and 7. In the absence of an instruction store, the storage selection signal is displayed on a third wire e3, which is connected to one of the outputs of the synchronous executing logic 31c and is indicated by a dashed line in the figure.

The synchronous controller 31 has two continuous and manual step modes. In continuous mode, the synchronization start signal at the second output b of the asynchronous controller 32 causes the start logic 31a to output a start signal at the output of the delay circuit 31b at this output. As a result of the trigger and storage selection signal, the storage 36 will be read at the location corresponding to the address. This read instruction may define a synchronous or asynchronous operation. In the synchronous operation, it delivers a control signal to the input of the synchronous actuator logic 31c at the seventh main output of the delay chain 31b. As a result, a synchronization operation signal is provided on the first il wire of the sixth control channel II connected to one of the outputs of the synchronous actuator logic 31c, which gates with the instruction output of the instruction decoder 37 on the first gl wire of the first G1 channel. In continuous mode, the control signal at the output f of the delay chain 31b initiates a cycle reset at the input of the boot logic 31a. Continuous mode is defined by a signal on the third k3 wire of the control channel K2 and signaling on the fourth k4 wire, which is connected to one of the inputs of the start logic 31a. In step mode, one step of synchronous or asynchronous control is performed in response to the step signals from the fourth k4 line. In the asynchronous operation, at the first output c of the asynchronous controller 32, it disables the input of the synchronous controller 31.

In a further exemplary embodiment of the synchronous controller (FIG. 6), the synchronous controller 31 also has OR gates 31d connected to two further first outputs i and second j of the delay chain 31b. The sync control storage storage designation output 31 is formed by the third conductor e3 of the first control channel E connected to the output of OR gate 31d. If the apparatus also has a instruction store 39, the instruction store is written with a token appearing on the fourth line e4 of the first control channel E connected to the output j of the delay circuit 31b. The fourth e4 wire

182 970 is indicated by a dashed line ending in an arrow. At the output k5 of the delay chain 31b, it provides a control signal to the asynchronous controller 32 which provides an address boost pulse to the serial input of the program counter 32.

By initiating the synchronization operation, the synchronous signals appearing at the outputs i and j of the delay chain 31b create a storage signal on the third line e3 of the first control channel E, which is connected to the output of gate 31d OR. As a result, the contents of the addressable compartment of the storage 36 are displayed on the data channel D of the storage 36. The instruction read from the storage 36 is written to the instruction storage 39 by the entry on the fourth line e4 of the first control channel E. The container 36 can then be deselected.

In a further exemplary embodiment of the synchronous controller (FIG. 6), the synchronous actuator logic 31c also has a third input to which an additional fi6 output of the delay circuit 31b is connected. The two outputs of the synchronous actuator logic 31c generate two synchronous actuator signals at different times which are transmitted to the input of the decoder 37 by the first and second wires of the fifth control channel I.

FIG. 7 is a further example of a synchronous controller 31; illustrates an embodiment which also has a sampler logic 31e and a cycle reset logic 31f. To the first input of the sampler logic 31e and the cycle reset logic 31f, respectively, the second jj and the fifth output fi6 of the delay chain 31b are connected. A further second input of the sampler logic 3 and the cycle reset logic 31f is connected to the fourth asynchronous control output 32 of the asynchronous controller 32. A further sixth input of the boot logic 31a is connected to the 0 clips of the loop reset logic 3lf. The other two outputs of the synchronous controller 31 are the fourth e4 and the fifth wires e4 of the first control channel E, which is connected to one of the outputs of the sampler logic 3.

The sampling logic 3le and the loop restart logic 3lf control the multi-word operations. The second output j signal of the delay circuit 31b generates a write signal on the fourth wire e4 of the first control channel E connected to the first output of the sampler logic 3le. This character writes the first word of the data channel D of the storage 36 into the first instruction store 39. The first input of the loop reset logic 31f is controlled by the fifth fi 6 output of the delay circuit 31b and the second input by the two-word command signal at the fourth output n of the asynchronous controller 32. As a result of these two signals, a cycle reset signal is generated at output 0 of the cycle reset logic f. This cycle rewrite signal generates a synchronous cycle start signal at the sixth input of the start logic 31a. The two-word command signal also controls the second input of the sampler logic 31. As a result of the synchronous cycle start signal, a new storage assignment signal appears on the third line e3 of the first control channel E that is connected to the output of gate 31d OR. Simultaneously, on the fifth line e5 of the first control channel E, which is connected to the second output of the sampler logic 3le, the reset signal generates a write signal which writes the instruction appearing on the data channel D of the storage 36 to the second instruction storage 40. Upon reading the second command word, a change of state occurs at the output n of the first (multi-word instruction) storage element 32c, thereby allowing synchronous actuation signals to be generated on the first I1 and second i2 wires of the fifth control channel I and to initiate the asynchronous cycle.

An exemplary embodiment of the asynchronous controller is also illustrated in FIG. The asynchronous controller 32 has a switching logic 32a, a gate 32n OR gate 32n and a delay circuit 320, and a logic 32b that triggers a service 32b between the output of the switching logic 32a and the second input of the gate 32n. The first, second and third inputs of the switching logic 32a are respectively connected to the output b of the delay circuit 32o and the two first out and second wires of the control channel K2. The second and third inputs of the service logic 32b are connected to the first, f, and second k5 outputs of the synchronous controller 32, the fourth input of the service request logic 33 sl, and the fifth input of the G1 instruction channel g1. The four outputs of the asynchronous controller 32 are the first lead of the first control channel E connected to the output of the switching logic 32a, as well as an output b of the delay circuit 32o, and two first outputs c and a second t of service logic 32b.

The device is switched on and off in the asynchronous controller 32 using the switching logic 32a. When the start button is pressed, the start signal coming from the first (start) off wire of the control channel K2 in the switching logic 32a creates an on state. This power-on state can be eliminated by the setting signal on the second k2 cable. The on state generates a wipe signal on the first front wire of the first control channel E, which is connected to the output of the switching logic 32a, which resets the storage elements of the device. Simultaneously, the signal at the output of the switching logic 32a initiates the asynchronous delay circuit 32o through gate 32n, and the signal at its output b initiates the synchronous delay circuit 31b through the startup logic 31a. The signal b from the delay circuit 32o is also fed back to a second second input of the switching logic 32a, which ensures that no further restarting can be initiated with the start button of the device after starting. Synchronization triggers a storage read from the null address, preferably with a pending statement. This waiting instruction is coupled by the instruction decoder 37 through the first gl line of the first instruction channel G1 to the waiting input of logic 32b for service.

In asynchronous mode, determined by the instruction decoder 37, the signal displayed at the second output k5 of the synchronous controller 31 writes the asynchronous operation. This is done by storing the wait instruction on the trigger logic 32b in response to the signal at output k5 and generating a synchronization execution prohibition signal on the first output c for the synchronous controller 31. Subsequently, the signal received at the first main output of the synchronous controller 31 causes the unit to standby and to be able to receive service requests from an external device on the requesting channel B. If the address vector is not in progress, the received request signal is transmitted through the request store 33c to the priority encoder 33d. At the output of priority encoder 33d, s indicates to service logic 32b that a service request has been received. As a result, the service logic 32b generates a signal at the output of t. On the one hand, the output signal t separates the outputs of the service requesting register 33b from the priority encoder input 33d, thereby ensuring that the requesting service address on the address channel A is undisturbed

182,970. On the other hand, the output of t produces an asynchronous start signal at the second input of the gate 32n OR, which causes another asynchronous cycle to be initiated. At the same time, it sends an address boost signal to the serial input of the program counter 35 on the second line e2 of the first control channel E, which is connected to the third output of the service logic 32b. The device performs synchronous or asynchronous control as described above until the device is turned off by the stop signal given to the second k2 lead of the control channel K2.

A further exemplary embodiment of the asynchronous controller is also shown in Figure 6. The asynchronous controller 32 also has a storage element 32c. The first input of the first control channel E is connected to the first input of the multi-word storage element 32c, to the second input g2 of the first control channel G1, and to the third input the second output k5 of the synchronous controller 31. The other five outputs of the asynchronous controller 32 are the second wire e2 of the first control channel E connected to the third output of the server start logic 32b, and the three, fourth i4, fifth i5 and sixth iodic wires 32c of the sixth control channel II connected to the three outputs of the delay chain 32o. output image

The memory element 32c of the asynchronous controller allows the execution of multi-word instructions. The multi-word instruction signal from the instruction decoder 37 on the second line g2 of the first instruction channel G1, and upon the signal from the synchronous controller 31 at the second output k5, writes the storage element 32c. The signal displayed at the output n of the storage element 32c, on the one hand, provides for the restart of the synchronous controller 31 and, on the other hand, prohibits the generation of synchronous execution signals. In addition, the output signal n ensures that the instruction is transferred from the storage 36 to the second instruction storage 40 the next time it is synchronized. The multi-word storage element 32c is reset to its initial position by a new signal from the second output k5, and thus the next read instruction is reintroduced into the first instruction store 39.

Figure 7 illustrates another embodiment of the asynchronous controller. The asynchronous controller 32 also has an additional second storage element 32d (timer logic selector) and an additional second gate 32g (suspending synchronization operation). The first input of the first storage channel 32d of the second storage element 32d is the first gate of the first control channel E, the third g3 of the first control channel G1, the third input of the second k5 output of the synchronous controller 31 and the seventh i7 of the sixth control channel II and an OR gate 32n. another third input is connected. The first input of the second gate 32g OR is connected to the second output c of the requesting logic 32b and the second input to the sixth wire ih of control channel II. The first cl output of the asynchronous controller 32 in this embodiment is the output of the OR gate 32g and a further output of the seventh wire i7 of the sixth control channel 11.

The sequence generation instruction from the instruction decoder 37 on the third line g3 of the first instruction channel G1 is written to the second timing select storage 32d by the second output signal k5 of the synchronous controller 31. The signal appearing at the output of the second storage element 32d, on the one hand, generates a signal at the output of the second OR gate 32g, which is transmitted to the synchronous controller 31 via the first output c1 of the asynchronous controller 32. On the other hand, the signal displayed at the output of the second storage element 32d provides a trigger signal through the first asynchronous starter 32n OR gate to the input of the asynchronous delay circuit 32o. The output signals of the second storage element 32d and the delay chain 32o are the fourth i4, fifth i5, and the sixth wire i6 of the sixth control channel II in the instruction decoder 37 to produce the desired sequence.

A further exemplary embodiment of the asynchronous controller 32 is illustrated in FIG. The asynchronous controller 32 also has a third storing element 32e that defines an additional step-through logic and a step-through logic 32p. Connected to the first input of the third storage element 32e and the instruction break-through logic 32p is the second output k5 of the synchronous controller 31. For the second input of the third storage element 32e, the first leading line of the first control channel E, the fourth input g4 of the first instruction channel G1 and the third input of the first control channel 32n and the second 32g OR gates, respectively, The second input of 32p logic is connected. The state input D1 of the instruction transition logic 32p and one of the outputs i4, 15, i6 of the delay circuit 32o are connected to each of the delay inputs. A further output of the asynchronous controller 32 is coupled to the output of the instruction break logic 32p; The second conductor e2 of the first control channel E is formed.

The instruction pass signal from the instruction decoder 37 on the fourth line g4 of the first instruction channel G1 is stored by the third storage element 32e that selects the instruction break logic as a result of the signal from the synchronous controller 31 at the second output of k5. The signal appearing on the output b2 of the third storage element 32e creates a synchronous start signal on the first gate OR 32n and the delay circuit 32o on the one hand, and on the other hand assigns the instruction pass 32p. The instruction pass logic 32p passes signals from the outputs i4, i5, i6 of the delay chain 32o to the second wire e2 of the first control channel E, which is connected to the output of logic 32p, depending on the transition conditions on state channel D. The signal of the second k5 output of the synchronous controller 31 is passed unconditionally on the instruction pass logic 32p.

FIG. 9 illustrates another exemplary embodiment of an asynchronous controller 32 having a further cycle starter fourth storage element 32f, a delay element 32i, and a first AND gate 32j of a cycle suspender. The output b3 of the first AND gate 32j is connected to an additional fifth input of the first gate 32n OR. The first and second inputs of the fourth starter storage element 32f are connected to the first f and second k5 outputs of the synchronous controller 31, the fifth input g5 of the first control channel G1, the third input of the first forward wire of the first control channel E and the fifth input of the delay circuit 32o. The eighth wire i of the sixth control channel II and an additional fourth input of the second gate 32g OR are connected to the output of the fourth starter storage element 32f. An additional dn wire of the state channel D1 is connected to the second input of the first AND gate 32j of the cycle suspender. The output of the asynchronous controller 32 is provided by the eighth wire i8 of the sixth control channel II.

This embodiment of the asynchronous controller 32 executes the CAMAC cycle. The third input from the fourth decoder fourth storage element 32f is provided by the instruction decoder 37

The signal from the fifth g5 line of the first G1 control channel 182 970 is stored in response to the signal at the second k5 output of the synchronous controller 31 by the fourth starter storage element 32f. Thus, the state of the signal on the fifth g5 line is rewritten to the output of the fourth storage element 32f. This stored assignment signal appears on the eighth line i8 of the sixth control channel II and on the one hand, the delay element 32i, the cycle suspend gate ES, and the first gate 32n OR and the delay circuit 32o, initiates a second input on the AND gate 32j. On the other hand, it provides a suspension signal at the input of the second OR gate 32g, which suspends the synchronous delay circuit 31b and the synchronous execution. The signal appearing on the eighth line i8 of the sixth control channel II assigns the input to the instruction decoder 37. The status signal dn of the state channel D1, which is connected to the second input of AND gate 32j, can suspend the start of the asynchronous cycle. The start signal of the CAMAC cycle, with asynchronous delay circuit 32o signals, generates signals BL'SY, S1, S2 on each of the wires of the second instruction channel M1 through the sixth control channel II in the instruction decoder 37. At the end of the CAMAC cycle, the signal of the output b of the asynchronous delay chain 32o on the one hand clears the fourth trigger storage element 32f. on the other hand, it initiates another synchronous cycle start.

FIG. 10 illustrates a further exemplary embodiment of an asynchronous controller 32 having a fifth sequence starter 32k and an additional two second gates 32m and a third AND 32r. The first input and the second input of the synchronous controller 31 are provided to the first and second inputs of the fifth input 32k, the sixth g6 of the first GI instruction channel, and the fourth input of the operational register 45 overflow m. and the first front wire of the first control channel E is connected to its fifth input. Connected to the output of the fifth storage element 32k is the ninth wire i9 of the sixth control channel II, as well as the first input of the second AND gates 32m and third 32r and an additional fifth input of the second or gate 32g. Connected to the second input of the second AND gate 32m is the fourth output il 2 of the delay chain 32o. The output b5 of the second AND gate 32m is connected to an additional sixth input of the first gate 32n OR. The second input of the third AND gate 32r is connected to the bb output of the delay chain 32o. A further output of the asynchronous controller 32 is the ninth wire i9 of the sixth control channel II, and the output b of the synchronous cycle starter is the output of the third AND gate 32r. The data output of the bus 45 is connected to the parallel data input of the operation register 45 via N data channels, and to the control input of the second output i5 of the delay chain 32o. In this embodiment, the operation register 45 is previously loaded in synchronous mode according to the number of asynchronous cycles. Then, a start instruction from the sixth gate of the first instruction channel G1 is written to the fifth storage element 32k by the signal coming from the second output k5 of the synchronous controller 31. As a result, the signal displayed at the output of the fifth initiating storage element 32k initiates the asynchronous delay circuit 32o through the second AND gate 32rn and the first 32n OR gate, the fourth output of which is fed back to the second input of the second AND gate 32m. The output of the fifth storage element 32k on the ninth i9 wire of the sixth control channel II provides a prohibition signal to the first input of the third AND gate 32r, and the ninth wire i9 provides information to the instruction decoder input 37 for the signal duration and the asynchronous . As described, a feedback loop is created which persists until the overflow signal at the output m of the operational register overflow 45 resets the fifth storage element 32k. The input of the operating register counter 45 receives control from the second output i5 of the delay chain 320. First outputs i4, second outputs i5, nth outputs i6 of the delay chain 32o, which can be used, for example, to actuate serial arithmetic, are output. The operation register overflow signal 45 resets the fifth storage element 32k, thereby allowing the output signal of the delay circuit 320 to generate a new synchronous cycle start signal via the third AND gate 32r at the output b.

All. FIG. 3B illustrates a further exemplary embodiment of an asynchronous controller 32 having a further sixth storage element 32h and a fourth fourth AND gate 32s. The first and second inputs of the synchronous controller 31 are the first and second outputs of the synchronous controller 31, the first in the first control channel E, the fourth in the eighth g8 of the first control channel G1, and the fifth inlet 538, respectively. network k6 output is connected. Connected to the output of the sixth storage element 32h is the tenth line 10 of the sixth control channel II, as well as the first input of the sequential network 53, the first and the second sixth inputs of the third AND gates 32r and fourth 32s. The fifth input i5 of the sixth control channel II is connected to the second input of the sequential network 53. Another output of the asynchronous controller 32 is the tenth wire 10 of the sixth control channel II.

A feature of this embodiment, as compared to the embodiment of Figure 10, is that the apparatus may contain not one but a plurality of operating registers. In the figure, two first and second operational registers 54, 55 are connected to a sequential network 53. The first and second operational registers 54, 55 can be programmed by means of a signal connected to the fourteenth fi4 and thirteenth fl3 wires of the second control channel F, respectively. The first forward line of the first control channel E is connected to the wipe input of the first and second operating registers 54, 55. The first and second operation registers 55, 54 are loaded as described above.

When the sequential mode is set up, a feedback network similar to that described in FIG. 10 is created. The desired signal sequence is provided by the sequential network 53. The fifth input f5 of the sixth control channel II is connected to the second input of the sequential network 53 and to the second output of the delay chain 32o. The second serial k7 output of the sequential network 53 is connected to the first and 544, 55, serial inputs of the second serial k8. The state of the sequential network 53 is changed by an overflow signal at the serial output s of the first operating register 54. Thus, the sequence of signals on the fifth i5 line of the sixth control channel II is the second operating register 55

-9182 970 turns through the third k8 output of the sequential network 53. The state of the sequential network 53 is maintained until the overflow signal at the serial p output of the second operation register 55 changes it. Further operation registers can be connected to the sequential network 53 as described. Thus, the states of the sequential network 53 are changed by the overflow signals of each of the operation registers. These state changes, in turn, assign a serial input to each operation register. The programmed prescribed sequences result from the decoding of the sequence state, which is coupled via the seventh control channel J1 to the input of the instruction decoder 37.

Or At the completion of the desired sequence generation, the overflow signal of the last output register serial output clears the code output of the sequential network designation sixth storage element 32h, thereby allowing another synchronous cycle start signal to be output through the third AND gate 32r.

12 -15. Figures 3 to 5 are diagrams illustrating the operation of the apparatus, in which, on the horizontal t-axis, the time relevant for operation is denoted by Arabic numerals beginning with zero. On the vertical axis, the control channel K2 is out first. first control channel E, first e2, third e3, fourth ed and fifth e5. and first fi and second f2 of the second control channel F. sixth control channel 11 first, second i2, third 13, fourth i4. fifth i5. sixth, eighth, Isa. the ninth iT and the twelfth 12, and the first instruction gateway G first gl, second g2. fourth g4, fifth g5, and sixth gos. and the requesting BI channel is an arbitrary bi. and the downstream shunting line D1 on the nth dn line and the synchronous delay circuit ib. j. k5. lake. 11. t2. f. and the first c. of the asynchronous controller 32; and cl. the second b. the third t. the signals appearing at the output of the fourth n and the service logic 33 requesting sl are shown. The symbols of each time diagram are shown from top to bottom of each diagram.

Figure 12 shows a time diagram of the operation of the equipment in the instruction store. The left side of the figure illustrates the execution of the wait instruction and the right side shows the request service. The triggering signal on the first out line at that time causes the unit to turn on. If the unit does not contain an instruction store, the storage line mark will appear on the third wire e3 after powering on. At the same time as the power is turned on, the eraser on the first lead will reset all the storage elements in the unit. The start signal first initiates the asynchronous 32o delay chain. having a fourth i4 connected to its first, second and nth outputs; fifth i5. and a sixth wire shows a unit width control signal. The last element of the asynchronous 32o delay chain eg \ test abolishes the first e! leads to a wipe signal and on the other hand initiates a synchronous delay chain 31b. The 3 TB delay chain i. j, who. main. 11. f2. The unit width signals displayed at the f outputs are the synchronous controller 31. asynchronous controller 32 and service request logic 33 controls. and gating the instruction decoder 37. The first ti on wire up to t2 or i? Until ti0, the label selection mark appears.

At the second output time b, the unit wide synchronous start signal is displayed. Λ On the third line e3, a two-width storage mark is displayed at time t2. On the fourth line e4, a unit-width instruction store entry is displayed at time t3. The signal at the second output k5 of the synchronous controller 31 increases the content of the program counter 35 and at the time t5 inserts a waiting instruction signal from the instruction decoder 37 on the first gl wire into the service logic 32b, which starts the service in the asynchronous controller 32. cl disables synchronous execution. The first and second synchronous executing signals are not displayed on the first wires il and the second i2. These marks are represented by dotted squares in the figure between the times t5 and the horse. The unit enforces the standby state V at the time of the lake so that the unit is capable of serving requests from external devices. The asynchronous controller 32, at the third output of t, provides an enable signal to the service logic 33 input. If a service request is received on any bi line at time t7, the service request logic 33 indicates on sl output that a service request has been received. If the unit is in standby mode. and at the same time, a service request is received, the service logic 32b generates an output signal at the third output of the asynchronous controller 32, the face initiates the asynchronous delay chain 32o and disconnects the data inputs of the request store 33c from its data outputs. Simultaneously, the decoder 37 selects the cymmethyl typlexer 34 through the first wire. so that the addressees on the address channel ator are connected to the data input of the program counter 35. At the same time, the device deletes the received request with the help of the decoder 33a decoder. Λ writes, at time S, a second signal on line i2, the data at the program counter 35's data inputs to the program counter 35 output, which is coupled via the address link C to the address header of the storage 3o. At the second output time b, the unit-width synchronous-start trigger signal appears, which causes the third line e3 to display the two unit / sharp storage markers. On the fourth line e4 (at time II, the / denial store symbol is displayed, which stores the data of the storage 3o in the 3 ¹ · 'passenger storage).

The unity / sharpness signal at time 2 at the output of the second output increases the content of the program counter 35 and, at 113 times, samples the asynchronous or other rate synchronous instructions from the instruction decoder 3 ^{7 on} the first gl line. The first i! and the second i2 line ti3. and 115 and 115, respectively, the first and second executables with / unity / sharpness are displayed. which are connected to his ^-7 instruction decoder input. The ulasit Decodes 37 are the. transmits the signals of the first ti and the second i2 wires to the controlled device via the second instruction channel M1.

FIG. 13 illustrates a timing diagram of executing a soft / acid instruction and instruction transition, a second uniform output line output signal being displayed at time t3 on the third line e3 as a result of the second output output b. The unit / sharpness signal at time t2 on the fourth wire e4. writes the contents of the container to the instruction store. A single-width signal appearing at the second output t5 k3, on the one hand, increases the content of the program number 35 via the second line e2 and on the other hand writes the two-word instruction item to the first storage 32c. Four-n output multi-word command signal provides feedback on loop-reset 3 lf logic

-101

182 90 and through the boot logic 31a to reboot the as / inkron 31b key. As a result, at time 15, a second two-width storage select signal appears on the third line e3. .this fifth unit line signal at the time of the fifth e5 line is the storage container 36. writes it to the second 40 glass containers. Λ second k5 ktnieneten time t ^_ niegjelenó unit width E2 of the second signal at the line 35 and the fourth programszániláló content noveu r output multiword instructions winter eliminates idApómban ib. If synchronous traversal is defined in the instruction, execution signals of unit width s / mk will be displayed on the first il and the second 3 wires! * ·> And ti 1 respectively. ΛThis 2 bow loops are triggered again and this causes the third e3 wire to have two unit / width stall markers. Λ fourth e4 leads are filled with the contents of taro 39 into the first instruction store 39. The unit width signal at the second output k5 at time t14 increases the content of program counter 35 on the second line e2 and writes the green / h instruction from the instruction decoder 3 'on the fourth line g4 to the third -2c storage element designating logic pass 52p. To water this, a> e \ z; the first I output! At 115 times, a plurality of units of s / incroncikhss telfiigges are created, the other at the first -2n \ (, Y at at asynchronous delay signal to the output of massive 32p logic kapesoll at second e2 ve / at 110 at tIS time they provide ninbb egv hels / e.egue address enhancement signals to the serial input of 3 piogliums / amuío, depending on the state of the switching 52p logic heme. the course of which takes place in front of the einwi'iiat t-ixu λ meg!

\ 14 ai'ia a (AM M Operation Cycle Time Charts: with Operational Suspend Option. \ Second, every ·· output · s / mknmcycle start signal! Time) mg. Limit stored at t2 time ^: io- \: 5 appearing unit ·

-.zele.sseen ic: Details for 5n '.j'.olo! to the passenger cabin 5 '> ia Hj j. u ío'j 't AMA! loops ke / yemen / essay. the

i.t'K c? ezme-mv; after 5 dates!

The second k 'marks of taste l · · v i a l l l l l l · · v are introduced into the cyclone primer. The fourth 521 'landscape ···. miie · mmereiem connected on the eighth iS wire t5, m p ·· mumm make some ici second 52g OR get »;: .η -zmk · ti-fellugges / io sign! gives the first cl chime, · -image m. ·,, -, maisul 51b kcsic'lelokmcot until je-.mi Mis · .. · - .. ·:: output of fourth 52Í tm'olo element e - -2: k dm roof principle mc cycle 'eb' tgges / Take the first.-2F.Skanar '> ib' .t at. ba state dn ve / eq mm mm: fourth t4 ve / el down connected to the output of .iv.'tkron 32o keselelu-toeo Λ 52o late at ·, third knneneiere connected third '5 •. unit width knife effect at t10. they found it. which are inputted to the instruction decoder 57 These signals create the BL'SY on the second decoder channel 37 in the travel decoder 37. Sl. S2 plot, This'. following the /, asynchronous 32o delay chain atom.o, the signal at the connected second output b 2 at t 2 of time deletes the fourth cycle id 52f: o'oeieme. and another synchronous cycle initiation ke / de \ I 'abm is illustrated in Figures 4 and 10. · itta-atas time diagram. At the time Άto, the single-width synchronous operation signal on the first line i1 writes the number of feedback loops into the operation register 45 as the input for the eleventh line I1 of the instruction decoder 3 '. At time t1, the executing signal of the first line il, as one of the thirteenth fi 3s of the instruction decoder 37, writes an operand into its first operation register 48. At time t2, the executing signal of the first conductor il writes the second operand into the second operative register 49 as a signal for the fourteenth conductor F14 of the instruction decoder 37. At time t3, the executing signal of the first wire il writes the secondary instruction store 50 as a signal of the fifteenth wire 15 of the instruction decoder 37. At time t4, the arithmetic operation command from the instruction decoder 37 on line g6 is triggered by the signals of the first output f and the second output k5 into the fifth starter memory 32k. The ninth Ϊ9 signal connected to the output of the fifth storage element 32k denotes the second AND gate 32m of the feedback loop and, at the same time, the third AND gate 32r, which is connected to the large output of the asynchronous delay circuit. This produces a feedback network which oscillates as long as the fifth state of the 32k storage element is maintained. When the operation register 45 connected to the fifth input of the fifth storage element 32k with an in output underflows, this occurs at time t. An underflow signal deletes the 32k storage element. the output of which is coupled to a ninth i9 lead signal now prohibiting further feedback and allowing the third output gate 32r ES to output sS at time tS. The fifth i5 and twelfth il 2 wires are connected to the second and fourth outputs of the asynchronous 32o delay chain. and the signal of the ninth wire i9 connected to the output of the fifth storage element 32k through the secondary path decoder 5 indicates, on the one hand, the expected operations for serial arithmetic 52 and the offset signals on the first and second opio 4 »for the register.

Claims (14)

1. Removal of Berende / Cs stored piogumu s / mkron-asijionion conductors. whose 'inc'-O k.iponh is the addressliplcvere. prograniszátiilaE'jj. imoluj.i e- ntasit.is ûck üície var. az / ai /eHimi'Z-.e. Itogv x / mkiónvezerlöbol (5 ') cs as nttronroncontrollerb.7 ι51 t. something small /:>! gal.ist kciai. logic (55 | consisting of a control unit l.'lh. lucucaiornaja I \ l. and two. first and second lead units (E. 1). and a control unit 15t ¹ 1 and the passenger decoder ι.Γ) were terminated: ends / erc. | 3S) is also available. the control unit (510 outputs of the address channel t \ t and the first \ ezi! öi.satoii) is ι Γ). the output of the instruction subcode I 5 is formed by the second control channel 11- », the eraser or cunnovelo input of the prograncial slam 5c), and the tarolo (5oI selection input to the first control channel II first and second wires). and the first and second wires (fi 12) of the second control channel (E) are connected to the address input of the address label tile (541) and the write input of the program controller (35), as well as the output of the device. / etékreelids / er (5S) An embodiment of the device according to claim 1, characterized in that the storage channel (56) has an atlet channel ID) and 1 1 -11182 970 is the instruction decoder (37). and an instruction store (39) between the data input of the address multiplexer (34). the data output of the instruction store (39) on the data channel (G) being the data input of the instruction decoder (37) and the address multiplexer (34), and the first control channel (L) being the erasure or writing input. and fourth wire (el, e4). and a second vc output of the instruction decoder (37) is connected to the control input of the e-mail modulator (34) via a third control channel (L). An embodiment of the apparatus of claim 2, characterized by. that between the data channel (D) of the container (36) and a second second data input of the destination decoder (37) and the address multiplexer (34), the data output of the second instruction store (40) is transmitted through the data channel (H). a second data input and an erase or write input of the first control channel (E) to the second data input of the instruction decoder (37) and the address multiplexer (34). The apparatus according to claim 3, characterized in that the address counter (C) of the program counter (35) and a third denomination storage register (4!) Of an additional third data input of the address multiplexer (34) are provided. a data output of the line storage register (41) via a data channel (1). the third data input of the address multiplexer (34). and the third and fourth wires (t'3. t'41) of the second control channel (E) are connected to its input and retractors. 5. According to 4, verbs! equipment for construction ul.ikia. Ask for a character. that the data channel (D) of the storage (56) and an additional fourth data input of the address multiplexer (54) is eimindexexis / .ter (42). the data output of the address index register (42) on the data channel (jl at the fourth data input of the address multiplexer (541), the erasure input of the address index register (42) is the first line of the first ve / row (E) a second control channel (the fifth and sixth wires 14 and 15, respectively) of the cone is connected to the talesmdulas input of the instruction iscodes (5) An embodiment of the apparatus according to claim 4. characterized by the ιd.it · - · i gymnastics of dcx-rcgisztet (42) (Jl. further has a tai-lio-elimeplexer (45) of the pi count counter (55 I) ((and I of the container (56)) for the first e-input of the (addressing) multiplexer (45) for the second address input of the progialassay (551 e-mail address (C). for the e-mail multiplexer (43)) and for the e-mail address of the storage eiminultiplexer (43). to the address input of the store (5n) and the seventh line (P) of the second ve / die.i tor (! ') to the input input of the address index index (42) on the data channel (Slide of the storage channel (5) | for the erase input, the first conductor (el) of the first control channel (E), the input of the second control channel (14, the fifth and the sixth conductor (f5. Its), for entering, addressing or addressing, and the decoder (5 '). connected to the overflow input. 7. An apparatus according to claim 6, characterized in that it is a tuple (40). I have a read-only memory (56) for something. a data channel (D) of the read-only storage (56) for the first data input of the biismultiplexer (46). and for the second data input, the data channel (J) of the address index register (42). to the controller input via an additional fourth control channel (P) at the third control output of the instruction decoder (37), the busmultiplexer (4h) output via the data channel (N) to the data input of the read-write storage (36) and the eighth wire (t'8) of the second control channel (F) is connected. An embodiment of the apparatus of claim 7, further comprising a second address index register (44), a data address and a data output of the second address index register (44) via a separate data channel (N.K) on the biismultiplexer (46). ) is connected to its data output or third data input, and to the erase input of the second address index register (44), the first wire (el) of the first control channel (E), the ninth or tenth wire (t) of the second control channel (I) 9, f 10), and the overflow output (s) is connected to the second overflow input of the instruction decoder (37). An embodiment of the apparatus of claim 8, further comprising an operating register (45). the data input and the data output of the operation register (45) break out via the separate data channel (N. M) to the data output of the biismultiplexer (46). and for the fourth data input, the first wire (el) of the / first control channel (E). the eleventh or tixetine wires of the second control channel (til 112), respectively, for entering, increasing or decreasing the input of an input or output. the overflow output (m) is coupled to the third overflow input of the commandJekinlei (- '). 10. The apparatus of claim 1, further comprising: a continuous ai 4 "). for paimin / amos antinenk.i (4i cbo C 'for the second data input on a single egv data channel (j. clat the first. and second cimindex registers (42.44 ι data output. parallel ai itnicüka ιΡ ι ada' output adaicsa ' oinan l0) .it is busunil: iplexei (4 (0 fifth data input, vve input input and egv additional 5th input / output) (Ri at azijsek.isdekoJei (5'4 fourth vc / e: lo output) 1). \ on demand pom code implementation downgraded with it. bogi a 'ui'einib ipiever I 4 (>) adams.iioi na | a (\) kél. eev cho e> egv second opci ace) 'icgisz le: | 4S. 49 |. something egv m.iO.ji.igns instruction for input of anno (pO) data, secondary atasii.islaroio | ^; m adatkimeiicic adal. saloiu.m ISI ai is a r.saso-specific instructionJekődci (51) adaibenieu recommended. the eho c> the second operating reg / le: i4s. 49 | 5.01 Continued Output s) a salt arylmeuka (52) first. or its second data input, the secondary ul setup decoder! (5!) I can. first. the second and third body (i.e., i2. i5) of each other is the input of the first and second opei.i <Ps regist / iei (48.4 '!). and the serial input for serial travel (52). the rail ardinclika P2) soios data output (.vl the first opeijcm ·, regist / ici ι-P) serial adalbenieiieteie. in horses, the opioid and the second opaque 1 umbrella (4s b'i. vakimuti to the louvre input of the mjvnihgo.s instruction store (5t>), the first ve / cilöc'aíorua 1 b) the first wire lei), bem. and its input on ku separately .1 second ve / er-esaioina (|) ti / enhai madik. fourteen. illeive ye / .olen wires (115 114, ye 51 connected. 12. An embodiment of any one of claims 1 to 4, wherein the cable (38) is a service exchange channel (R1). from statuscool'aina (141). from two first and second ulcerative hernias (Gl. M1), treatment canal (k2). and a further one, dying and consisting of a seventh control channel (11 J I). -121 182,970 the service request channel (B1), the status channel (D1), the first instruction channel (G1) and the control channel (K2) are the inputs of the control unit (30), and the sixth control channel (11) is the output of the control unit (30), the first and second command channels (G1, M1) being the output of the instruction decoder (37), and the sixth and seventh control channels (II, J1) forming the input of the instruction decoder (37). An embodiment of the apparatus of claim 12, wherein the control unit (30) is a synchronous controller (31). it has asynchronous controller (32) and request logic (33), two first and second outputs (f, k5) and two inputs of the synchronous controller (31) separately with two inputs and two first and second outputs of the asynchronous controller (32) b) two inputs and one output (sl) of the service request logic (33) are also connected separately to a wire (el), an output (t) and an input of the asynchronous controller (32). 14. The apparatus of claim 13. characterized in that the requesting logic (33) is a chained request deletion decoder (33a) and a service requesting register (33b). it has a request store (33c) and a priority encoder (33d). the output of the service request logic (33) to the address output of the priority encoder (33d) and the address input (A) of the request eraser decoder (33a) and the output of the priority encoder (33d) to the input requesting service register (33b) a request channel (B1I) and a lead (el) and an output (t) of the asynchronous controller (32), the lead (e 1) to the wipe input of the service request register (33b), and the output (t) to the request wipe decoder (33a) and is connected to the disconnect input of the request store (33c). An embodiment of the apparatus according to claim 1, 3 or 14, characterized in that the synchronization controller (31) has a start logic (31a), a delay circuit (3lb). and synchronous actuator logic (31c), the first output (c) of the asynchronous controller 132) for each input of the actuator logic (31a) and the synchronous actuator logic (31c). the output (1) of the delay chain (31b), the output (e) of the output logic (31a) for the input of the delay chain (31b) and the second output (b) of the asynchronous controller (32) separately for the other three inputs of the startup logic (31a), and the two third and fourth wires (k3. k4t) of the control channel <K2), and the two outputs of the synchronous controller (31) are two outputs (f. k5) of the delay circuit (31b). Shoot. The apparatus of claim 15, wherein the synchronous controller (31). also has a third gate (31d) connected to the other two outputs (i, j) of the delay chain (31b), a third wire (e) of the first control channel (E) connecting the memory selector output of the synchronous controller (31l) to the output of the gate (3d) ). I ”A lo. An embodiment of the apparatus according to claim 1. symbolized by that. that the third input of the synchronous actuator logic (having an additional Third input. the third input is connected to an additional output of the tamper circuit (31b), the two other outputs of the synchronous controller (31) being connected to one of the outputs of the synchronous execution logic (31c). the first and second wires (il, i2) of the control channel (11). lb. An embodiment of the apparatus of claim 13. characterized in that the synchronous controller (31) also has a sampling logic (3le) and a cycle reset logic (31f), the second input of the delay circuit (31b) being provided to the first input of the sampling logic (3le) and the cycle reset logic (3f). and a fifth output (j, fi 6), and a second input of the fourth multi-word instruction output (n) of the asynchronous controller (32), and an output (o) of the cycle reset logic (31f) and a further sixth input of the boot logic (31a). connected, the other two outputs of the synchronous controller (31) are the fourth and fifth wires (e4, e5) of the first control channel (E) connected to one of the outputs of the sampling logic (3le). 19. An embodiment of the apparatus according to any one of claims 1 to 5, characterized in that the asynchronous controller (32) has a circuit-switched switching logic (32a), an OR gate (32n) and a delay circuit (32o) and an output of the switching logic (32a) and a second input of the OR gate (32n). between the first, second and third inputs of the switching logic (32a), respectively, the output (b) of the delay circuit (32o) and the two first and second wires of the control channel (K2) (off, k2). ), and one of the first and second outputs (f, k5) of the synchronous controller (31) to the second and third inputs of the service logic (32b) and the fifth (in) of the requesting logic (33) to the fourth and the first wire (gl) of the instruction channel (Gl) is connected, the first control channel (E) connecting the four outputs of the asynchronous controller (32) to the output of the switching logic (32a) the output (b) of the delay chain (32o) and the two first and second outputs (c, t) of the service start logic (32b). An embodiment of the apparatus of claim 19, wherein the asynchronous controller (32) further comprises a storage element (32c), the first input (1) of the first control channel (E) at the first input of the multi-word storage element (32c), a second wire (g2) of a first instruction channel (G1) and a third input (k5) of the synchronous controller (31) connected to its third input, a first control channel (E) connecting the other five outputs of the asynchronous controller (32) to the third output of the service logic (.32b). the second line (e2) and the third fourth, fifth and sixth lines (i4, i5, i6) of the six control channels (II) connected to the other three outputs of the delay chain (32o) and the output (n) of the multi-word storage element (32c). An embodiment of the apparatus of claim 20, wherein the asynchronous controller (32) further comprises a second second storage element (32d) and an additional second OR gate (32g), a first instruction channel for the first input of the second storage element (32d). (G1) a third wire (g3), a second input (e5) of the first control channel (E) for its second input and a second output (k5) of the synchronous controller (31) for its second input and a seventh wire (i7) for the sixth control channel (11). ) and an additional third input of the first OR gate (32n), the second output (c) of the service request logic (32b) for the first input of the second OR gate (32g) and the seventh wire (i) of the sixth control channel (1). ⁷ ) connected, the first output (cl) of the asynchronous controller (32) is connected to the output of the second OR gate (32g) and the seventh wire of the sixth control channel (1) connected to the output of the second storage element (32d) (i7). 22. The apparatus of claim 21, wherein the asynchronous controller (32) -13182 970 also has a third third storage element (32e) and an instruction transition logic (32p), first inputs of the third storage element (32e) and an instruction transition logic (32p), a second output (k5) of the synchronous controller (31), a third storage element (32e), the first input channel (el) of the first control channel (E) for its second input, the fourth wire (g4) of the first control channel (G1) for its third input, and the first and second OR gates (32n, 32g) an additional fourth and third input, and a second input of the instruction passage loric (32p), a state input (D1) for the state input of the instruction transition logic (32p), and an output of the delay chain (32o) for each delay input Connected (i4, i5, i6), the output of the asynchronous controller (32) is formed by the second wire (e2) of the first control channel (E) connected to the output of the instruction transition logic (32p). 23. An embodiment of the apparatus of claim 22, wherein an additional fourth storage element (32f) of the asynchronous controller (32) is chained. delay (32i). I also have an AND gate (32j) of something. the output (h3) of the AND gate 2 (32j) being connected to an additional fifth input of the first OR gate (32n), the first and second inputs of the fourth gates (32f) being the first of the synchronous controller (31). and its second output (f, k5), and its third input is the fifth wire (g5) of the first instruction channel (G1). the fourth input of the first control channel (E) is the first wire (el), and the fifth input is the output of the delay circuit (32o) (b). and an additional fourth input 3 of the sixth control channel II (eighth wire 18) and the second OR gate 32g. and a second line (dn) of the status channel (D1) to the second input of the first AND gate 32j. A further output of the asynchronous controller (32) is formed by the eighth wire (lIS) of the sixth control channel (11). 3 24. The apparatus of claim 23. with that. Thus, an additional fifth storage element (32k) of the asynchronous control (32). and having additional second and third AND gates (32m, 32r), the first and second outputs of the first and second outputs (f, k5) of the synchronous controller (31) for the first and second inputs of the five input fifth storage elements (32k) (Έ) first wire (el), fourth input of operating register (45) serial output (m), fifth input g of first instruction channel (G1) sixth wire (go) and output of ninth wire of sixth control channel (11) (i9) , and the second and 0 first input of third AND gate (32m, 32k). and a further fifth input of the second OR gate (32g). the second input of the second AND gate (32m) is the fourth output (il 2) of the delay chain (32c) and its output (b5) is an additional sixth input of the first OR gate (32n). the second input of the third ES gate (32r) is connected to the output (boo) of the delay chain (32o). a further output of the asynchronous controller (32) is the ninth wire (i) of the fade control channel (II). 25. The apparatus of claim 24. characterized in that the asynchronous controller (32) has an additional sixth storage element (32li) and an additional fourth AND gate (32s). the first and second inputs of the six-input sixth storage element (32h) being the first of the synchronous controller (31). and its second output (f. k5). for the third input, the first conductor (el) of the first control channel (E). for the fourth input, the eighth wire (gS) of the first instruction hook (G1). and a fifth input of a sequential network (53). the sixth The tenth line (ilU) of the sixth control channel (11) is output to its 10 storages (32h). and a first input of the sequential network (53). the third and fourth ES gates (32r 32s) first. and a further sixth input of the second OR gate (32g). sequential The second input (15) of the network (53) is connected to the fifth wire (i5) of the fading control channel (111), and a further outlet of the flashing control channel (111) is provided by the tensile line (11L) of the fading control channel.