RU2037874C1 - Device for control of memory unit - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has two decoders, five bus shapers, five read-only memory unit, three counters, four registers, flip-flop, comparison circuit, seven AND gates, fourteen AND gates, two univibrators, four delay gates, multiplexer, information input- output, address input, input of information replacing mode, input of full reconfiguration mode, input of partial reconfiguration mode, instruction selection input, initial setting input, writing input, reading input, setting input for replaced information type, input for permission of change of replaced information address, group of registers, group of multiplexers, adder, NOT gate, NOR gate, reverse multiplexer, group of delay gates. EFFECT: decreased memory usage, increased speed. 2 dwg

Description

 The invention relates to computer technology and can be used in fault-tolerant computing systems.

 A device for calling interpreted programs is known, which contains two triggers, a memory device, a register, and two AND elements (V.I. Signals. On one approach to expanding single-chip microprocessor instruction systems. Control systems and machines, N 4, 1985, pp. 31-33) .

 The disadvantages of such a device are the narrow scope and class of tasks to be solved, since it can be used to interpret commands that are not in the command system of a given microprocessor, and cannot change interpretation modes during the operation of a microprocessor system, which is necessary in fault-tolerant systems.

 It is also known a device containing a decoder, four blocks of read-only memory, an address matrix, a storage matrix, an OR element, bus drivers, an inverter, a group of inverters (Shevkoplyas B.V. Microprocessor structures, M. Radio and communications, 1986, pp. 212-215 , fig. 10.7).

 The disadvantages of such a device are the narrow scope and class of tasks to be solved, since it only allows you to replace the wrong command codes with the correct ones (cell by cell) and is not able to provide the replacement of a failed command with equivalent sequences of commands of arbitrary length that do not contain codes of a failed command (and such the possibility due to the redundancy of the command system is almost always there).

 The closest in technical essence to the proposed is a memory management device containing a decoder, bus driver, three read-only memory blocks, two counters, two registers, a trigger, a comparison circuit, four OR elements, eight AND elements, a single-shot, delay element, multiplexer, and the outputs of all memory blocks, the bus driver, the information inputs of the first and second counters, the second register and the first information input of the multiplexer are connected to the information input-output of the device, info the input inputs of the first register, the decoder, the second information input of the multiplexer, the address inputs of the first and second memory blocks are connected to the address input of the device, the third input of the first OR element, the third input of the eighth element And and the fourth input of the sixth element And are connected to the input of the device command sample, third the input of the second OR element, the installation inputs to "0" of the first and second registers and the first counter are connected to the input of the initial installation of the device, the second input of the first OR element, the second inputs of the first, second o and the third element AND are connected to the recording input of the device, the first input of the first OR element is connected to the read input of the device, the output of the first OR element is connected to the enable input of the decoder, the second, third and fourth outputs of which are connected respectively to the first inputs of the first, second and third elements And, the first output of the decoder is connected to the access permission address of the second block of read-only memory, the output of the first element And to the synchronization input of the second register, the output of the second element And to the synchronization input of the counter, the fifth output of the decoder to the enable input of the bus driver, the sixth output of the decoder to the first inputs of the fourth and fifth elements And, the second input of the fourth element And and the inverse input of the fifth element And to the output of the trigger, the output of the fourth element And to the enable input of the third memory block , the output of the fifth element AND to the input of the resolution permission of the first memory block, the seventh output of the decoder to the first input of the second element OR, the eighth output of the decoder to the input of the “0” second counter, sync input cat Orogo is connected to the output of the third element And, the sixth output of the decoder to the first inputs of the sixth, seventh and eighth elements And, the second input of the sixth element And to the output of the third element OR, the third input of the sixth element And to the input of the partial reconfiguration mode of the device, the output of the sixth element And to the first input of the fourth element OR the second input of the seventh element And to the input of the mode of complete reconfiguration of the device, the output of the seventh element And to the second input of the fourth element OR, the second input of the eighth element And is connected to the input mode and replacing the information of the device, and the output to the third input of the fourth OR element, the output of which is connected to the gate input of the comparison circuit, the output of the comparison circuit is connected to the trigger inputs of the trigger and the first register, the output of which is connected to the information input of the bus driver, the output of the sign of the end of data reading of the third block memory to the input of the delay element, the output of which is connected to the input of the one-shot, the output of the single vibrator is connected to the second input of the second OR, the output of which is connected to the input setting to “0” a trigger, the information input of which is connected to the input of the logical “1” device, and the output is to the subtracting input of the second counter, the outputs of which are connected to the inputs of the third OR element, the second information input of the multiplexer is connected to the address input of the device, the address input of the multiplexer to the input of the job type of the replaced information of the device, the output of the multiplexer to the first information input of the comparison circuit, the second information input of which is connected to the output of the second register, the output of the first counter to the address the input of the third memory block, the access permission address of which is connected to the counting input of the first counter, the input of the resolution of which account is connected to the input of the permission to change the address of the replaced information of the device (ed. USSR N 1679489, class G 06 F 12/00, 1989).

 The disadvantage of the prototype is the large amounts of permanent memory necessary to organize the replacement of a failed command with the equivalent sequences of the remaining commands recorded in the second memory block, the time taken to complete these replacements is large, i.e. the performance of computing systems (AC) as a whole is reduced, which may make it impossible to use the known device in multiprocessor aircraft or in control aircraft operating in real time. The number of different teams involved in the software replacement of the failed team is also significant, which significantly reduces the possibility of using the prototype in fault-tolerant aircraft, since for multiple failures of the command system, equivalent replacement algorithms most often simply do not exist.

 The aim of the invention is to reduce memory and time spent on algorithmic reconfiguration.

; где k количество информационных участков в формате команды, используемых под операнды), информационный вход нулевого регистра группы и нулевые информационные входы мультиплексоров группы подключены соответственно к группе информационных выходов второго блока памяти (т.е. информационный вход нулевого регистра группы подключен к нулевому выходу группы, а нулевой информационный вход i-го мультиплексора группы подключен к i-му информационному выходу группы второго блока памяти), адресные входы мультиплексоров группы подключены к соответствующим выходам четвертого блока памяти, выходы мультиплексоров группы подключены к информационным входам соответствующих регистров группы (т. е. выход i-го мультиплексора группы подключен к информационному входу i-го регистра группы), выходы всех регистров группы подключены соответственно к группе информационных входов пятого шинного формирователя (т.е. выход нулевого регистра группы подключен к нулевому входу группы, а выход i-го регистра группы подключен к i-му входу группы информационных входов пятого шинного формирователя), первый выход первого дешифратора подключен к вторым входам шестого элемента ИЛИ и десятого элемента И, к входам синхронизации всех регистров группы и к первому входу тринадцатого элемента И, выход которого подключен к входу разрешения пятого шинного формирователя, выход признака окончания считывания данных второго блока памяти подключен к входу третьего элемента задержки, выход которого подключен к входу второго одновибратора, выход пятого элемента ИЛИ подключен к входу начальной установки третьего счетчика, к счетному входу которого подключен выход десятого элемента И, выход первого элемента И подключен к первому входу шестого элемента ИЛИ, выход которого подключен к входу четвертого элемента задержки, выход которого подключен к входу разрешения обращения четвертого блока памяти, к второму адресному входу которого подключен выход третьего счетчика, выход второго регистра подключен к первому адресному входу четвертого блока памяти и к информационному входу второго дешифратора, выход которого подключен к адресному входу пятого блока памяти, выход которого подключен к второму входу сумматора, к первому входу которого подключен выход первого регистра, выход сумматора подключен к информационному входу третьего регистра, синхронизирующий вход которого подключен к выходу второго элемента задержки, выход мультиплексора подключен также к входу группы элементов задержки, выход которых подключен к информационному входу демультиплексора.The goal is achieved by the fact that in the memory management device containing a decoder, bus driver, three read-only memory blocks, two counters, two registers, a trigger, a comparison circuit, four OR elements, eight AND elements, a one-shot, delay element, a multiplexer, the outputs of the third memory block, bus driver, information inputs of the first and second counters, the second register are connected to the information input-output of the device, the information inputs of the first register, decoder, the second information input multi lexor, the address inputs of the first and second memory blocks are connected to the address input of the device, the third input of the first OR element, the third input of the eighth element And and the fourth input of the sixth element And are connected to the sample input of the device command, the third input of the second OR element, the installation inputs to "0 "the first and second registers and the first counter are connected to the input of the initial installation of the device, the second input of the first OR element, the second inputs of the first, second and third elements AND are connected to the input of the device record, the first input of the first the OR element is connected to the read input of the device, the output of the first OR element is connected to the decoder enable input, the second, third and fourth outputs of which are connected respectively to the first inputs of the first, second and third AND elements, and the first decoder output is connected to the input of the second block constant access permission memory, the output of the first element And is connected to the synchronization input of the second register, the output of the second element And to the synchronization input of the first counter, the fifth output of the decoder to the input resolution bus form switch, the sixth decoder output to the first inputs of the fourth and fifth elements And, the second input of the fourth element And and the inverse input of the fifth element And to the output of the trigger, the output of the fourth element And to the permission input of the access of the third memory unit, the output of the fifth element And to the permission input of the first of the memory block, the seventh output of the decoder to the first input of the block of the second OR element, the eighth output of the decoder to the installation input at “0” of the second counter, the clock input of which is connected to the output of the third element AND, the sixth output of the decoder torus to the first inputs of the sixth, seventh and eighth elements AND, the second input of the sixth element AND to the output of the third OR element, the third input of the sixth element And to the input of the partial reconfiguration mode of the device, the output of the sixth element And is connected to the first input of the fourth element OR, the second input of the seventh element And to the input of the mode of complete reconfiguration of the device, the output of the seventh element And to the second input of the fourth element OR, the second input of the eighth element And is connected to the input of the replacement mode of the information of the device, and the output to the third one of the fourth OR elements, the output of which is connected to the gate input of the comparison circuit, the output of the comparison circuit is connected to the trigger inputs of the trigger and the first register, the output of which is connected to the information input of the bus driver, the output of the end of data reading of the third memory block is connected to the input of the delay element, the output of which connected to the input of a single vibrator, the output of a single vibrator is connected to the second input of the second OR element, the output of which is connected to the installation input in the "0" trigger, the information input to It is connected to the input of the logical "1" device, and the output is to the subtracting input of the second counter, the outputs of which are connected to the inputs of the third OR element, the address input of the multiplexer is connected to the input of the type of the replaced information of the device, the output of the multiplexer to the first information input of the comparison, the second information input which is connected to the output of the second register, the output of the first counter to the address input of the third memory block, the input of the access permit which is connected to the counting input of the first counter, the input is bit To solve the problem, which is connected to the permission input for changing the address of the replaced information of the device, a counter, two registers, a group of registers, a group of multiplexers, an adder, a NOT element, two read-only memory blocks, four bus shapers, a single vibrator, an OR-NOT element, three OR elements, are entered, a demultiplexer, a group of delay elements, three delay elements, a decoder, six AND elements, and the input of the information replacement mode is connected to the first input of the OR-NOT element, the second input of which and the first input of the ninth element AND connect are accessed to the input of the partial reconfiguration mode, the inverse input of the ninth AND element is connected to the output of the third OR element, the output of the OR-NOT element is connected to the first input of the seventh OR element, the second input of which is connected to the output of the ninth AND element, the output of the seventh OR element is connected to the input of the element NOT to the resolution input of the second bus driver, the information input of which and the first input of the multiplexer are connected to the output of the first memory block, the output of the element is NOT connected to the first inputs of the tenth and twelfth element Comrade And and to the permission input of the second decoder, the input of the complete reconfiguration mode of the device is connected to the third inverse input of the eleventh element And and the first inverse input of the fourteenth element And, the second input of which, the second inverse inputs of the twelfth, thirteenth elements And and the second input of the fifth OR element are connected to the output of the second one-shot, the output of the fourteenth element And is connected to the enable input of the third bus driver, the information input of which is connected to the output of the third register, the output the third bus driver is connected to the address input of the first memory block, the outputs of the second, fourth and fifth bus drivers are connected to the information input-output of the device, the output of the twelfth element is connected to the resolution input of the fourth bus driver, the information input of which is connected to the first output of the demultiplexer, the second output which is connected to the information input of the fourth register, the installation inputs to "0" of the third and fourth registers and the first input of the fifth element OR are connected to the input of the initial installation of the device, the input of the type of the replaced information of the device is connected to the second inverse input of the eleventh element And, the first input of which is the access enable address of the fifth memory block, the input of the second delay element and the address input of the demultiplexer are connected to the output of the comparison circuit, the output of the eleventh element And is connected to the fourth synchronization input, the outputs of which are connected to the corresponding information inputs of all the multiplexers of the group (i.e. the i-th output of the fourth register is connected to the i-th information inputs of all multiplexers of the group, i =

; where k is the number of information sections in the command format used for operands), the information input of the group zero register and the zero information inputs of the group multiplexers are connected respectively to the group of information outputs of the second memory block (i.e. the information input of the group zero register is connected to the group zero output, and the zero information input of the i-th group multiplexer is connected to the i-th information output of the group of the second memory block), the address inputs of the group multiplexers are connected to the corresponding the corresponding outputs of the fourth memory block, the outputs of the group multiplexers are connected to the information inputs of the corresponding group registers (i.e., the output of the i-th group multiplexer is connected to the information input of the i-group register), the outputs of all the group registers are connected respectively to the group of information inputs of the fifth bus driver (i.e., the output of the group's zero register is connected to the group zero input, and the output of the i-group register is connected to the i-th input of the group of information inputs of the fifth bus driver), the first the course of the first decoder is connected to the second inputs of the sixth OR element and the tenth element AND, to the synchronization inputs of all the registers of the group and to the first input of the thirteenth element AND, the output of which is connected to the resolution input of the fifth bus driver, the output of the end of the data reading of the second memory block is connected to the input the third delay element, the output of which is connected to the input of the second one-shot, the output of the fifth OR element is connected to the input of the initial installation of the third counter, to the counting input of which n is the output of the tenth element AND, the output of the first element AND is connected to the first input of the sixth element OR, the output of which is connected to the input of the fourth delay element, the output of which is connected to the input of the circulation resolution of the fourth memory block, the second address of which is connected to the output of the third counter, the output of the second the register is connected to the first address input of the fourth memory block and to the information input of the second decoder, the output of which is connected to the address input of the fifth memory block, the output of which is connected to the second th input of the adder, the first input of which is connected to the output of the first register, the output of the adder is connected to the data input of the third register, a clock input terminal coupled to the output of the second delay element, the output is also connected to an input of the group delay elements multiplexer whose output is connected to the data input of the demultiplexer.

 The essence of the invention is to reduce the amount of memory and time spent on algorithmic reconfiguration by introducing an algorithmic reconfiguration mode by template. The essence of the new mode introduced is to configure the device to analyze command codes read from the first block of read-only memory that are found to be malfunctioning as a result of an external processor self-test; in the exception of reading to the external processor a faulty command from the first memory block as a result of the output of the second bus driver being in a high impedance state under conditions of failure detection such as incorrect execution of individual commands and in the organization of reading in this case serviceable commands to the external processor from the first memory block through the first multiplexer, demultiplexer and fourth bus driver; in the installation of the trigger when it detects the code of this command on the information input / output, which blocks the first block of read-only memory and connects the third block of read-only memory; in a record in the first register of the address at which the reconfiguration of the command occurred, and in the fourth register of the failed command itself; in reading from the third block of read-only memory of the corresponding unconditional jump instruction, which is executed by an external processor, the address of the required instruction being determined by the setting; resetting the trigger at the end of the external processor reading the unconditional jump command in order to restore the ability to read operands from the first block of read-only memory; in the reading in the algorithmic reconfiguration mode from the second memory block of the program template (consisting of templates of separate instructions) of the equivalent replacement of the failed command and the synthesis on its basis (using the contents of the fourth register) of the desired equivalent replacement program executed by an external processor; in controlling at each step of this synthesis a group of multiplexers in accordance with the control codes of the fourth memory block to form the next program command equivalent to replace the failed command; in calculating in the adder the advanced address of the failed command (i.e., the address at which reading from the first block of read-only memory will continue after the equivalent replacement is completed) and in issuing it after completion of the equivalent replacement of the failed command in the algorithmic reconfiguration mode with the address input of the first memory block .

 The invention is implemented by the following set of design features of new elements and relationships that determine the compliance of the claimed technical solution to the criterion of "novelty."

 The introduction of the third counter and its corresponding connections allows the fourth block of memory to be addressed in the mode of algorithmic reconfiguration according to the pattern in order to select the templates of the program commands for the equivalent replacement of the failed command.

 The introduction of the third register and the relations corresponding to it allows, in the newly introduced mode, to store the advanced address of the failed command and issue it to the address input of the first memory block to continue working on the main program.

 The introduction of the fourth register and its corresponding relationships allows the storage of a failed team and the use of its information sections to fill in command templates in the newly introduced mode.

 The introduction of a group of registers and their corresponding relationships allows the storage of equivalent replacement program instructions at each synthesis step, as well as their output to an external processor through the fifth bus driver, in the newly introduced mode.

 The introduction of a group of multiplexers and their corresponding connections allows filling in templates of program commands for an equivalent replacement of the failed command with the necessary information sections on the basis of switching their information inputs in accordance with control codes from the fourth memory block in the newly introduced mode.

 The introduction of the adder and its associated relationships allows us to calculate the advanced address based on the address of the failed command in the newly entered mode.

 The introduction of the element NOT and the corresponding relationships allows you to control the twelfth element And and the control input of the second decoder in the event of failure detection such as incorrect execution of individual commands.

 The introduction of the fourth memory block and its corresponding connections allows, in accordance with the code of the failed command and the value of the third counter, to control the group of multiplexers in the newly introduced mode in order to fill the template with the necessary information sections of the failed command.

 The introduction of the fifth memory block and its corresponding relationships allows the adder in the newly introduced mode to calculate the advanced address by issuing it as the second term the necessary constant.

 The introduction of the second bus driver and its associated connections eliminates the reading of faulty commands into the external processor when a failure such as incorrect execution of individual commands is detected.

 The introduction of the third bus driver and its associated connections allows, in the newly introduced mode, at the end of the equivalent replacement, the first block of permanent memory to be addressed with a moved address in order to return to the main program.

 The introduction of the fourth bus driver and its corresponding connections allows us to read serviceable commands into the external processor from the first memory unit in the new introduced mode under conditions of failure detection such as incorrect execution of individual commands.

 The introduction of the fifth bus driver and its associated connections allows us to read the equivalent replacement program of the failed command synthesized on the basis of the template into the external processor using the necessary information from the failed command.

 The introduction of the second one-shot and the corresponding connections allows you to control the third bus driver in the newly introduced mode to issue an advanced address to the first input memory block and reset the third counter after the equivalent replacement of the failed command is completed.

 The introduction of the OR-NOT element and the corresponding relationships allows you to control the seventh OR element in all operating modes, except for settings.

 The introduction of the fifth OR element and its corresponding connections allows you to reset the third counter both after applying power to the device, and when implementing a new mode entered.

 The introduction of the sixth OR element and its corresponding relationships allows you to control the fourth memory block to ensure that they issue to the address inputs of the group of control code multiplexers in order to organize a new mode entered.

 The introduction of the seventh OR element and its corresponding connections allows you to control the second bus driver in order to exclude the reading of the faulty command from the first memory block to the external processor under conditions of failure detection such as incorrect execution of individual commands.

 The introduction of a demultiplexer and its corresponding connections allows, under conditions of failure detection such as improper execution of individual commands, to ensure the issuance of serviceable commands from the first memory block to the fourth bus driver, as well as the recording of the faulty command in the fourth register.

 The introduction of a group of delay elements and their corresponding connections allows to output information from the multiplexer output to the information input of the demultiplexer with a delay sufficient to trigger the comparison circuit when reading a faulty command from the first memory and switching unit (in connection with this) of the demultiplexer under conditions of failure detection such as incorrect execution individual teams.

 The introduction of the second delay element and its associated relationships allows you to control the entry in the third register of the advanced address of the failed command (used in the newly entered mode) after the adder completes the calculations under conditions of failure detection such as the incorrect execution of individual commands.

 The introduction of the third delay element and its associated connections allows you to control the second one-shot after reliable reading from the second memory block of the entire template and completion of the synthesis device program equivalent to replace the failed command in the new mode entered.

 The introduction of the fourth delay element and its associated connections allows you to control the fourth memory block to issue the next control codes to the address inputs of the multiplexer group after the third counter has been reliably activated in the newly introduced mode.

 The introduction of the second decoder and its corresponding connections allows, in accordance with the code of the faulty command, to address the fifth memory block under conditions of failure detection such as incorrect execution of individual commands. Without this decoder, a block would have to use the number of cells equal to the number of possible commands.

 The introduction of the ninth AND element and its corresponding relationships allows you to control the seventh OR element in the partial algorithmic reconfiguration mode.

 The introduction of the tenth element And and the corresponding connections allows you to control the counting input of the third counter in the newly entered mode.

 The introduction of the eleventh element And and its corresponding relationships allows controlling the fourth register to ensure recording of the faulty command from the demultiplexer in the newly introduced mode.

 The introduction of the twelfth element And and its associated connections allows you to control the fourth bus driver to ensure that a good command is read into the external processor under conditions of failure detection such as incorrect execution of individual commands.

 The introduction of the thirteenth And element and its corresponding connections allows you to control the fifth bus driver to provide step-by-step reading into the external processor from the group of command registers of the equivalent replacement program synthesized in the new introduced mode.

 The introduction of the fourteenth And element and its corresponding connections allows controlling the third bus driver to provide, in the newly introduced reading mode, an advanced address after the synthesis of an equivalent replacement program is completed on the address input of the first permanent memory block.

 The introduction of the element NOT and the corresponding relationships allows you to control the tenth and twelfth elements And and the second decoder in the event of failure detection such as the incorrect execution of individual commands.

 The introduction of new connections for the first memory block allows, under conditions of failure detection such as incorrect execution of individual commands, to exclude the reading of a faulty command in an external processor, and also provides automatic return to the main program after completion of the equivalent replacement of a failed command.

 The introduction of new connections for the second memory block allows us to provide the new introduced mode with the necessary program templates for equivalent replacements of failed commands, as well as to control the third delay element at the end of the template reading.

 The introduction of new relationships for the first register allows you to use the address of the failed command to calculate in the adder the advanced address used at the end of the newly entered mode.

 The introduction of new relationships for the second register allows addressing the sixth memory block in the newly introduced mode in order to select the appropriate set of control codes and control the second decoder.

 The introduction of new relationships for the comparison circuit allows you to control the fifth memory unit, the second delay element, the eleventh AND element, and the demultiplexer in the newly introduced mode.

 The introduction of new relationships for the third OR element allows you to control the ninth AND element in the partial algorithmic reconfiguration mode.

 The introduction of new connections for the multiplexer allows you to organize the issuance of all information from the first memory block to the input of a group of delay elements in the event of failure detection such as incorrect execution of individual commands.

 Thus, the proposed technical solution meets the criterion of "inventive step", since in the known analogue and prototype devices under conditions of failure detection such as incorrect execution of individual commands when replacing a failed command with equivalent sequences from the remaining ones, a reduction in memory and time spent on execution is not achieved algorithmic reconfiguration due to the lack of the above set of design features.

 When using the proposed device, the objective of the invention is achieved, which consists in reducing the amount of memory and time spent on performing the algorithmic reconfiguration mode, thereby expanding the possibilities of using the proposed device in fault-tolerant aircraft.

 Figure 1 shows a functional diagram of the proposed device memory management; figure 2 is a timing diagram of its operation in the mode of algorithmic reconfiguration according to the template.

 The memory management device contains a first decoder 1, containing outputs 1.0-1.7, a first bus former 2, three blocks 3-5 of permanent memory, the first counter 6, two registers 7, 8, trigger 9, a comparison circuit 10, four elements OR 11-14 , eight elements And 15-22, the first one-shot 23, the first delay element 24, multiplexer 25, the second counter 26, the information input-output 27, the address input 28, the input 29 information replacement mode, the input 30 full reconfiguration mode, the input 31 partial mode reconfiguration, input 32 command fetch, input 33 initial setup and recording input 34, input 35 read input 36 displaceable job type information input 37 permits a change of address information of the replaced device, the third counter 38, two registers 39, 40, 41.0-41.k group of registers, multiplexers 42.1-42 group. k, adder 43, element NOT 44, two blocks 45, 46 of permanent memory, four bus drivers 47-50, second one-shot 51, element OR NOT 52, three elements OR 53-55, demultiplexer 56, group of delay elements 57, three delay element 58-60, second decoder 61, six elements And 62-67.

, где k количество информационных участков в формате команды, используемых под операнды). Информационный вход нулевого регистра 41.0 группы и нулевые информационные входы мультиплексоров 41.1-42. k группы подключены соответственно к группе информационных выходов второго блока 4 памяти (т. е. информационный вход нулевого регистра 41.0 группы подключен к нулевому выходу группы, а нулевой информационный вход i-го мультиплексора 41. i группы подключен к i-му информационному выходу группы второго блока 4 памяти). Адресные входы мультиплексоров 42.1-42.k группы подключены к соответствующим выходам четвертого блока 46 памяти, выходы мультиплексоров 42.1-42.k группы подключены к информационным входам соответствующих регистров 41.1-41.k группы (т.е. выход i-го мультиплексора 42.1-42. k группы подключен к информационному входу i-го регистра 41.1-41.k группы). Выходы всех регистров 41.0-41.k группы подключены соответственно к группе информационных входов пятого шинного формирователя 50 (т.е. выход нулевого регистра 41.0 группы подключен к нулевому входу группы, а выход i-го регистра 41.1 группы подключен к i-му входу группы информационных входов пятого шинного формирователя 50). Первый выход 1.0 первого дешифратора 1 подключен к входу разрешения обращения второго блока 4 памяти, к вторым входам шестого 54 и десятого 63 элементов И, к входам синхронизации всех регистров 41.0-41.k группы и к первому входу тринадцатого элемента И 66, выход которого подключен к входу разрешения пятого шинного формирователя 50. Выход признака окончания считывания данных второго блока 4 памяти подключен к входу третьего элемента 59 задержки, выход которого подключен к входу второго одновибратора 51. Выход пятого элемента ИЛИ 53 подключен к входу начальной установки третьего счетчика 38, к счетному входу которого подключен выход десятого элемента И 63. Выход шестого элемента ИЛИ 54 подключен к входу четвертого элемента 60 задержки, выход которого подключен к входу разрешения обращения четвертого блока 46 памяти, к второму адресному входу которого подключен выход третьего счетчика 38. Выход второго регистра 7 подключен к первому адресному входу четвертого блока 46 памяти и к информационному входу второго дешифратора 61, выход которого подключен к адресному входу пятого блока 45 памяти. Выход блока 45 подключен к второму входу сумматора 43, к первому входу которого подключен выход первого регистра 8. Выход сумматора 43 подключен к информационному входу третьего регистра 39, синхронизирующий вход которого подключен к выходу второго элемента 58 задержки. Выход мультиплексора 25 подключен также к входу группы элементов 57 задержки, выход которых подключен к информационному входу демультиплексора 56.The outputs of the third memory block 5, the first 2, second 47, fourth 49 and fifth 50 bus drivers, the information inputs of the first 6 and second 26 counters, the second register 7 are connected to the information input-output 27 of the device, the output of the third bus driver 48 is connected to the address input first block 3 of the memory. The information inputs of the first register 8, decoder 1, the second information input D _{1 of the} multiplexer 25, the address inputs of the first 3 and second 4 memory blocks are connected to the address input 28 of the device. The third input of the first element OR 14, the third input of the eighth element And 22 and the fourth input of the sixth element And 20 are connected to the input 32 of the sample command device. The third input of the second element OR 13, the first input of the fifth element OR 53, the installation inputs to "0" registers 7, 8, 39, 40 and the first counter 6 are connected to the input 33 of the initial installation of the device. The second input of the first element OR 14, the second inputs of the first 15, second 16 and third 17 elements AND are connected to the input 34 of the recording device. The first input of the first element OR 14 is connected to the input 35 of the reading device, the output of the first element OR 14 is connected to the enable input of the decoder 1, second 1.1, third 1.2 and fourth 1.3 whose outputs are connected respectively to the first inputs of the first 15, second 16 and third 17 AND elements The output of the first element And 15 is connected to the synchronization input of the second register 7 and to the first input of the sixth element OR 54, the output of the second And 16 element is connected to the synchronization input of the first counter 6, the fifth output 1.4 of the decoder 1 to the resolution input of the first bus 2, the sixth output 1.5 of the decoder 1 to the first inputs of the fourth 18 and fifth 19 elements And and to the first inputs of the sixth 20, seventh 21 and eighth 22 elements I. The second input of the fourth element And 18 and the inverse input of the fifth element And 19 are connected to the trigger output 9, the output of the fourth element And 18 to the input of the permission of the appeal of the third memory block 5, the output of the fifth element And 19 to the input of the permission of the appeal of the first memory block 3, the seventh output 1.6 of the decoder 1 to the first input of the second element OR 13, the eighth output 1.7 of the decoder 1 to the input setting to "0" the second counter 26, the clock input of which is connected to the output of the third element And 17. The second input of the sixth element And 20 is connected to the output of the third element OR 11, the third input of the sixth element And 20 to the input 31 of the partial reconfiguration mode of the device, the output of the sixth element And 20 to the first input the fourth element OR 12, the second input of the seventh element And 21 to the input 30 of the mode of complete reconfiguration of the device, the output of the seventh element And 21 to the second input of the fourth element OR 12, the second input of the eighth element AND 22 to the input 29 of the mode of replacing information roystva and output to the third input of the fourth OR gate 12, whose output is connected to a strobe input of the comparison circuit 10. The output of the comparison circuit is connected to the first input of the eleventh element And 64, the access enable address of the fifth memory unit 45, the input of the second delay element 58, as well as to the sync inputs of the trigger 9 and the first register 8. The output of the end of data reading of the third memory unit 5 is connected to the input of the first delay element 24, the output of which is connected to the input of the first one-shot 23. The output of the one-shot 23 is connected to the second input of the second OR 13 element, the output of which is connected to the setting input in trigger "0" 9. The information input after it is connected to the input of the logical "1" device, and the output to the subtracting input of the second counter 26, the outputs of which are connected to the inputs of the third element OR 11. The second information input of the multiplexer 25 is connected to the address input 28 of the device, the address input of the multiplexer 25 to the input 36 of the job type replaced information of the device, the output of the multiplexer 25 to the first information input D _o comparison circuit 10, the second information input of which is connected to the output of the second register 7. The output of the first counter 6 is connected to the address input of the third about the memory block 5, the access permission address of which is connected to the counting input of the first counter 6. The counter resolution input of the counter 6 is connected to the input 37 of the address change permission address of the replaced information of the device, the information substitution mode input 29 is connected to the first input of the OR-NOT 52 element, the second input which and the first input of the ninth element And 62 are connected to the input 31 of the partial reconfiguration mode. The inverse input of the ninth element AND 62 is connected to the output of the third element OR 11, the output of the element OR NOT 52 is connected to the first input of the seventh element OR 55, the second input of which is connected to the output of the ninth element AND 62. The output of the seventh element OR 55 is connected to the input of the element NOT 44 and to the resolution input of the second bus driver 47, the information input of which and the first input of multiplexer 25 are connected to the output of the first memory unit 3. The output of the element NOT 44 is connected to the first inputs of the tenth 63 and the twelfth 65 of the And elements and to the resolution input of the second decoder 61. The input 30 of the mode of complete reconfiguration of the device is connected to the third inverse input of the eleventh element And 64 and to the first inverse input of the fourteenth element And 67, the second input which, the second inverse inputs of the twelfth 65, thirteenth 66 AND elements and the second input of the fifth OR element 53 are connected to the output of the second one-shot 51. The output of the fourteenth AND 67 element is connected to the resolution input of the third a former driver 48, the information input of which is connected to the output of the third register 39. The output of the third bus driver is connected to the address input of the first memory unit 3. The outputs of the second 47, fourth 49 and fifth 50 bus drivers are connected to the information input-output 27 of the device. The output of the twelfth element And 65 is connected to the resolution input of the fourth bus driver 49, the information input of which is connected to the first output of the demultiplexer 56. The second output of the latter is connected to the information input of the fourth register 40. The input 36 for setting the type of replaced information of the device is connected to the second inverse input of the eleventh element And 64, the output of which is connected to the synchronization input of the fourth register 40. The outputs of the register 40 are connected to the corresponding information inputs of all multiplexers 42.1-42. k groups (i.e., the i-th output of the fourth register 40 is connected to the i-th information inputs of all multiplexers 42.1-42. k groups, i =

, where k is the number of information sections in command format used for operands). The information input of the zero register 41.0 groups and zero information inputs of the multiplexers 41.1-42. k groups are connected respectively to the group of information outputs of the second memory block 4 (i.e., the information input of group zero register 41.0 is connected to the group zero output, and the information input of the i-th multiplexer 41 is zero. group i is connected to the i-th information output of the second group block 4 memory). The address inputs of the group multiplexers 42.1-42.k are connected to the corresponding outputs of the fourth memory block 46, the outputs of the group multiplexers 42.1-42.k are connected to the information inputs of the corresponding registers 41.1-41.k of the group (i.e., the output of the i-th multiplexer 42.1- 42. k groups are connected to the information input of the i-th register 41.1-41.k of the group). The outputs of all the registers 41.0-41.k of the group are connected respectively to the group of information inputs of the fifth bus driver 50 (i.e., the output of the group zero register 41.0 is connected to the group zero input, and the output of the i-group register 41.1 is connected to the i-th group input information inputs of the fifth bus driver 50). The first output 1.0 of the first decoder 1 is connected to the access enable address of the second memory unit 4, to the second inputs of the sixth 54 and tenth 63 AND elements, to the synchronization inputs of all registers 41.0-41.k of the group and to the first input of the thirteenth AND 66 element, the output of which is connected to the resolution input of the fifth bus driver 50. The output of the end of data reading of the second memory unit 4 is connected to the input of the third delay element 59, the output of which is connected to the input of the second one-shot 51. The output of the fifth OR 53 is connected to the input of the installation of the third counter 38, to the counting input of which the output of the tenth element And 63 is connected. The output of the sixth element OR 54 is connected to the input of the fourth delay element 60, the output of which is connected to the access permission input of the fourth memory unit 46, to the second address input of which the output of the third counter 38. The output of the second register 7 is connected to the first address input of the fourth memory block 46 and to the information input of the second decoder 61, the output of which is connected to the address input of the fifth memory block 45. The output of block 45 is connected to the second input of the adder 43, the first input of which is connected to the output of the first register 8. The output of the adder 43 is connected to the information input of the third register 39, the clock input of which is connected to the output of the second delay element 58. The output of the multiplexer 25 is also connected to the input of the group of delay elements 57, the output of which is connected to the information input of the demultiplexer 56.

 Decoder 1 is designed to control 6 memory blocks 3, 4, 5, 46, bus drivers 2, 50, registers 7, 8, group of registers 41.0-41.k and counters 6, 26, 38. Decoder 1 decodes the address set on the address inputs 28 in the event that the output of the OR element 14 is activated, exciting the enable input of the decoder 1. If the inputs of the counter 28 are set to addresses 6, registers 7, 8, then the corresponding outputs 1.1, 1.2, 1.3 of the decoder are excited. If the address of the bus driver 2 is set at the inputs 28, then the output 1.4 of the decoder 1 is excited. If the addresses of the memory cells of unit 3 are set at the inputs 28, the output 1.5 of the decoder 1 is excited. If the addresses of the memory cells 4 are set at inputs 28, the output 1.0 the decoder 1. To control the zeroing of the trigger 9 and the counter 26 at the inputs must be installed addresses that excite the corresponding outputs 1.6, 1.7 of the decoder 1. The decoder can be implemented, for example, on standard integrated circuits 155IDZ.

 The bus driver 2 is designed to buffer the outputs of the register 8. The external processor refers to the bus driver 2 as a memory location with a fixed address, the output 1.4 of the decoder 1 is excited (it doesn’t matter in the write or read mode) and the information from the outputs of the register 8 is input output 27 and then to an external processor. Otherwise, the output of the bus driver 2 is in a high-paced state and does not affect the transmission of information at the input-output 27. The bus driver 2 can be implemented, for example, on standard integrated circuits 589АП16.

 Block 3 of permanent memory is designed to store the main programs of the external processor, composed of a complete list of its commands in machine language. Commands and data in accordance with the addresses of the cells at input 28 are read from block 3 to input-output 27 via a bus driver 47 or (in the event of a type failure detection incorrect execution of individual commands) through a multiplexer 25, a demultiplexer 56 and a bus driver 49 with a delay determined by a group of delay elements 57, wherein the permission input is activated by the output of element And 19. Otherwise, the output of block 3 is in a high impedance state and does not affect the transmission of information at input-output 27. Block 3 of read-only memory m Jet be implemented, for example, standard integrated circuits 556RT5, buffered bus formers 589AP16 of inputs.

 Unit 4 of permanent memory is intended for storing the algorithmic equivalent patterns of instructions of an external processor, composed of truncated conditions of a complete system of instructions as a result of failures. Access to block 4 occurs when the output 1.0 of decoder 1 is excited. Block 4 of read-only memory is implemented similarly to block 3.

 Block 5 of permanent memory is intended for storing information that needs to be replaced with information in block 3, or of unconditional jump commands (set by counter 6) with algorithmic equivalent patterns. When the last word of the unconditional jump command is selected, a separate output of block 5 is activated. If the resolution enable input of block 5 is not activated, its output is in a high impedance state and does not affect the transmission of information via input-output 27. The permanent memory block 5 is also implemented similarly to block 3. The external synchronization frequency the processor is such that the recording of information from block 3 through the elements of the proposed device on the data bus to the internal registers of the processor occurs after the possible trigger 9 and switching to reading information from block 5, i.e. the processor "will not notice" the substitution of a faulty command located in block 3, with an unconditional jump command located in block 5.

 The counter 6 is designed to store the address code of the information recorded in block 5. This code is recorded from the input-output 27 by the pulse at the output of the element And 16. The state of the counter 6 is changed by the trailing edge of the pulse at the output of the element And 18 to provide addressing of the transition command, consisting of a few words. The counter 6 can be implemented, for example, on standard integrated circuits 155IE7. To implement the control of the counting input at input 37, an AND element is required that is connected by the output to the counting input.

 Register 7 is used to store the address code or command code, on which either information is replaced with information from block 5, or the algorithm is reconfigured according to the template from block 4. The stored command code addresses block 46 (the corresponding equivalent replacement program template is selected), and through the decoder 61, the addressing of block 45 (a constant is selected to calculate the advanced address). Information in the register 7 is recorded from the input-output 27 by the pulse at the output of the element And 15.

 Register 8 is designed to store the address at which the algorithmic reconfiguration or replacement of information that is recorded from the input 28 on the leading edge of the pulse at the output of the comparison circuit 10 takes place. Registers 7, 8 can be implemented, for example, on standard integrated circuits 155IR13.

 The trigger 9 is designed to control the counter 26 and the elements And 18, 19. The trigger can be zeroed by the signal from the output of the element OR 13, and is set by the leading edge of the pulse at the output of the comparison circuit 10, since the logical 1 signal is applied to the information input of the trigger. The excited output of the trigger 9 blocks the element I19. The trigger can be implemented, for example, on standard integrated circuits 155TM2.

 Comparison circuit 10 is intended to compare information at the output of multiplexer 25 and register 7 for controlling a trigger 9, register 8, AND element 64, memory unit 45, demultiplexer 56, and delay element 58. The comparison circuit 10 is gated by the output of the OR element 12. It can be implemented, for example, on standard integrated circuits 553SP1.

 The OR element 11 is designed to control the AND element 20 and block the AND element 62. Its output is activated if the code recorded in the counter 26 is nonzero.

 The OR element 12 is intended to control the synchronization input of the comparison circuit 10 in the event that at the outputs of at least one of the I20, 21, 22 elements there is a logical "1".

 The OR element 13 is designed to reset the trigger 9 either by the initial reset signal from the input 33, or by the output of the one-shot 23, or by the output 1.6 of the decoder 1.

 The OR element 14 is designed to control the decoder 1 in the event that one of the control signals 35 read, 34 write, 32 sample command is activated. In this case, the decoder 1 decrypts the address at the input 28.

 Element And 15 is designed to generate a pulse of recording information in the register 7 and control through the element OR 54 by the delay element 60 if the output 1.1 of the decoder 1 and the input 34 of the record are excited.

 Element And 16 is designed to control the recording of information in the counter 6 in the event that the output 1.2 of the decoder 1 and the input 34 of the record is excited.

 Element And 17 is designed to control the recording of information in the counter 26 in the event that the output 1.3 of the decoder 1 and the input 34 of the record is excited.

 Element And 18 is designed to control the enable input of block 5 and the counting input of counter 6 if output 1.5 of decoder 1 is excited and trigger 9 is installed.

 Element And 19 is intended to control the input of the resolution of block 3 in the event that the output 1.5 of the decoder 1 is excited and trigger 9 is not installed.

 The AND element 20 is designed to control the OR element 12 in the event that the output 1.5 of the decoder 1, the output of the OR element 11, the input 31 of the partial reconfiguration mode, and the input 32 of the sample command are excited.

 Element And 21 is designed to control the element OR 12 in the event that the output 1.5 of the decoder 1 and the input 30 of the full reconfiguration mode are excited.

 The AND element 22 is intended to control the OR element 12 in the event that the output 1.5 of the decoder 1, the input 29 of the information substitution mode and the input 32 of the sample command are excited.

 The one-shot 23 is designed to generate a reset pulse of trigger 9 at the end of a sample from block 5 of the unconditional transition command to the algorithmic equivalent patterns of block 4 or to replaceable information. The one-shot 23 can be implemented, for example, on standard integrated circuits 155AG1.

 The delay element 24 is designed to delay the control signal of a single-shot 23 from a separate output of block 5 for a period of time necessary for reliable reading of information from block 5 into an external processor.

The multiplexer 25 is designed to connect to the input of the D _o circuit 10 comparing either the output of block 3 or the address input 28, depending on the value of the signal at input 36 of the type of information to be replaced (if the input is logical "1", address input 28 is connected). The multiplexer 25 also provides information to the input of a group of delay elements 57. It can be implemented, for example, on standard integrated circuits 155KP1.

 The counter 26 is designed to control the element OR 11 by subtracting a unit from the number recorded in it during configuration, whenever trigger 9 is reset, which is necessary to set the required number of algorithmic reconfigurations. Information is recorded in the counter 26 from the input-output 27 by the signal at the output of the element And 17. The counter 26 is reset when the output 1.7 of the decoder 1 is excited. The counter can be implemented, for example, on standard integrated circuits 155IE7.

 Information input-output 27 is designed to connect the data bus of an external processor. The external processor reads data and commands from input-output 27 using its own clock signals, the repetition rate of which is such that information is recorded in its internal registers with a delay that takes into account the possible operation of trigger 9 and switching of memory blocks 3 and 5. Therefore, the external processor "will not notice" the substitution of information.

 Address input 28 is used to connect the address bus of an external processor.

 The input 29 of the information substitution mode is intended to transfer the output of the bus driver 47 to a high impedance state and to control the And 22 element, where it is used to set the algorithmic reconfiguration mode by command code, or when changing by command code when input 32 is activated.

 The input 30 of the full reconfiguration mode is intended to block the And 64, 67 elements, as well as to control the And 21 element either to set the algorithmic reconfiguration mode, or when replacing information both by the command or operand code and by the address.

 The partial reconfiguration mode input 31 is designed to control the And 20 element, to set the partial algorithmic reconfiguration mode, and also to switch the output of the bus driver 47 to a high impedance state or activate it when a logical "0" appears at the output of the OR 11. Inputs 29, 30 , 31 are excited unitarily: in each of the possible modes, only one of them is excited.

 The input 32 of the sample command is intended to signal the cycle of the sample command of the external processor. It is connected to the corresponding discharge of the processor control bus (for example, for the 580IK80 processor it is a conjunction of bits 5, 7 of the status word register).

 The input 33 of the initial installation is designed to reset the trigger 9 registers 7, 8, 39, 40 and counters 6, 38. It can be connected to the category "Initial reset" of the processor control bus.

 Record input 34 is intended for connecting a write bit to a memory cell of a control bus of an external processor. The read input 35 is for connecting a read bit of a memory cell of a control bus of an external processor.

 The input 36 of the job type of the replaced information is intended to control the multiplexer 25, as well as to block the element And 64. If the input 36 is not excited, the input-output 27 is connected to the inputs of the multiplexer 25.

 The input 37 of the permission to change the address of the replaced information of the device is intended to block the counting input of the counter 6 if there is no need to change its state (fixed replacement of information by address or code), in which case the input 37 is reset.

 The counter 38 is designed to address the memory block 46 in the mode of algorithmic reconfiguration according to the pattern. Another increase in the contents of the counter is carried out by the trailing edge of the signal from the output of the AND element 63, and zeroing is done by the signal from the output of the OR element 53. The counter 38 can be implemented, for example, on standard integrated circuits 155IE7.

 Register 39 is designed to store the advanced address of the failed command recorded from the output of the adder 43 according to the signal from the output of the delay element 58.

Register 40 is designed to store the contents of a failed command for which the pattern-based algorithmic reconfiguration mode is executed. Information in the register 40 is recorded from the output D _{1 of the} demultiplexer 56 along the leading edge of the signal from the output of the And 64 element. Registers 39, 40 can be implemented, for example, on standard integrated circuits 155IR13.

 The group of registers 41.0-41.k is intended for storing received commands at each step of the synthesis of the program for equivalent replacing a failed command in the mode of algorithmic reconfiguration according to the template. Information in the group of registers 41.0-41.k is recorded on the leading edge of the signal from the output 1.0 of the decoder 1. In this case, at each synthesis step, the code for the next command (first bits of the corresponding command pattern) from block 4 is written to registers 41.1-41 .k, respectively, information sections of the synthesized command from the outputs of multiplexers 42.1-42.k. The group of registers 41.1-41.k can be implemented, for example, on standard integrated circuits 155IR13.

. Группа мультиплексоров 42.1-42.k может быть реализована, например, на стандартных интегральных микросхемах 155КП1.The group of multiplexers 42.1-42.k is designed to connect to the information inputs of the group of registers 41.1-41.k either the corresponding outputs 1-k of block 4 (not shown in Fig. 1) or the corresponding outputs 1-k of register 40, depending on the control code at the outputs 1-k of block 46 (and the address input of the i-th group multiplexer is connected to the i-th output of block 46, i =

. The multiplexer group 42.1-42.k can be implemented, for example, on standard integrated circuits 155KP1.

The adder 43 is designed to calculate the advanced address of the failed command (the address of the failed command to the input D _{o of the} adder comes from register 8), for which the mode of algorithmic reconfiguration by template is performed by increasing the contents of register 8 by the value of the constant supplied to the input D _{1 of the} adder from the block 45. The adder 43 may be implemented, for example, on standard integrated circuits 155IM1.

 Element NOT 44 is intended to control the enable input of the decoder 61 and the first inputs of AND 63, 65 elements if the output of OR 55 is not activated.

Block 45 of constant memory is designed to store the constants necessary to calculate the advanced address of the failed commands. The number of stored constants is determined by the number (in a given aircraft) of various formats of commands. The choice of the necessary constant depends on which output of the decoder 61 is excited, since each output of the decoder corresponds to one memory cell in block 45 (the outputs of the decoder 61 are indicated by the bus in Fig. 1). Read the selected constant to the input D _{1 of the} adder 43 is carried out by the signal from the output of the comparison circuit 10 at the input of the access resolution block 45. Block 45 can be implemented, for example, on standard integrated circuits 556РТ5, buffered by bus shapers 589АП16 at the inputs.

Permanent memory unit 46 is intended for storing sets of codes that provide control of a group of multiplexers 42.1-42.k in the mode of algorithmic reconfiguration according to the template. At block 46, the dual addressing principle is used. At the address input A ₁ in accordance with the code of the failed command from the output of register 7, a sequence of control codes is selected, each set inside which is selected at the address input A _{2 by} counter 38. Read control codes with the output 1-k of block 46, respectively, to the address inputs of the multiplexers 42.1-42.k is carried out by a signal from the output of the delay element 60, which excites the circulation enable input of block 46. Block 46 can be implemented, for example, on standard integrated circuits 556РТ5, buffered GOVERNMENTAL bus formers 589AP16 of inputs.

 Bus driver 47 is designed to buffer the outputs of block 3 of read-only memory. It provides the reading of information from block 3 to input-output 27 in the event that the enable input is enabled by a logical "1" signal from the output of the OR element 55. Otherwise, the output of the bus driver is in a high-impedance state and does not affect the transmission of information through input-output 27. The bus driver 47 is implemented similarly to the bus driver 2.

 The bus driver 48 is designed to buffer the outputs of the register 39. It provides information from the register 39 to the address input of block 3 if the enable input is activated by a logical "1" signal from the output of the And 67 element. Otherwise, the output of the bus driver is in a high-impedance state and does not affect transmitting information at the address input 28. The bus driver 48 is also implemented similarly to the bus driver 2.

The bus driver 49 is designed to buffer the outputs of the demultiplexer 56. It provides information from the output D _{o of the} demultiplexer 56 to the input-output 27 if the enable input is activated by a logical "1" signal from the output of the And 65 element. Otherwise, the output of the bus driver is in a high impedance state and does not affect the transmission of information at the input-output 27. The bus driver 49 is also implemented similarly to the bus driver 2.

 The bus driver 50 is designed to buffer the outputs of the group of registers 41.0-41.k, these outputs are connected respectively to its 1-k (shown in Fig. 1 indicated by the bus) information inputs. It provides the reading of information at the input-output 27 in the case of activation of the enable signal by a logical "1" signal from the output of the And 66 element. Otherwise, the output of the bus driver is in a high impedance state and does not affect the transmission of information at the input-output 27. The bus driver 50 is also implemented similar to bus driver 2.

 The one-shot 51 is designed to control the OR 53 and AND 67 elements when a logical "1" signal appears at the output of the delay element 59, while the one-shot 51 also blocks the And 65, 66 elements, keeping the outputs of the bus drivers 49, 50 in a high impedance state. The one-shot 51 is implemented similarly to the one-shot 23.

 The OR-NOT 52 element is designed to control the OR 55 element if the input 29 of the information substitution mode and the input 31 of the partial reconfiguration mode of the device are activated.

 The OR element 53 is designed to reset the counter 38 to either the initial reset signal from the input 33, or the output of the single-shot 51.

 The OR element 54 is intended to control the delay element 60 in the event that the output 1.0 of the decoder 1 or the output of the AND element 15 is excited.

 The OR element 55 is designed to control the enable input of the bus driver 47 if the output of the OR-NOT 52 element or the output of the And 62 element is excited.

 Demultiplexer 56 is designed to connect the output of a group of delay elements to either the information input of the bus driver 49 or to the information input of the register 40 depending on the signal value at the output of the comparison circuit 10 (if the output is logical “1”, then the input of the demultiplexer 56 is connected to the information input register 40). Demultiplexer 56 can be implemented, for example, on standard integrated circuits 155ID3.

 The group of delay elements 57 (indicated by one element in FIG. 1) is intended to delay the information received from the output of the multiplexer 25 to the input of the demultiplexer 56 for the period of time necessary for the operation of the comparison and switching circuit 10 (in connection with this) of the demultiplexer 56.

 The delay element 58 is designed to delay the signal from the output of the comparison circuit 10 to the synchronization input of the register 39 for a period of time necessary to complete the calculations in the adder 43.

 The delay element 59 is designed to delay the control signal of the one-shot 51 from the separate output of block 4 for the period of time necessary for reliable reading of the template from block 4, completion of the formation on its basis of an equivalent replacement program for a failed command.

 The delay element 60 is designed to delay the signal from the output of the OR element 54 to the input of the access permission of the memory unit 46 for a period of time necessary for the reliable operation of the counter 38.

 The decoder 61 is designed to control the block 45 of the memory. It decodes the information recorded in register 7, if the output of the element NOT 44 is activated, which excites the enable input of the decoder 61. The number of decoder outputs corresponds to the number of cells in block 45. Depending on the command code recorded in register 7, the decoder output is excited 61, activating the cell of block 45, where the constant corresponding to this code is recorded. The decoder 61 can be implemented, for example, on standard integrated circuits 155ID3.

 The AND element 62 is designed to control the OR element 55 if the input 31 of the partial reconfiguration mode is activated and the output of the OR element 11 is not activated.

 Element And 63 is intended to control the counting input of the counter 38 if the input of the element NOT 44 and the output 1.0 of the decoder 1 are excited.

 Element And 64 is intended to control the recording of information in the register 40 if the output of the comparison circuit 10 is activated and the input 30 of the full reconfiguration mode and the input 36 of the type of information to be replaced are not activated.

 Element And 65 is designed to control the resolution input of the bus driver 49 in the event that the output of the element HE 44 is excited and the output of the one-shot 51 is not activated.

 Element And 66 is designed to control the enable input of the bus driver 50 in the event that the output 1.0 of the decoder 1 is excited and the output of the one-shot 51 is not activated.

 Element And 67 is intended to control the resolution input of the bus driver 48 in the event that the output of the single-shot 51 is excited and the output 30 of the full reconfiguration mode is not activated.

 The device operates as follows.

 Setting mode. In this mode, the external computer records in the register 7 and 6.26 counters the configuration information. Previously, before recording information at input 38, counter 6, register 7, trigger 9 are reset to zero via OR 13 and counter 38 via OR 53. In this case, an information word is received at input-output 27, and the address of the memory cell is set at address inputs, t .e. register address 7. Since in this case the input 34 of the device is activated, the output of the OR element 14 is activated, the enable input of the decoder 1, its output 1.1 and, accordingly, the output of the element And 15 are activated, which leads to the entry in the register 7 of the command code requiring algorithmic reconfiguration , as well as to issue to the address inputs of the group of multiplexers 42.1-42. k control sets from the outputs 1-k, respectively, of block 46 (the first address input of which receives the command code from register 7, and the second value is zero from the output of counter 38), since the logical "1" at the output of AND element 15 through OR element 54 and delay element 60 permits the output of the information necessary for the pattern-based algorithmic reconfiguration mode.

 Similarly, information is recorded in counter 6, where the address of the command to switch to a given variant of the algorithmic configuration is recorded, and output 1.2 of decoder 1 and output of element 16 are excited. Information is recorded from input-output 27. A code for the number of repetitions of a given number can be written to counter 26 teams that require algorithmic reconfiguration. In this case, similarly to the above, the output 1.3 of the decoder 1 is excited, the output of the element And 17, and information is recorded at the inputs of the counter 26 from the input-output 27 by a clock from the output of the element And 17.

 The mode of replacing information in the cell. In this mode, logic “1” is supplied to inputs 30, 37. The information loaded into the register 7, in this case, has the meaning of the address of the cell in which the information is to be replaced, and the address code of the new information is recorded in counter 6. Counter 26 is not used in this mode. Logic "1" is supplied to input 36 and input 28 is connected to comparison circuit 10. Information from the output of the multiplexer 25 also arrives at the demultiplexer 56, from which (depending on the signal at its address input) it is fed either to the bus driver 49 or to the register 40, but in this mode these elements are not used, since the register synchronization input 40, the zero signal from the output of the And 64 element is set, and at the resolution input of the bus driver 49, the zero signal from the output 1.0 of the decoder 1. The inputs 29, 31, 32 are reset, a single signal from the output of the OR-NOT 52 element through the OR element 55 excites the bus control inputormirovatelya 47, providing external computer reads (with entry and exit 27) and executing a program recorded in a permanent memory unit 3. In this case, the input 35 or 32 is excited, therefore, the output 1.5 of the decoder 1 is excited at the addresses of the cells of block 3 and, since the trigger 9 is still zero, the output of the And 19 element excites the sample input of the block 3, from which, in accordance with the addresses set at the input 28 , either the command or the data for input-output 27 is read through the bus driver 47. If information is read at the address specified in register 7, the output of element 21 is excited (input 30 and output 1.5 of decoder 1 are excited), therefore, through element OR 12 drive control input circuit 10 comp Eden. The output of the comparison circuit is activated (the information in the register 7 is equal to the information at the input 28 coming through the multiplexer 25), therefore, the trigger 9 is set, since its information input is connected to the input of the logical "1" of the device, the address set at the input 28 is written in register 8 . Changes the state of the counter 26, however, in this mode it is not used. The output of the trigger 9 through the element And 19 blocks the reading of information from block 3 and connects the block 5 through the element And 18, which ensures the replacement of information at a given address. In block 5, one information output is designed to reset trigger 9 after such a replacement, which occurs with a delay determined by element 24 (necessary for reliable reading of the replaced information), by a single-vibrator 23, which, through element OR 13, resets trigger 9. The state of counter 6 changes. At the next installation of trigger 9, block 5 reads information from the next cell. Therefore, the replaced information may change during the computing process. Otherwise, it is necessary to set a logical “0” at the input, blocking the passage of counting pulses.

Similarly to the prototype, in this mode, replacement can be carried out not only by addresses, but also by data. In this case, the input 36 is not activated (the output of the multiplexer 25 is connected to the input D _o ), and a code is written in register 7, which must be replaced by another one written in block 5. To replace only the data, the logical “1” is supplied to the control input 29, at the output of the OR-NOT 52 element, a logical "0" appears, which through the OR element 55 transfers the output of the bus driver 47 to a high impedance state (at the output of the And 62 element, a logical "0"), i.e. excludes reading information from block 3 directly to input-output 27. Logical "1" from the output of the element NOT 44 through the AND element 65 activates the enable input of the bus driver 49 (logical "0" at the output of the one-shot 51). Now the information from the output of block 3 to the input-output 27 enters through the multiplexer 25, the demultiplexer 56 and the bus driver 49. Similarly to the above, when reading the code set in the register 7, the output of the comparison circuit 10 is activated, the trigger 9 is installed and is read from block 5 every time other necessary information, taking into account the change in state of counter 6, if necessary. Addresses recorded in register 8 can be used for debugging in order to check the operation of the device, moreover, they are read from register 8 programmatically: output 1.4 of decoder 1 is excited (register 8 is programmatically accessible as a memory for reading through bus former 2), the bus control input is excited shaper 2 and the address from the register 8 is fed to the input-output 27.

 Full algorithmic reconfiguration mode. In this mode, the device provides the issuance of 27 unconditional jump command codes to the inputs and outputs to replace commands that cannot be executed by an external processor due to some partial failure of its hardware (this can be identified by the processor itself based on the results of, for example, its self-test) on their algorithmic equivalents made up and the remaining teams. Unlike the prototype, in block 4, the entire program of equivalent replacements is not written down, but only their templates (consisting of command templates), on the basis of which the proposed device, through the use of the operands of the failed command, forms full replacements of the failed teams. This allows you to significantly reduce these programs, and consequently, the required amount of memory and the execution time of equivalent replacements.

In register 7, the code of the command to be replaced is recorded, in counter 6, the address of the command corresponding to this code is the unconditional jump to the beginning of the algorithmic equivalent of the template recorded in block 4. Logic "1" is fed to control inputs 29, 37, and inputs 30, 31, 36 logical "0". Moreover, the supply of logical levels to the control inputs can be carried out, for example, by an external processor by outputting the code to some external register (not shown in Fig. 1) or, for example, by supplying the required voltage levels rigidly. Logical "0" from the output of the OR-NOT 52 element through the OR element 55 (at the output of the AND 62 element also logical "0") sets the output of the bus driver 47 to a high impedance state, and the signal from the output of the element NOT 44 activates the control inputs of the decoder 61 through the AND element 65 of the bus driver 49, as well as the first input of the And 63 element. As a result of switching the bus driver 47 to a high impedance state and activating the output of the bus driver 49, the device excludes reading into the external processor at the input-output during the entire mode 27 of the faulty command (not provided by the prototype), checking on the comparison circuit 10 (since the inputs D ₁ and D _o of the comparison circuit are connected respectively to the outputs of register 7 and multiplexer 25) of all information read from block 3 for consistency with the command code recorded in register 7. In the event of a mismatch, the information from block 3 to the input-output 27 goes through a multiplexer 25, a group of delay elements 57, a demultiplexer 56, and a bus driver 49. The outputs of blocks 2, 5, 47, 50 are in a high-impedance state and are not influence to transmit information on the input-output 27. Logical "1" at the control input of the decoder 61 allows it to decode the command code from register 7. As a result, the output of the decoder 61 corresponding to the format of the failed command is excited (in Fig. 1, the outputs of the decoder 1 are indicated by the bus ), and in block 45, a memory cell is selected from which the constant necessary for calculating the advanced address (memory address of the memory block 3, following the one from which the faulty command was read) will be read. The process of calculating the advanced address consists in increasing the address of the failed command by the length (in bytes) of this failed command (since the information in the main memory of the computer is sequentially a single array), which is performed by the adder 43. The number of required cells in block 45 is determined by the number of different command formats, used in the sun. So, for example, for the processor BI 0210 EC computer (BI 0210 Technical description CE 3.031.041 TO1 1987), where commands and data bits 16 and 32 are used, two memory cells are sufficient (constants 2 and 4 will be in the memory of block 45).

. На остальные входы D₁-D_k этих мультиплексоров подаются соответственно информационные участки 1-k отказавшей команды (код команды не используется) из регистра 40 (т.е. i-й информационный участок отказавшей команды подается на все i-е входы мультиплексоров 42.1-42.k). Мультиплексоры 42.1-42. k управляются по адресным входам кодами из блока 4, т.е. в регистры 41.1-41. k в данном режиме целиком переписана команда (слово шаблона) из соответствующей ячейки блока 4 в случае управляющего кода

(выходы всех мультиплексоров 42.1-42.k подключены к их входам D_o) или в эти регистры записывается скорректированное слово шаблона для иного управляющего кода (т.е. из регистра 40 в слово шаблона внесены соответствующие информационные участки отказавшей команды). Количество мультиплексоров k определяется в зависимости от формата используемых команд и соответствует количеству выходов регистра 40. Например, в процессоре БИ 0210 ЕС ЭВМ используются команды форматов, представленных на фиг.3.When reading from block 3, the output 1.5 of decoder 1 is excited, when the command is sampled, input 32 is excited, input 29 is excited, therefore the outputs of the AND 22, OR 12 elements are activated, and therefore, when comparing (i.e., the faulty command was read from block 3) the output of the comparison circuit 10 is activated, which sets the trigger 9 to a single state, writes to the register 8 the address of the command to be algorithmically reconfigured, issues the corresponding constant command code from block 45 to the input D _{1 of the} adder 43 through the address input of the demultiplex Sora 56 provides the connection of its input to output D ₁ . In addition, a single signal at the output of the comparison circuit 10 activates the output of the And 64 element, which provides recording into the register 40 through the demultiplexer 56 (with the delay provided by the group of delay elements 57, in order to reliably trigger the demultiplexer 56) of the command during which the comparison occurred. The outputs 1-k of the register 40 allow you to use any information section of the failed command at each step of reading the template. Reading information from a particular output of register 40 (for writing to a template of one or another information section of a failed command) is carried out in accordance with the control code at the outputs 1-k of block 46, which respectively arrive at the address inputs of multiplexers 42.1-42.k. Since the address of the failed command is received at the input D _{o of the} adder 43 from the output of the register 8, and the necessary constant is input at the input D ₁ , the advanced address from the output of the adder 43 will be read into the register 39 (writing to the register 39 is provided by the logical "1" from the output of circuit 10 comparison with the delay performed by the element 58 in order to reliably operate the register 8 and the adder 43). The output of trigger 9 blocks the element And 19 and unlocks the element And 18. Such blocking occurs so quickly that the external processor does not enter information from the output of block 3, but from the output of block 5. The outputs of blocks 2, 4, 50 at this moment are in a high impedance state and do not affect the transmission of information at the input-output 27 (the output of the bus driver 49 also has no effect, since its information input-output is disconnected from the input of the demultiplexer 56). As already described, from block 5 in this mode, the command to unconditionally switch to the specified algorithm equivalent template is read, which is perceived by an external processor. The frequency of synchronization of the external processor is such that it reads information from the data bus later than the possible trigger moment of trigger 9 and switching the 3.5 memory blocks, so the processor will not "notice" that the device will "substitute" an unconditional transition to the algorithm algorithm template instead of the faulty command code equivalent, written in block 4. At the same time, the output 1.5 of decoder 1, the output of element And 18, and the enable input of block 5 are excited. If the unconditional jump command contains more than one word, then the processor goes to block 5: the output 1.5 of decoder 1 is excited and the next word is read from block 5, since the state of counter 6 has changed by the trailing edge of the pulse at output And 18. When reading the last word, a separate output of block 5 is excited and with a delay determined by delay element 24, the one-shot 23 is triggered, in connection with which the trigger 9 is reset via the OR element 13. The external processor programmatically proceeds to execute the algorithmic equivalent of the failed command based on the corresponding template from block 4. In this case, it is excited in move 1.0 of decoder 1 (the addresses of the patterns of the algorithmic equivalents do not intersect with the addresses of the main program recorded in block 3) and the first word of the pattern (command pattern) from the outputs 0-k (not shown in FIG. 1) of block 4 goes to the input of register 41.0 and inputs D _o multiplexers 42.1-42. k. Moreover, each read word of the template is decomposed: the first bits of the word (representing the command code) are fed to the input of register 41.0, the remaining bits are divided into k groups (information sections) and fed respectively to the inputs D _{o of} multiplexers 42.1-42.k (i.e. at the input D _{o of the} multiplexer 41.i, the i-th part of the command (template words) from block 4, i =

. The remaining inputs D ₁ -D _{k of} these multiplexers are respectively supplied with information sections 1-k of the failed command (command code is not used) from register 40 (i.e., the i-th information section of the failed command is fed to all i-inputs of the multiplexers 42.1- 42.k). Multiplexers 42.1-42. k are controlled by address inputs by codes from block 4, i.e. into registers 41.1-41. k in this mode the command (template word) from the corresponding cell of block 4 is completely rewritten in the case of the control code

(the outputs of all multiplexers 42.1-42.k are connected to their inputs D _o ) or the corrected template word for a different control code is written in these registers (i.e., from register 40, the corresponding information sections of the failed command are entered into the template word). The number of multiplexers k is determined depending on the format of the commands used and corresponds to the number of outputs of the register 40. For example, in the processor BI 0210 of the EC computer commands of the formats shown in FIG. 3 are used.

 It should be noted that S format commands that make up 11% (check I / O, start I / O, stop I / O, check the channel, write down the processor addresses, load the program status word) in case of failure cannot be implemented by the proposed method (i.e., a combination of the remaining ones), therefore, in the future, the format S is not considered. Then the operands or information about them in the example under consideration are always placed in bits 8-32 of the instruction format.

For the command system under consideration, it is advisable to use the eight-bit register 41.0 (for the command code) and four-bit registers 41.1-41. k, multiplexers 42.1-42. k respectively should provide switching four-bit tires. Knowing the maximum length of the commands used and the number of bits allocated for the command code, it is not difficult to determine k = (32-8) / 4 = 6. In a universal device, the number k can be equal to the number of bits allocated in the largest format for the operands. At the inputs D ₁ -D _{k of the} multiplexers 42.1-42.k, information sections 1-k of the failed command are respectively sent from the outputs 1-k of the register 40. Therefore, in accordance with the control code of the block 46 (along the leading edge of the signal 1.0), the first command is recorded equivalent replacement programs (the first word of a template saturated with necessary contextual information) in registers 41.1-41.k. Since the outputs of these registers are connected respectively to the information inputs 0-k (not shown in Fig. 1) of the bus driver 50, the first synthesized command through the bus driver 50 (whose enable input is activated by signal 1.0) is read to the input-output 27. On the trailing edge of signal 1.0, the counter state increases by one (equal to one) and from block 46 with a delay determined by delay element 60 (in order to reliably operate counter 38, which chooses the next control code in block 46, and also excludes interference during the formation of the previous bypass command in registers 41.0-41.k), multiplexers 42.1-42 are configured through the address inputs. k to form the second bypass program command. The formation of the second command in the registers 41.0-41.k and reading to the input-output 27 through the bus driver 50 are again carried out on the rising edge of the signal 1.0, on the falling edge of which the state of the counter 38 again increases by one. Further, the device operates similarly until the last word of the template is read from block 4 and read from the bus driver 50 to the input-output 27 of the last command of the algorithmic equivalent. Moreover, if necessary, it is possible to read information from block 3 at the input-output 27 (since the And 19 element is already unlocked by this moment) through the multiplexer 25, delay element 58, demultiplexer 56, and bus former 49 (zero signal from the output of comparison circuit 10 provides the connection of the output D _{o of the} demultiplexer 56 to its input, as well as the AND element 64 eliminates the change of information in the register 40). The outputs of the bus drivers 2.47 and block 5 are in a high-impedance state and do not affect the transmission of information to an external processor via input / output 27, and the addresses used in blocks 3 and 4 are not repeated. After reading the last word from block 4, its separate output is excited and, with the delay determined by element 59, a single-shot 51 is activated, which through element And 67 activates the control input of bus driver 48. Through the bus driver 48, an advanced address is supplied to the address input of memory unit 3 (recorded in register 39), i.e. in the future, the program based on the commands read from block 3 (the output 1.5 of the decoder 1 is activated similarly to the above) is executed taking into account the results of the algorithmic equivalent of the failed command. Moreover, the reading of commands from block 3 to input-output 27 is still carried out through multiplexer 25, a group of delay elements 57, demultiplexer 56, and bus driver 49 until a new failed command appears in the program.

 If the unconditional jump command (in block 5) contains several words, then the program of the algorithmic equivalent should provide for the return of the contents of counter 6 by writing the necessary address to it (referring to it as a memory cell with a fixed address that excites the output 1.2 of decoder 1). If the unconditional jump command used contains one word (for example, BCR and BC at R1 = 15 for processor BI 0210), then output 37 is reset and this is not necessary.

A modification of the described mode is possible in this case, access to block 5 occurs depending on the address at inputs 28. For this, logical “1” is supplied to device inputs 30, 36, logical “0” to input 29. Logical "1" from the output of the OR-NOT 52 element through the OR element 55 activates the enable input of the bus driver 47, allowing the output of information from block 3 to input-output 27, and the logical "0" from the output of the element NOT 44 through the AND 65 element translates into high impedance state the output of the bus driver 49. A zero signal at the output of the And 67 element supports the output of the bus driver 48 in a high impedance state, and a zero signal from the output of the And 64 prevents writing to register 40. Accessing block 5 to read the unconditional jump command goes if the address at input 28 matches the address recorded in register 7. Similarly, information is read from block 4, but in this case, not templates are written in the corresponding memory area of the block, but ready-made commands, while control block codes 46 represent sets of zeros (that is, they provide the connection of inputs D _{o of} multiplexers 42.1-42.k with their outputs). Moreover, after the completion of the program recorded in block 4, a program transition to the address recorded in register 8 (as described above) is possible, which allows you to "expand" the software recorded in block 3 at specified points without breaking the structure. This, for example, is necessary for modifying a certain program for the purpose of improvements or for the purpose of the required reduction of the algorithm in the process of its repeated use during operation of the aircraft.

 Partial algorithmic reconfiguration mode. In this mode, the algorithmic reconfiguration is performed not every time when a given command code is read from block 3, but a specified number of times. Partial algorithmic reconfiguration is necessary, for example, to modify a program by once or repeatedly replacing a command with its algorithmic equivalent in order to compare the results of calculations to control the operation of the aircraft. The code of the number of configurations is entered in the counter 26 (described in detail in the setup mode), the logical "1" is supplied to the inputs 31, 37, the inputs 29, 30, 36 are reset. The output of the bus driver 47 is held in a high impedance state by a logical “0” from the output of the OR element 55 and information is read from block 3 as in the previous mode. Through the element OR 11, the input of the element And 20 is excited, the output of which is excited when reading the command, since in this case the output 1.5 of the decoder 1 and the input 32 are excited. Therefore, similarly to the previous mode, the output of the element OR 12 is excited and if the specified command code is read from block 3 , the output of the comparison circuit 10 is excited, the trigger 9 is set, and further the device operates as described above. After zeroing the trigger 9 by the trailing edge of the signal from its output, the contents of the counter 26 are reduced by one. Algorithmic reconfiguration is performed until the counter 26 is reset to zero, then the logical “0” is set at the output of the OR element 11, which blocks the And 20 element, it is also blocked comparison circuit 10 for synchronization input. Logical "0" at the output of the OR element 11 excites the inverse input of the And 62 element (at the input 31 logical "1"), the logical "1" from the output of which through the OR element 55 activates the enable input of the bus driver 47, and the logical "0" from the output of the element NOT 44 puts the output of the bus driver 49 into a high impedance state. Subsequently, the information from block 3 is read to the input-output 27 through the bus driver 47 (the outputs of blocks 2, 5, 49, 50 are in a high impedance state).

 It should be noted that the counter 26 and trigger 9 can be reset by software when the external processor accesses them both to fixed memory cells (both in read and write modes), while outputs 1.7, 1.6 of decoder 1 are respectively excited. This can be necessary, for example, to terminate the algorithmic reconfiguration mode during debugging or during aircraft operation.

 Thus, the proposed device, providing the entire range of prototype operating modes, allows in the algorithmic reconfiguration mode to significantly reduce memory costs and, accordingly, the execution time of the algorithmic equivalent of a failed command. For comparative evaluations, we consider examples of equivalent replacements for one of the BI 0210 processor commands with the prototype and the proposed device. Suppose that as a result of a processor self-test, a malfunction is detected; failure to execute the addition command A (5A).

For the prototype, the program of the algorithmic equivalent of this command, written in block 4, can look like this (150 _{16 is} used as the starting address):
150 90 0 6 0 0 E 0 write to the memory of the contents of all general purpose registers (RON);
154 58 4 0 0 0 DC write to the memory of the advanced address, determining the address of the failed
158 98 5 6 0 0 2 8 commands, writing it to memory;
15C 54 6 0 0 0 A 0
160 50 6 0 0 0 8 0
164 50 5 0 0 0 7 C
168 5V 6 0 4 7 7 0
16C 50 6 0 0 0 A 4
170 54 6 0 0 0 C 8
174 47 7 0 0 IDA transfer to the IDA address if the failed team is located at the edge of the word, otherwise at 178;
178 58 6 0 0 0 A 4 selection of the contents of the failed command,
17C 58 6 0 6 0 0 0 if it is written on the word boundary;
180 18 5 6 highlighting the attributes of a failed team,
182 54 6 0 0 0 1С filling in the bypass pattern (addresses
186 56 6 0 0 0 C 5 IAA-IB6);
18A 50 6 0 0 1 A A
18E 89 5 0 0 0 0 8
192 88 5 0 0 0 1 C
196 89 5 0 0 0 0 2
19A 4A 5 0 0 1 5 2
19E 40 5 0 0 1 V 0
1A2 40 5 0 0 1 V 8
1A6 98 0 6 0 0 E 0 first recovery of RON-s;
IAA 00 0 0 0 0 0 0 the actual bypass pattern of a failed team in this case, for IAE 58 2 0 0 0 0 0 due to the use of sequential operations loading add-ons
IB2 13 3 3 LCR (13) and register subtraction SR (IB);
IB4 1B 2 3
IB6 50 2 0 0 0 0 0
IVA 98 0 6 0 0 E 0 the second recovery of RON-s (taking into account the results of the bypass IVE 47 8 0 0 ID 6 and the failed command);
IC2 92 1 0 0 0 V 0
IC6 47 4 0 0 ID 6 correction of the condition code depending on the results of the bypass ISA 92 2 0 0 0 8 0 yes of the failed command;
ISE 47 2 0 0 ID 6
ID2 92 3 0 0 0 8 0
ID6 82 0 0 0 0 7 C jump to an advanced address, i.e. address to the following
mu for the address of the failed team;
IDA 58 6 0 0 0 A 4 selection of the contents of the failed command for the case when it is on the IDE 58 6 0 6 0 0 0 moves at the half-word boundary, after completion unconditionally jumps to IE2 54 6 0 0 0 A 8 moves to the general program section (at 180).

IE6 58 5 0 0 0 2 C
IEА 5В 5 0 4 7 7 4
IEE 58 5 0 5 0 0 0
IF2 88 5 0 0 0 1 0
IF6 IA 6 5
IF8 47 F 0 0 1 8 0
In addition, the constants used in this program for equivalent replacement are: 000FFFFF (OIC), 00040000 (ODC), 58300000 (OOC), CFFFFFFF (OAO), 00000003 (OC8), FFFF0000 (OA8).

 That is, to implement the full algorithmic reconfiguration mode, the prototype needs an algorithm of 45 teams (18 of them are different), and the cost of permanent memory will be 196 bytes.

0 2 3 4 5 6
170 13 0 0 0 0 0 0 0 0
172 50 0

0 2 3 4 5 6
176 58

0 0 2

4 1 0 0 0 1 0
17А 5B

1 2 3 4 5 6
17Е 50 0 0 0 2

4 0 0 0 0 1 0
182 58 0 0 0 2 0 4 0 0 0 0 0 0
186 58 1 0 0 2 1 4 0 0 0 0 0 0
18А 58 2 0 0 2 2 4 0 0 0 0 0 0
19Е 58 3 0 0 2 3 4 0 0 0 0 0 0
IA2 58 4 0 0 2 4 4 0 0 0 0 0 0
IA6 58 5 0 0 2 5 4 0 0 0 0 0 0
IAA 58 6 0 0 2 6 4 0 0 0 0 0 0
Из блока 45 используется константа "4".The proposed device for the equivalent replacement of the same operation A (5A) requires the following information:
in block 4, respectively, in block 46
150 50 0 0 0 2 0 4 0 0 0 0 0 0
154 50 1 0 0 2 1 4 0 0 0 0 0 0
158 50 2 0 0 2 2 4 0 0 0 0 0 0
15С 50 3 0 0 2 3 4 0 0 0 0 0 0
160 50 4 0 0 2 4 4 0 0 0 0 0 0
164 50 5 0 0 2 5 4 0 0 0 0 0 0
168 50 6 0 0 2 6 4 0 0 0 0 0 0
16C 58 0

0 2 3 4 5 6
170 13 0 0 0 0 0 0 0 0
172 50 0

0 2 3 4 5 6
176 58

0 0 2

4 1 0 0 0 1 0
17A 5B

1 2 3 4 5 6
17E 50 0 0 0 2

4 0 0 0 0 1 0
182 58 0 0 0 2 0 4 0 0 0 0 0 0
186 58 1 0 0 2 1 4 0 0 0 0 0 0
18A 58 2 0 0 2 2 4 0 0 0 0 0 0
19E 58 3 0 0 2 3 4 0 0 0 0 0 0
IA2 58 4 0 0 2 4 4 0 0 0 0 0 0
IA6 58 5 0 0 2 5 4 0 0 0 0 0 0
IAA 58 6 0 0 2 6 4 0 0 0 0 0 0
From block 45, the constant "4" is used.

символ первого операнда,

соответственно второго операнда. Например, если по адресу 4Е6D4 из блока 3 считана команда 5А

(с выходов 1-6 регистра 40 считывается соответственно 5,0,6,В,А,А), то с предлагаемого устройства на вход-выход 27 считана программа
50 0 0 0 2 0 4 запись в память содержимого всех РОН-ов;
50 1 0 0 2 1 4
50 2 0 0 2 2 4
50 3 0 0 2 3 4
50 4 0 0 2 4 4
50 5 0 0 2 5 4
50 6 0 0 2 6 4
58 0

загрузка в используемый РОН второго операнда (отказавшей команды);
13 0 0 проведение над содержимым используемого РОН-а операции загрузки
дополнения (в целях получения отрицательного значения второго опе-
ранда);
50 0

запись в память полученного отрицательного значения второго операн- да;
58

0 0 2

4 загрузка в используемый РОН первого операнда;
5В

из первого операнда вычитается отрицательное значение второго,
т. е. по существу осуществляется их сложение;
50 0 0 0 2

4 запись в память полученного значения (коррекция области памяти,
отведенной для данного РОН-а по результатам вычислений);
58 0 0 0 2 0 4 восстановление содержимого всех РОН-ов.In this algorithm, “*” indicates the positions at which the proposed device, as described above, introduces the attributes of a failed command:

character of the first operand

respectively, the second operand. For example, if at address 4E6D4 block 5A is read from block 3

(5.0.6, B, A, A are read from outputs 1-6 of register 40, respectively), then the program is read from the proposed device to input-output 27
50 0 0 0 2 0 4 record in the memory of the contents of all RON-s;
50 1 0 0 2 1 4
50 2 0 0 2 2 4
50 3 0 0 2 3 4
50 4 0 0 2 4 4
50 5 0 0 2 5 4
50 6 0 0 2 6 4
58 0

loading the second operand (failed command) into the used RON;
13 0 0 carrying out on the contents of the used RON-a loading operation
additions (in order to obtain a negative value of the second
randa);
50 0

writing to the memory of the received negative value of the second operand;
58

0 0 2

4 loading the first operand into the used RON;
5V

the negative value of the second is subtracted from the first operand
that is, in essence their addition is carried out;
50 0 0 0 2

4 record in the memory of the obtained value (correction of the memory area,
reserved for this RON based on the calculation results);
58 0 0 0 2 0 4 restoration of the contents of all RON-s.

58 1 0 0 2 1 4
58 2 0 0 2 2 4
58 3 0 0 2 3 4
58 4 0 0 2 4 4
58 5 0 0 2 5 4
58 6 0 0 2 6 4
Upon completion of reading this program from the register 39 through the bus driver 48 to the address input of block 3, the advanced address 4F6D8 will be read.

 Thus, the equivalent replacement of the failed team is provided by an algorithm of 20 teams (composed of four different), while the memory costs are 78 bytes in block 4 and 45 bytes in block 46, which gives a gain in comparison with the prototype more than 1.5 times. The prototype for the full algorithmic reconfiguration of the command in question when implementing on BI 0210 requires 346 μs (if the failed command is located in block 3 at the word boundary) or 424 μs (if at the half-word boundary), while the proposed device is only 112 μs, t i.e., the time gain is 3.1-3.8 times. In addition, the proposed device for implementing equivalent replacement uses significantly fewer different commands for A (5A), only four (in the prototype 4.5 times more than 18), which significantly expands the possibilities of using the proposed device in fault-tolerant aircraft in the conditions of multiple failures of the command system.

Claims (1)

 MEMORY CONTROL DEVICE, comprising a decoder, bus driver, three read-only memory blocks, two counters, two registers, a trigger, a comparison unit, four OR elements, eight AND devices, a single-shot, delay element, a multiplexer, the outputs of the third memory unit, bus driver, the information inputs of the first and second counters, the second register are the information input-output of the device, the information inputs of the first register, decoder, the second information input of the multiplexer, the address inputs of the first o and the second memory blocks are combined and are the address input of the device, the third input of the first OR element, the third input of the eighth element And and the fourth input of the sixth element And are combined and are the sample command input of the device, the third input of the second OR element, the installation inputs are “0” of the first and the second registers and the first counter are combined and are the input of the initial installation of the device, the second input of the first OR element, the second inputs of the first, second and third elements AND are the input of the device record, the first input of the first Entry OR by the device read input, the output of the first OR element is connected to the decoder enable input, the second, third and fourth outputs of which are connected respectively to the first inputs of the first, second and third AND elements, and the first decoder output to the access enable input of the second read-only memory block, output the first element And is connected to the synchronization input of the second register, the output of the second element And to the synchronization input of the first counter, the fifth output of the decoder is connected to the enable input of the bus driver, the output to the first inputs of the fourth and fifth elements And, the second input of the fourth element And and the inverse input of the fifth element And are connected to the trigger output, the output of the fourth element And to the permission input of the access of the third memory block, the output of the fifth element And to the permission input, the appeal of the first block memory, the seventh output of the decoder is connected to the first input of the second element OR, the eighth output to the input of the setting in "0" of the second counter, the clock input of which is connected to the output of the third element AND, the sixth output of the decoder is connected to the first m inputs of the sixth, seventh and eighth AND elements, the second input of the sixth AND element to the output of the third OR element, the third input is the input of the partial reconfiguration mode of the device, the output of the sixth AND element is connected to the first input of the fourth OR element, the second input of the seventh AND element is the mode input complete reconfiguration of the device, the output of the seventh AND element is connected to the second input of the fourth OR element, the second input of the eighth AND element is the input of the device information replacement mode, and the output is connected to the input of the fourth OR element, the output of which is connected to the gate input of the comparison unit, the output of the comparison unit is connected to the trigger inputs of the trigger and the first register, the output of which is connected to the information input of the bus driver, the output of the end of data reading of the third memory unit is connected to the input of the delay element, output which is connected to the input of the one-shot, the output of the one-shot is connected to the second input of the second OR element, the output of which is connected to the installation input in the "0" trigger, information the course of which is connected to the input of the logical unit of the device, the output of the trigger is connected to the subtracting input of the second counter, the outputs of which are connected to the inputs of the third OR element, the address input of the multiplexer is the input of the job type of the replaced information of the device, the output of the multiplexer is connected to the first information input of the comparison unit, the second information the input of which is connected to the output of the second register, the output of the first counter is connected to the address input of the third memory block, the input of which allows access о is connected to the counting input of the first counter, the input of the resolution of which is the input of allowing changing the address of the replaced information of the device, characterized in that a counter, two registers, a group of registers, a group of multiplexers, an adder, an element NOT, two blocks of read-only memory are entered into it bus driver, one-shot, OR element, three OR elements, demultiplexer, delay element group, three delay elements, decoder, six AND elements, the first input of the OR element is NOT an input of the replacement mode I have device information, the second input and the first input of the ninth element AND are connected to the input of the partial reconfiguration mode of the device, the inverse input of the ninth element AND is connected to the output of the third OR element, the output of the OR element is NOT connected to the first input of the seventh OR element, the second input of which is connected to the output of the ninth AND element, the output of the seventh OR element is connected to the input of the NOT element and to the enable input of the second bus driver, the information input of which and the first input of the multiplexer are connected to the output of the first unit In the eye of memory, the output of the element is NOT connected to the first inputs of the tenth and twelfth elements And and the enable input of the second decoder, the input of the complete reconfiguration mode of the device is connected to the third inverse input of the eleventh element And to the first inverse input of the fourteenth element And, the second input of which, the second inverse inputs the twelfth and thirteenth AND elements and the second input of the fifth OR element are connected to the output of the second one-shot, the output of the fourteenth AND element is connected to the resolution input of the third bus the driver, the information input of which is connected to the output of the third register, the output of the third bus driver is connected to the address input of the first memory block, the outputs of the second, fourth and fifth bus drivers are connected to the information input-output of the device, the output of the twelfth element And to the resolution input of the fourth bus driver, the information input of which is connected to the first output of the demultiplexer, the second output of which is connected to the information input of the fourth register, the inputs of the setting to "0" of the fourth and fourth registers and the first input of the fifth element OR are connected to the input of the initial installation of the device, the second inverse input of the eleventh element is connected to the input of the job of the type of replaceable information of the device, the first input of which is the permission input of the fifth memory unit, the input of the second delay element and the address input demultiplexer connected to the output of the comparison unit, the output of the eleventh element And connected to the synchronization input of the fourth register, the outputs of which are connected to the corresponding information the input inputs of all group multiplexers, the information input of the group zero register and the zero information inputs of the group multiplexers are connected respectively to the group of information outputs of the second memory block, the address inputs of the group multiplexers are connected to the corresponding outputs of the fourth memory block, the outputs of the group multiplexers to the information inputs of the corresponding group registers, outputs all registers of the group, respectively, to the group of information inputs of the fifth bus driver, the first output of the first the decoder is connected to the second inputs of the sixth OR element and the tenth AND element, to the synchronization inputs of all the registers of the group and to the first input of the thirteenth AND element, the output of which is connected to the resolution input of the fifth bus driver, the output of the end of data reading of the second memory unit is connected to the input of the third element delays, the output of which is connected to the input of the second one-shot, the output of the fifth element OR to the input of the initial installation of the third counter, the counting input of which is connected to the output of the tenth nta AND, the output of the first AND element is connected to the first input of the sixth OR element, the output of which is connected to the input of the fourth delay element, the output of which is connected to the circulation enable input of the fourth memory unit, the second address input of which is connected to the output of the third counter, the output of the second register is connected to the first address input of the fourth memory block and to the information input of the second decoder, the output of which is connected to the address input of the fifth memory block, the output of which is connected to the second input of the adder, the first second input of which is connected to the output of the first register adder output is connected to the data input of the third register, whose clock input is connected to the output of the second delay element, the multiplexer output is connected to inputs of the delay elements of the group, the outputs of which are connected to the data input of the demultiplexer.

Images