Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66742—Thin film unipolar transistors
  • H01L29/6675—Amorphous silicon or polysilicon transistors
  • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
  • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

• the present invention relates to the field of fabrication techniques for thin film transistors, and more particularly to techniques for self-aligned fabrication of thin film transistors.
• Background Informal-ion Thin film transistors TFTs are employed in liquid crystal displays and imagers to control or sense the state of each pixel of the display or image.
• TFTs Thin film transistors
• Such thin film transistors are typically fabricated from amorphous silicon.
• system operating characteristics are optimized by making each cell or pixel have substantially identical operating characteristics. These operating characteristics include switching speed, t capacitive loading of drive and sense lines, the gain of transistors and so forth.
• One of the processing problems which causes variation in the characteristics of different cells within such structures is the inability to accurately align the position of a mask which defines the source and drain electrodes of thin film transistors in a manner which ensures that the source/drain electrodes are accurately aligned with respect to the gate electrodes. Misalignment results in an increase in the overlap between the gate electrode and either the source electrode or the drain electrode with a corresponding decrease in the overlap between the gate and the other of them. Since the capacitances between the gate electrode and the source or drain electrodes are direct functions of the overlap between them, such a change in overlap produces a change in device's capacitances and consequently, switching speed and loading of other circuits.
• the possibility of misalignment requires that the size of the gate metal be increased to ensure that all devices have acceptable overlap between the gate and the source and drain. This increases the device size and hence the total capacitance per device.
• the device capacitance is important because it controls the charging time of the gate electrodes, the capacitive coupling between the gate and the source and drain nodes, and the noise introduced by the defects in the amorphous silicon or at the amorphous silicon/dielectric interface. Consequently, there is a desire to provide self- alignment between the source and drain electrodes and the gate electrode in order to maintain a fixed, predictable overlap between the gate electrode and each of -the source and drain electrodes across an entire wafer.
• a subordinate layer (source/drain metallization) is deposited on the support layer and may be either conformal or not conformal. If necessary, a planarization layer is formed over the subordinate layer to provide a planar upper surface for the structure. Material is then removed from the upper surface in a non-selective, uniform manner until the source/drain metallization becomes exposed in an aperture which is thereby created in the planarization layer.in alignment with the underlying reference layer pattern. The exposed portion of the subordinate layer is then selectively etched to expose the support layer.
• planarization etch could be continued until the support layer was exposed, but that would result in thinner source and drain electrodes.
• Other portions of the subordinate layer are then patterned, if necessary and the fabrication of the device completed. The result is a device in which the overlap of the subordinate layer over the reference pattern in the vicinity of the aperture in the subordinate layer is self-aligned with respect to the reference layer pattern.
• RD-19,584 can provide a very short overlap between the gate electrode and the source and drain electrodes. In particular, an overlap of less than 0.5 ⁇ m is achievable. Such a small overlap is desirable from the point of view of minimizing overlap capacitance and capacitance induced noise. Unfortunately, it is found experimentally that there is a minimum overlap between the gate and the source and drain electrodes below which the saturation drain current of a TFT degrades significantly. While the minimum length of this overlap for good device operating characteristics may vary with different semiconductor materials and other variations in the device structure, it would be desirable to have a technique for positively controlling the amount of overlap between the gate electrode and the source and drain electrodes in a self-aligned TFT structure.
• a primary object of the present invention is to provide a technique for positively controlling the length of the overlap between the gate electrode and the source and drain electrodes in a self- aligned thin film transistor.
• Another object of the present invention is to increase the versatility of the self-alignment technique disclosed in related application Serial No. (RD- 19,584) .
• Another object of the present invention is to provide a self-alignment method which is applicable to opaque substrates.
• the gate electrode as two separate layers of different conductors; patterning the entire gate electrode to the desired gate electrode pattern and subsequently etching the second layer of the gate electrode conductor back from the edges of the first level gate electrode conductor in a self-aligned manner whereby positive control of the degree of setback of the tapered edge of the upper layer (thick) gate conductor material from the lower layer (thin) conductor material is provided while retaining self-alignment.
• a self-aligned process which relies on propagation of the topography of the gate electrode through subsequently deposited layers of the structure provides gate-to-source and gate-to-drain electrode overlaps which are controlled by the setback of the second gate conductor layer with respect to the first gate conductor layer in addition to the setback produced by the slope of the tapered second gate conductor layer.
• the first and second gate conductor layers are sequentially deposited on a substrate in the same vacuum pumpdown, the gate conductor is photomasked and etched to expose the substrate in the areas where the gate conductor is not desired. Thereafter, the second gate conductor layer is etched back from the edge of the first conductor layer using the same gate mask and an etchant to which the first gate conductor layer is substantially immune and with a technique which tapers the second gate conductor layer to provide lateral edges on that layer which are suitable for the deposition of conformal layers thereover. Thereafter, substantially conformal gate dielectric and semiconductor layers are deposited on the structure followed by patterning of the semiconductor layers and then deposition of source/drain metallization which may be conformal or non- conformal.
• a planarization layer is deposited on top of the source/drain metallization to provide a planar upper surface for the device structure.
• the device structure is then etched in a non-selective manner until the source/drain metallization is exposed in alignment with the raised (thick) portion of the gate electrode pattern.
• the exposed portion of the source/drain metallization is then selectively etched to expose the n + amorphous silicon which is then removed. Thereafter, back channel passivation may be provided on the upper surface of the structure to minimize the effect of external conditions on the operating characteristics of the device.
• the resulting semiconductor device has a setback or top hat gate conductor configuration in which the effective electrical gate width is that of the thin, lower, wider gate conductor layer while the configuration of the thicker, upper, narrower gate conductor layer controls the self- alignment of the source and drain electrodes with respect to the gate electrode and thus the overlap between the source and drain electrodes and the gate electrode.
• Figure 1 is a perspective, partially cross section view of a substrate having an unpatterned reference layer disposed thereon;
• Figure 2 is a perspective, partially cross section view of the Figure 1 structure having a patterned layer of photoresist disposed thereon;
• Figure 3 is a perspective, partially cross section view of the Figure 2 structure following etching of an upper gate conductor layer
• Figure 4 is a perspective, partially cross section view of the Figure 3 structure following etching of a lower gate conductor layer
• Figure 5 is a perspective, partially cross section view the structure following etch back of the upper layer of the gate conductor from the edge of the lower gate conductor
• Figure 6 is a perspective, partially cross-section view of the Figure 5 structure following stripping of the retained photoresist
• Figure 7 is a perspective, partially cross-section view of the Figure 6 structure following the deposition of a gate insulator thereover;
• Figure 8 is a perspective, partially cross-section view of the structure following the deposition of two layers of semiconductor material
• Figure 9 is a perspective, partially cross-section view of the Figure 8 structure after patterning of the layers of semiconductor material
• Figure 10 is a perspective, partially cross-section view of the structure following the deposition of two layers of source/drain metallization
• Figure 11 is a perspective, partially cross-section view of the structure following completion of the structure through the formation of a substantially planar surface
• Figure 12 is a plan view of a portion of the structure
• Figure 13 is a perspective, partially cross-section view of the structure following uniform removal of enough material from the structure to expose the support layer within an aperture in the subordinate layer;
• Figure 14 is a perspective, partially cross-section view of the Figure 13 structure following etching of the support layer in the self-aligned openings in the subordinate layer;
• Figure 15 is a perspective, partially cross-section view of the structure following formation of a passivation layer over the structure.
• an amorphous silicon thin film (TFT) field effect transistor (FET) may be fabricated.
• TFT amorphous silicon thin film
• FET field effect transistor
• a substrate 12 has a uniform reference layer 18 disposed thereon.
• Reference layer 18 comprises first and second sublayers 14 and 16.
• the layer 18 constitutes the gate conductor while the substrate 12 constitutes a larger structure on which the transistor is to be disposed.
• the substrate 12 it is desirable that the substrate 12 be transparent, however, transparency of the substrate is unimportant to the present process and thus, is a matter of design choice in accordance with the intended use of the thin film transistor to be fabricated.
• Typical transparent substrate materials are glass, quartz and appropriate plastics.
• the gate conductor sublayers 14 and 16 are deposited on the substrate in sequence by any appropriate technique such as sputtering, chemical vapor deposition, thermal evaporation and so forth.
• This gate conductor is comprised of two layers of different metals such as a first layer of titanium disposed in contact with the substrate with a layer of molybdenum or aluminum (referred to as Mo/Ti and Al/Ti metallization, respectively) disposed thereover or a layer of chromium disposed on a substrate with a layer of molybdenum disposed thereover (Mo/Cr metallization) .
• the first sublayer of the gate conductor may be a transparent conductor material such as indium tin oxide or other transparent conductors. We prefer to use Mo/Cr.
• the gate electrode is typically deposited to a thickness of 1,000A to 10,000A, depending on the sheet resistivity required for the gate electrode structure and the vertical height of the top hat gate required to achieve good self-alignment.
• the Cr is preferably 100 to 500 A thick and the Mo is preferably 1000 to 10,000 A thick
• the Figure 1 structure is then photomasked to provide a mask pattern corresponding to the desired gate conductor configuration as shown in F:.gure 2.
• the upper surface of the second conductor 16 is exposed in the window 22 where the photoresist 20 has not been retained.
• the structure is dry etched preferably using reactive ion etching to pattern the upper conductor layer 16 in accordance with the retained photoresist pattern.
• the wafer is mounted in a reactive ion etching apparatus which is then purged and evacuated in accordance with normal reactive ion 64
• a source gas flow preferably of 37.5 seem (standard cubic centimeters per minute) of sulphur hexafluoride (SF ⁇ ) , 6.5 seem of CI 2 and 16 seem of O 2 is established, introduced into the etching chamber at a pressure of 65 mtorr and reactive ion etching potentials are applied to etch the molybdenum in the windows 22.
• This etching is preferably carried out until all the molybdenum is removed in center of the windows and is allowed to proceed for 40 seconds more of overetching to ensure that all of the molybdenum is removed from within the originally defined windows 22.
• This molybdenum etching step is preferably carried out at a power of 200 watts.
• a tapered gate electrode of this type may be provided in a variety of other ways well known in the art including reliance on the erosion of the photoresist during etching of the gate conductor where reactive ion etching (RIE) is employed or an isotropic wet etch may be employed which undercuts the resist during etching of the unprotected portion of the gate conductor.
• RIE reactive ion etching
• Such a slope is provided in RIE, in part because when the photoresist is baked after patterning to toughen it prior to RIE etching, the photoresist slumps with the result that its thickness tapers from small or zero at the edge of a photoresist region upward to the central thickness of the photoresist over a finite distance.
• the photoresist erodes as the gate conductor is etched with the result that a taper is produced on the retained portion of the gate conductor.
• the etching gas is preferably changed to
• the molybdenum upper layer of the gate conductor is etched back to expose a desired width of the first gate conductor layer. This may be done with the RIE using the same source gases as for the initial etching of the molybdenum, provided that that etchant does not excessively etch the now exposed portion of the substrate where the chromium has been removed.
• a gate dielectric layer 28 is deposited over the entire structure preferably by chemical vapor deposition or some other process which is known to produce a high integrity dielectric.
• This gate dielectric is preferably be silicon nitride but may be silicon dioxide or other dielectrics and is about 1,000 to 4000A thick.
• the chromium gate conductor layer 14 is sufficiently thin (10 to IOOOA) and the sidewall of the molybdenum gate conductor layer 16 is sufficiently vertically inwardly tapered or sloped that a high integrity conformal dielectric layer results.
• This deposition of gate dielectric on the upper surface of the structure is done in a conformal manner whereby the raised configuration of the patterned gate electrode extends to the upper surface of that gate dielectric layer, that is, the surface.topography is essentially unchanged as shown in Figure 7.
• a layer 30 of intrinsic amorphous silicon is deposited on the gate dielectric layer in a conformal manner. This intrinsic amorphous silicon layer
• a thinner layer 32 (about 500A) of doped (typically phosphorous doped, that is n + ) amorphous silicon is then deposited on the intrinsic amorphous silicon in a conformal manner to provide the structure illustrated in Figure 8.
• doped typically phosphorous doped, that is n +
• the dielectric layer, the intrinsic amorphous silicon and the doped amorphous silicon may all be deposited in the same deposition chamber without breaking the vacuum. Where that is done, we prefer to stop the plasma discharge in the deposition chamber after the completion of the deposition of a particular layer until after the proper gas composition for the deposition the next layer has been established. We then re-establish the plasma discharge to deposit that new layer.
• the two silicon depositions may be done in different chambers.
• this source/drain metallization is preferably a two layer molybdenum on chromium (Mo/Cr) metallization in which the Cr is 100 to lOOOA thick and the molybdenum is 1000 to 10,000A thick, as shown in Figure 10.
• this metallization may be a single metal such as molybdenum, chromium or tungsten .
• a planarization layer 40 (which may be photoresist) is then formed over the entire structure to provide a substantially planar upper surface 42 of the structure as shown in Figure 11.
• the topology of the patterned gate conductor is propagated upward through the various layers, at least through the support layer (the n + doped amorphous silicon in this example) on which the source/drain metallization is disposed. That propagation of topography could be terminated by the source/drain metallization itself, but is at this time preferably terminated by a separate planarization layer because common metallization deposition processes are substantially conformal in nature and making t.ie source/drain metallization conformal enables the final source and drain electrodes to be thicker.
• planarization reactive ion etch is then etched back in a non- selective manner by a planarization reactive ion etch.
• This planarization etch is preferably stopped once the molybdenum over the gate electrode has been exposed. That exposed molybdenum is then selectively etched with the remaining portion of the planarization layer serving as the etching mask to restrict that etching to the molybdenum which is over the gate electrode. This is followed by etching the now exposed chromium. As illustrated in Figure 12, a self- aligned overlap between the source and drain electrodes and the gate electro ⁇ e is produced. Alternatively, the planarization etch may be continued until the chromium layer of the source/drain metallization has been exposed.
• That exposed chromium 34 is then selectively etched to expose the doped silicon 32.
• the planarization etch can be continued until the doped silicon becomes exposed.
• the exposed doped silicon is removed by etching to leave only intrinsic silicon between the source and drain electrodes. This normally involves the removal of some, but not all of the intrinsic amorphous silicon in order to ensure that all of the doped amorphous silicon has been removed.
• the source/drain gap in the circle 60 in the top down view in Figure 13 is disposed in proper alignment with the underlying gate electrode 18. Since the source/drain gap is defined by the self-aligned planarization method just described, control of the size of the source/drain gap and its location is independent of the alignment of the etching mask 52 which controls the pattern and location of the other portions of the boundary of the retained source/drain metallization.
• the source and drain metallization is then patterned to provide the various desired segments of the source and drain metallization which connect to various devices and interconnect devices in a manner which is appropriate to the structure being fabricated.
• the etching of the pattern of the source/drain metallization may preferably be done in two stages using RIE with the appropriate source gases discussed above or it may be done by wet etching or other means. This yields the structure illustrated in Figure 14.
• a passivation layer 48 may be deposited on the upper surface of the structure as shown in Figure 15.
• This passivation layer is known as a back channel passivation layer since its purpose is to passivate the back or the away- from-the-gate-metallization surface of the silicon to maximize the stability of the device characteristics of this thin film transistor.
• This passivation layer is typically about 2,000A thick and may be silicon dioxide, silicon nitride or other insulators such as polyimide.
• the illustrated thin film transistor is only one of many such thin film transistors which are simultaneously fabricated on the same substrate.
• the semiconductor material in the just described embodiment is amorphous silicon, since that is the material p esently in typical use for thin film transistors, it should be understood that this process is equally applicable to the use of other semiconductor materials or other forms of silicon.
• the gate dielectric layer has been described as being silicon nitride, it will be understood that more than one sublayer may be present in the gate dielectric layer and various sublayers may have different compositions and a single layer dielectric may be Si ⁇ 2 or other dielectric materials.
• semiconductor materials which are presently used in an amorphous condition are germanium and cadmium selenide. This process technique is applicable to those amorphous silicon semiconductor materials and any others as well as being applicable to polycrystalline or even monocrystalline semiconductor materials where the underlying support structure supports the formation of such semiconductor layers.
• the distance by which the upper gate layer 16 is setback from the edge of the lower gate layer 16 is controlled by the rate at which the upper gate layer etches back and the length of time for which that etch back is allowed to proceed.
• this setback can be varied over a substantial range, from a fra.cion of a micron to several microns or more as may be considered desirable in a particular device.
• This provides the ability to controllably increase the degree of overlap between the gate electrode and the source and drain electrodes of self-aligned device produced in accordance with Application Serial No. (RD- 19,584), "Device Self-Alignment by Propagation of a Reference Structure's Topography".
• the first gate metallization layer is made of a material which is transparent or sufficiently trans issive of the actinic light employed to expose the photoresist that the photoresist can be exposed through the lower, thin, gate conductor and shadowed by the thick gate conductor in their self-aligned processes which expose the photoresist by directing the exposing radiation through the substrate as a means of establishing the channel region gap between the source and drain electrodes in a self-aligned manner.
• thin gate conductor layer Transmission of the exposing (UV) radiation through the first, thin gate conductor layer may be provided by use of a conductor layer which is transparent to that light frequency or alternatively, by use of gate metallization material which is opaque to that light frequency, but whose thickness is kept below about lOOA whereby a substantial portion of the actinic radiation incident thereon passes therethrough.
• the gate metallization pattern is fabricated in the same manner as described above and the device fabrication carried out in the manner described above through the deposition of the layer of intrinsic amorphous silicon.
• a layer of dielectric material is deposited on that amorphous silicon layer.
• a positive photoresist layer is disposed on that layer of dielectric material, expos d to actinic radiation through the substrate and the underlying layers of the device being fabricated and developed. This leaves a plug of photoresist in alignment with the thick, upper conductor of the gate metallization. This plug is then used as a mask for the removal of the dielectric layer where it is not protected by the photoresist. This leaves a plug of the dielectric material disposed on the intrinsic amorphous silicon in alignment with the thick, upper gate conductor material.
• n + doped amorphous silicon is deposited over the dielectric plug and the exposed portions of the intrinsic amorphous silicon.
• the source/drain metallization is then deposited, a planarization layer such as photoresist is formed over the upper surface of the structure and that upper surface of the structure is uniformly etched in a non-selective manner until the source/drain metallization is exposed over the dielectric plug because of its greater height there.
• This exposed portion of the source/drain metallization may then be selectively etched to expose the n + doped amorphous silicon which is disposed on the dielectric plug.
• the now exposed portion of the n + amorphous silicon is then removed to expose the top of the dielectric plug to isolate the source and drain electrodes from each other in this region.
• the source/drain metallization layer is then further patterned to remove at least those portions which connect the source and drain electrodes to each other outside this portion of the structure. Alternatively, that patterning of the source/drain metallization may be done before deposition of the planarization layer. Any other steps necessary to the fabrication of the device are then carried out.
• the silicon could be left unpatterned. This results in intrinsic amorphous silicon and n + amorphous silicon being left under the source/drain metallization in all places. For applications such as imagers this is acceptable. Just the intrinsic amorphous silicon could be patterned before the n + amorphous silicon deposition and then the source/drain metallization deposited. This would result in n + under the source/drain metallization in all places. This could be acceptable even for displays where the contact to the transparent electrode would then be metal/n + /transparent electrode. While the invention has been described in. detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Ceramic Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=24374648

Family Applications (1)

Country Status (4)

Cited By (5)

Families Citing this family (1)

Citations (4)

Family Cites Families (1)

• 1991
  • 1991-10-02 DE DE19914192352 patent/DE4192352T/de not_active Withdrawn
  • 1991-10-02 JP JP51794791A patent/JPH04505830A/ja active Pending
  • 1991-10-02 WO PCT/US1991/007335 patent/WO1992006497A1/en active Application Filing
• 1992
  • 1992-04-30 GB GB9209424A patent/GB2254187A/en not_active Withdrawn

Patent Citations (4)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events