WO1988005569A1 - Systeme a multicalculateur et son procede de commande - Google Patents

Systeme a multicalculateur et son procede de commande Download PDF

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Publication number
WO1988005569A1
WO1988005569A1 PCT/DE1987/000533 DE8700533W WO8805569A1 WO 1988005569 A1 WO1988005569 A1 WO 1988005569A1 DE 8700533 W DE8700533 W DE 8700533W WO 8805569 A1 WO8805569 A1 WO 8805569A1
Authority
WO
WIPO (PCT)
Prior art keywords
reset
computers
computer
computer system
operating voltage
Prior art date
Application number
PCT/DE1987/000533
Other languages
German (de)
English (en)
Inventor
Wolfgang Drobny
Werner Nitschke
Peter Taufer
Hugo Weller
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1988005569A1 publication Critical patent/WO1988005569A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • Multi-computer system and method for controlling the multi-computer system are Multi-computer system and method for controlling the multi-computer system
  • the invention relates to a multicomputer system, the individual computers of which are acted upon by a first switch-on reset pulse (“power-on reset pulse”) when the operating voltage is switched on, in order to set the computers in a defined state, the individual computers are further brought into a reset state by second reset pulses if the operating voltage falls below a predetermined minimum value ("undervoltage reset”), and each computer can be reset by one or more other computers by means of third reset pulses (reset can be set) if this computer is identified as working incorrectly by monitoring, in particular a multi-computer system for safety devices in motor vehicles, for example air bags or belt tensioners.
  • the invention also relates to a method for controlling a multi-computer system.
  • Multi-computer systems of the above type are known to be required for the rapid processing of large amounts of data in a short time, such as occur in the monitoring, control and regulation of processes or when data is retrieved from extensive files.
  • a plurality of computers are connected together in order to carry out the requirements, in that a mutual data exchange is carried out between them.
  • a particular area of application for such multi-computer systems is the control of safety systems in motor vehicles, such as anti-lock braking systems or passive restraint systems (for example inflatable gas cushions (airbags) which are automatically effective when the vehicle collides with an obstacle, or seat belts, which are tensioned at the moment of impact (belt tensioners)).
  • passive restraint systems for example inflatable gas cushions (airbags) which are automatically effective when the vehicle collides with an obstacle, or seat belts, which are tensioned at the moment of impact (belt tensioners)
  • the requirement for processing large amounts of data results from the fact that when the vehicle collides with an obstacle, the deceleration values run in the form of a curve having a maximum and minimum (crash curve) and the triggering time for the restraint systems in one by trying beforehand agreed exact time must be done.
  • the other point of view namely the need for data processing in the shortest possible time, follows from the short time span between the impact of the vehicle on the obstacle and the possibility of injury to the vehicle occupants. In this relatively short period of time, a complete recording of the course of the deceleration curve is required.
  • the computers of the multi-computer system be set to a defined state when switched on, regardless of whether the individual computers are working synchronously or asynchronously.
  • the defined states of the individual computers when the system is switched on are an indispensable prerequisite for safe operation.
  • each computer must be able to be reset by one or more other computers after it has been started up or after the multi-computer system has been put into operation in the above sense, if it is activated by a corresponding monitoring method or by a monitoring system is identified not working correctly.
  • the invention is intended to provide a method for correspondingly controlling a multi-computer system.
  • Another advantage is increased security. If a defect occurs in the one-piece control circuit common to all computers, all three of the functions addressed are disrupted, which is immediately noticeable. If, on the other hand, three separate circuits are used, malfunctions are difficult to detect if, for example, only one circuit is defective, while the * other two circuits are still working properly. This can result in a considerable safety risk in the passive restraint systems.
  • the common control circuit comprises a delay switch which takes effect when the operating voltage is switched on. device, the output of which is connected to the reset pulse inputs of the computers via an OR gate assigned to each computer.
  • the use of the delay circuit offers the advantage that all computers can be put together in a defined state at a point in time at which the operating voltage has stabilized at a constant value.
  • each computer is connected to the reset pulse inputs of the other computers via the OR elements already mentioned.
  • each computer can be reset by one or more other computers after the system has started up if it is identified as not working correctly by a corresponding monitoring method.
  • the already mentioned delay circuit is formed by a comparator, one input of which is supplied with a reference voltage lower than the operating voltage, and the other input of which is supplied with the operating voltage and via a charging resistor a charging capacitor is connected to ground.
  • the output of the comparator is in turn connected to the reset pulse inputs of the individual computers via a number of switching transistors that is equal to the number of computers.
  • This arrangement makes it possible not only to use the control circuit for generating the "power-on reset", but rather it is also possible to put all the computers in the reset state when the operating voltage falls below a certain predetermined value .
  • FIG. 1 shows a basic block diagram of a multi-computer system with two computers and a common control circuit
  • FIG. 2 shows a detailed circuit diagram of a control circuit according to FIG. 1.
  • the multi-computer system shown schematically in FIG. 1 comprises a control circuit 10 which is common to two computers 20, 22 and which controls these computers.
  • the control circuit 10 is used to process signals that are generated by the computers 20, 22.
  • the control circuit 10 comprises a delay circuit 14, to which the stabilized operating voltage u of the multi-computer system is supplied at terminal 12. Furthermore, the control circuit 10 has two OR gates 16 and 18, via which the output of the delay circuit 14 is connected to reset inputs 24 and 30 of the two computers 20, 22.
  • Each computer 20, 22 also has a reset output 26 or 28. Since after the start of the multi-computer system, each computer should be able to be reset by one or more other computers if it is identified as not working properly by a corresponding monitoring method, these are Reset outputs 26, 28 are provided which control the other computer 20, 22 via the two OR gates 16, 18.
  • FIG. 2 shows an example of the control circuit 10 shows.
  • the same terminals or connections from Fig. 1 are designated in Fig. 2 with the same reference numerals.
  • An essential component of the control circuit is a comparator 42 with the two inputs 74 and 76.
  • a voltage divider formed by the resistors 32 and 34, the tap of which is connected to the upper input 76 of the comparator.
  • a charging capacitor 36 is connected in parallel with the resistor 34.
  • the tapping point of the voltage divider 32, 34 is connected to the output of the comparator 42 via a further resistor 44.
  • a further voltage divider which is formed by a resistor 38 and a reference diode 40, and whose tap point is connected to the lower input 74 of the comparator 42 is also connected to the operating voltage U.
  • a stabilized voltage is formed by the reference diode 40, the value of which is lower than the operating voltage U, and which is at the input 74 of the comparator 42.
  • diodes 46 and 48 At the output of the comparator are two diodes 46 and 48 connected, which form the OR elements 16, 18 mentioned above in FIG. 1.
  • One diode 46 leads via a resistor 52 to the base of a first transistor 54, and furthermore the diode 46 is connected to the reset output 28 of the computer 22 via a capacitor 56, and the base of the transistor 54 is connected via a resistor 50 at the operating voltage U.
  • the other diode 48 is connected via a resistor 64 to the base of another transistor 68 and via a capacitor 66 to the reset output 26 of the computer 20.
  • the base of the further transistor 68 is also connected to the operating voltage U via a resistor 62.
  • the emitters of the two transistors 54 and 58 are connected directly to the operating voltage U, and a resistor 58 and a capacitor 60 lead from the collector of the transistor 54 to ground; accordingly, the collector of the other transistor 68 is connected to ground via a resistor 70 and a capacitor 72.
  • the end of the resistor 58 facing away from the collector of the transistor is also connected to the reset input 24 of the computer 20, and the end of the resistor 58 facing away from the collector of the other transistor 68 Resistor 70 to reset input 30 of further computer 22.
  • the potential at the upper input 76 of the comparator 42 rises more slowly as a result of the action of the charging capacitor 36 than the potential specified by the reference diode 40 at the lower input 74 of the comparator 42.
  • the output of the comparator 42 is at ground during a time period which is dependent on the dimensioning of the resistors 32, 34, 44, the charging capacitor 36 and the reference voltage of the reference diode 40, and thus switches the transistors 54 and 68 through.
  • the reset inputs 24 and 30 of the computers 20, 22 are approximately at the voltage potential of the operating voltage U.
  • the reference voltage of the reference diode 40 is approximately 2.5 V. If the voltage at the charging capacitor 36 now increases, the voltage at the upper input 76 of the comparator 42 exceeds the reference voltage of the reference diode 40, the transistors 54 and 68 are blocked by the switching up at the comparator output, and the capacitors 60 and 72 are discharged via the internal "pull-down" resistors of the reset inputs 24 and 30 the computers 20, 22, so that the computers are released for operation.
  • the delay time required to exceed the reference voltage specified by the reference diode 40 when the operating voltage U is switched on is approximately 30 ms, and the discharge time of the capacitors 60 and 72 via the internal pull-down resistors of the reset inputs 24 and 30 is of the order of a few microseconds (is).
  • the first time delay means that the computers 20, 22 of the multi-computer system are only set to a defined initial state after a certain start-up time, when the entire system has set itself to a stabilized initial state. The case described so far relates to the reliable generation of the "power-on reset".
  • the reset pulses are generated by interventions via the capacitors 56 and 66.
  • the reset output 28 of the computer 22 switches from the operating voltage to ground (if the computer 22 detects an error in the other computer 20 and wants to reset the computer 20)
  • the dynamic coupling of the capacitor 56 and the Resistor 52 of transistor 54 is briefly conductive, which triggers a reset pulse for computer 20.
  • the other reset output 26 of the computer 20 can be used to generate reset pulses for the computer 22 via the capacitor 66 and the resistor 64 and by means of the transistor 68.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)

Abstract

Dans un système à multicalculateur, notamment pour des dispositifs de sécurité dans des véhicules à moteur, par exemple coussins pneumatiques ou tendeurs de ceinture de sécurité, il est entre autres nécessaire de générer une remise à l'état initial ''marche'' lorsque le système est mis sous tension de fonctionnement, une remise à l'état initial de sous-tension lorsque la tension tombe au-dessous d'une valeur prédéterminée, et une remise à l'état initial de contrôle dans le cas d'un calculateur défectueux. Ces trois exigences sont satisfaites par un seul circuit d'attaque commun à tous les calculateurs du système à multicalculateur et comportant un comparateur, des éléments OU et des transistors de commutation. La mise en oeuvre d'un seul circuit d'attaque commun permet de réaliser le système à multicalculateur sous un encombrement minimal et d'en accroître la fiabilité.
PCT/DE1987/000533 1987-01-22 1987-11-20 Systeme a multicalculateur et son procede de commande WO1988005569A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3701735 1987-01-22
DEP3701735.7 1987-01-22

Publications (1)

Publication Number Publication Date
WO1988005569A1 true WO1988005569A1 (fr) 1988-07-28

Family

ID=6319277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1987/000533 WO1988005569A1 (fr) 1987-01-22 1987-11-20 Systeme a multicalculateur et son procede de commande

Country Status (2)

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DE (1) DE3790885D2 (fr)
WO (1) WO1988005569A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402144A2 (fr) * 1989-06-08 1990-12-12 Canon Kabushiki Kaisha Système de communication entre unités et méthode de remise à zéro
FR2658335A1 (fr) * 1990-02-15 1991-08-16 Bosch Gmbh Robert Systeme de calculateur, mis en óoeuvre dans des dispositifs de securite appliques aux vehicules automobiles.
WO1998050859A1 (fr) * 1997-05-06 1998-11-12 Telefonaktiebolaget Lm Ericsson Systeme electronique possedant un circuit de remise a zero integre a puce et dote d'un detecteur de pointe de tension
US6480967B1 (en) 1999-05-21 2002-11-12 Koninklijke Philips Electronics N.V. Multiple module processing system with reset system independent of reset characteristics of the modules
DE10329196A1 (de) * 2003-06-28 2005-01-20 Audi Ag Verfahren zum Reset von elektronischen Fahrzeug-Steuergeräten
WO2009052926A1 (fr) * 2007-10-26 2009-04-30 Pilz Gmbh & Co. Kg Dispositif de commande pour un système de commutation de sécurité à surveillance intégrée de la tension d'alimentation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2571872A1 (fr) * 1984-10-15 1986-04-18 Sagem Dispositif d'alimentation electrique de microprocesseurs
US4586179A (en) * 1983-12-09 1986-04-29 Zenith Electronics Corporation Microprocessor reset with power level detection and watchdog timer
EP0184758A2 (fr) * 1984-12-07 1986-06-18 Hitachi, Ltd. Dispositif pour le réglage d'hauteur d'un véhicule

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4586179A (en) * 1983-12-09 1986-04-29 Zenith Electronics Corporation Microprocessor reset with power level detection and watchdog timer
FR2571872A1 (fr) * 1984-10-15 1986-04-18 Sagem Dispositif d'alimentation electrique de microprocesseurs
EP0184758A2 (fr) * 1984-12-07 1986-06-18 Hitachi, Ltd. Dispositif pour le réglage d'hauteur d'un véhicule

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402144A2 (fr) * 1989-06-08 1990-12-12 Canon Kabushiki Kaisha Système de communication entre unités et méthode de remise à zéro
EP0402144A3 (fr) * 1989-06-08 1992-09-02 Canon Kabushiki Kaisha Système de communication entre unités et méthode de remise à zéro
US5511161A (en) * 1989-06-08 1996-04-23 Canon Kabushiki Kaisha Method and apparatus to reset a microcomputer by resetting the power supply
FR2658335A1 (fr) * 1990-02-15 1991-08-16 Bosch Gmbh Robert Systeme de calculateur, mis en óoeuvre dans des dispositifs de securite appliques aux vehicules automobiles.
WO1998050859A1 (fr) * 1997-05-06 1998-11-12 Telefonaktiebolaget Lm Ericsson Systeme electronique possedant un circuit de remise a zero integre a puce et dote d'un detecteur de pointe de tension
US6085342A (en) * 1997-05-06 2000-07-04 Telefonaktiebolaget L M Ericsson (Publ) Electronic system having a chip integrated power-on reset circuit with glitch sensor
AU739864B2 (en) * 1997-05-06 2001-10-25 Telefonaktiebolaget Lm Ericsson (Publ) Electronic system having a chip integrated power-on reset circuit with glitch sensor
CN1118023C (zh) * 1997-05-06 2003-08-13 艾利森电话股份有限公司 具有集成加电复位电路与瞬变干扰检测器的芯片的电子系统
US6480967B1 (en) 1999-05-21 2002-11-12 Koninklijke Philips Electronics N.V. Multiple module processing system with reset system independent of reset characteristics of the modules
DE10329196A1 (de) * 2003-06-28 2005-01-20 Audi Ag Verfahren zum Reset von elektronischen Fahrzeug-Steuergeräten
WO2009052926A1 (fr) * 2007-10-26 2009-04-30 Pilz Gmbh & Co. Kg Dispositif de commande pour un système de commutation de sécurité à surveillance intégrée de la tension d'alimentation

Also Published As

Publication number Publication date
DE3790885D2 (en) 1989-05-03

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