WO1988005569A1

WO1988005569A1 - Multicomputing system and process for driving same

Info

Publication number: WO1988005569A1
Application number: PCT/DE1987/000533
Authority: WO
Inventors: Wolfgang Drobny; Werner Nitschke; Peter Taufer; Hugo Weller
Original assignee: Robert Bosch Gmbh
Priority date: 1987-01-22
Filing date: 1987-11-20
Publication date: 1988-07-28
Also published as: DE3790885D2

Abstract

In a multicomputing system, in particular for safety devices in motor vehicles, for example air bags or safety-belt tensioners, it is necessary among other things to generate a power-on reset when the working voltage is switched on, an undervoltage reset when the working voltage falls below a predetermined value and a monitoring reset in case of faulty computations. These three requirements are met by a single driving circuit common to all computers of the multicomputing system and having a comparator, OR-means and switching transistors. By using a single common driving circuit, the multicomputing system can be built in a minimal space and its reliability is increased.

Description

Multi-computer system and method for controlling the multi-computer system

The invention relates to a multicomputer system, the individual computers of which are acted upon by a first switch-on reset pulse (“power-on reset pulse”) when the operating voltage is switched on, in order to set the computers in a defined state, the individual computers are further brought into a reset state by second reset pulses if the operating voltage falls below a predetermined minimum value ("undervoltage reset"), and each computer can be reset by one or more other computers by means of third reset pulses (reset can be set) if this computer is identified as working incorrectly by monitoring, in particular a multi-computer system for safety devices in motor vehicles, for example air bags or belt tensioners. The invention also relates to a method for controlling a multi-computer system.

Multi-computer systems of the above type are known to be required for the rapid processing of large amounts of data in a short time, such as occur in the monitoring, control and regulation of processes or when data is retrieved from extensive files. For this purpose, a plurality of computers are connected together in order to carry out the requirements, in that a mutual data exchange is carried out between them.

A particular area of application for such multi-computer systems is the control of safety systems in motor vehicles, such as anti-lock braking systems or passive restraint systems (for example inflatable gas cushions (airbags) which are automatically effective when the vehicle collides with an obstacle, or seat belts, which are tensioned at the moment of impact (belt tensioners)). In the case of passive restraint systems, for example, the requirement for processing large amounts of data results from the fact that when the vehicle collides with an obstacle, the deceleration values run in the form of a curve having a maximum and minimum (crash curve) and the triggering time for the restraint systems in one by trying beforehand agreed exact time must be done.

The other point of view, namely the need for data processing in the shortest possible time, follows from the short time span between the impact of the vehicle on the obstacle and the possibility of injury to the vehicle occupants. In this relatively short period of time, a complete recording of the course of the deceleration curve is required.

The requirement, which is important in practice, for an effective response of the restraint systems is offset by the same importance of reliable protection against a faulty triggering. If the restraint system is the inflatable gas cushion already mentioned, it can be incorrectly triggered at high speeds. cause considerable damage to the motor vehicle as a result of visual impairment and as a result of driver frightening. It must also be taken into account that the gas cushions have to be replaced after a false triggering, which is associated with not inconsiderable costs.

In order to prevent false triggering, the data evaluated by the individual computers in a multicomputer system must be constantly monitored so that one can anticipated false triggering can be corrected.

In this context, there is also a requirement that the computers of the multi-computer system be set to a defined state when switched on, regardless of whether the individual computers are working synchronously or asynchronously. In any case, the defined states of the individual computers when the system is switched on are an indispensable prerequisite for safe operation.

In addition, there are also the requirements that each computer must be able to be reset by one or more other computers after it has been started up or after the multi-computer system has been put into operation in the above sense, if it is activated by a corresponding monitoring method or by a monitoring system is identified not working correctly.

Finally, in the case of a multi-computer system, care must also be taken that the computers must be set to the so-called reset state if the operating voltage falls below a certain value. If the operating voltage drops below a predetermined value, the safe operation of the computer is no longer guaranteed, so that the risk of false tripping can be increased. stands. It is therefore necessary to reset the computers to a defined state in such a case.

In order to meet the above three important requirements - "power-on reset", reset pulse in the case of a faulty computer and "undervoltage reset" - in a multi-computer system, a considerable amount of circuitry is naturally required for the individual three functions. In conjunction with this, a relatively large space requirement for the individual circuits is disadvantageously recorded, as a result of which the overall system becomes more expensive. In practice, this fact can be of crucial importance, because the user often specifies a minimum space requirement for the entire system.

This is where the invention comes in, which is based on the task of creating a multi-computer system which meets the requirements with minimal effort and a small space requirement. In addition, the invention is intended to provide a method for correspondingly controlling a multi-computer system.

This object is achieved by the invention in the multi-computer system required in the preamble of claim 1 the characteristics specified in the characterizing part.

The basic idea of the invention of generating or processing the first, second and third reset pulses by means of a single control circuit common to all computers in the multi-computer system leads to a significant space advantage in comparison with known solutions, each with separate circuits work for the generation and processing of the individual reset pulses.

Another advantage is increased security. If a defect occurs in the one-piece control circuit common to all computers, all three of the functions addressed are disrupted, which is immediately noticeable. If, on the other hand, three separate circuits are used, malfunctions are difficult to detect if, for example, only one circuit is defective, while the ^* other two circuits are still working properly. This can result in a considerable safety risk in the passive restraint systems.

In an expedient embodiment of the invention, the common control circuit comprises a delay switch which takes effect when the operating voltage is switched on. device, the output of which is connected to the reset pulse inputs of the computers via an OR gate assigned to each computer.

The use of the delay circuit offers the advantage that all computers can be put together in a defined state at a point in time at which the operating voltage has stabilized at a constant value.

In another advantageous embodiment of the invention, the reset pulse output of each computer is connected to the reset pulse inputs of the other computers via the OR elements already mentioned. As a result, each computer can be reset by one or more other computers after the system has started up if it is identified as not working correctly by a corresponding monitoring method.

In an expedient embodiment of the invention, the already mentioned delay circuit is formed by a comparator, one input of which is supplied with a reference voltage lower than the operating voltage, and the other input of which is supplied with the operating voltage and via a charging resistor a charging capacitor is connected to ground. The output of the comparator is in turn connected to the reset pulse inputs of the individual computers via a number of switching transistors that is equal to the number of computers.

This arrangement makes it possible not only to use the control circuit for generating the "power-on reset", but rather it is also possible to put all the computers in the reset state when the operating voltage falls below a certain predetermined value .

Further advantageous embodiments of the invention result from the claims, the description and the drawing.

For a better understanding, the invention is explained in more detail below with reference to the embodiment shown in the drawing. Show it:

1 shows a basic block diagram of a multi-computer system with two computers and a common control circuit, and

FIG. 2 shows a detailed circuit diagram of a control circuit according to FIG. 1. The multi-computer system shown schematically in FIG. 1 comprises a control circuit 10 which is common to two computers 20, 22 and which controls these computers. In addition, the control circuit 10 is used to process signals that are generated by the computers 20, 22.

The control circuit 10 comprises a delay circuit 14, to which the stabilized operating voltage u of the multi-computer system is supplied at terminal 12. Furthermore, the control circuit 10 has two OR gates 16 and 18, via which the output of the delay circuit 14 is connected to reset inputs 24 and 30 of the two computers 20, 22.

Each computer 20, 22 also has a reset output 26 or 28. Since after the start of the multi-computer system, each computer should be able to be reset by one or more other computers if it is identified as not working properly by a corresponding monitoring method, these are Reset outputs 26, 28 are provided which control the other computer 20, 22 via the two OR gates 16, 18.

The mode of operation of the control circuit 10 common to all computers 20, 22 results from FIG. 2, which shows an example of the control circuit 10 shows. The same terminals or connections from Fig. 1 are designated in Fig. 2 with the same reference numerals.

An essential component of the control circuit is a comparator 42 with the two inputs 74 and 76. At the terminal 12 with the stabilized operating voltage U there is a voltage divider formed by the resistors 32 and 34, the tap of which is connected to the upper input 76 of the comparator. A charging capacitor 36 is connected in parallel with the resistor 34. In addition, the tapping point of the voltage divider 32, 34 is connected to the output of the comparator 42 via a further resistor 44.

A further voltage divider, which is formed by a resistor 38 and a reference diode 40, and whose tap point is connected to the lower input 74 of the comparator 42 is also connected to the operating voltage U. A stabilized voltage is formed by the reference diode 40, the value of which is lower than the operating voltage U, and which is at the input 74 of the comparator 42.

At the output of the comparator are two diodes 46 and 48 connected, which form the OR elements 16, 18 mentioned above in FIG. 1. One diode 46 leads via a resistor 52 to the base of a first transistor 54, and furthermore the diode 46 is connected to the reset output 28 of the computer 22 via a capacitor 56, and the base of the transistor 54 is connected via a resistor 50 at the operating voltage U.

The other diode 48 is connected via a resistor 64 to the base of another transistor 68 and via a capacitor 66 to the reset output 26 of the computer 20. The base of the further transistor 68 is also connected to the operating voltage U via a resistor 62.

The emitters of the two transistors 54 and 58 are connected directly to the operating voltage U, and a resistor 58 and a capacitor 60 lead from the collector of the transistor 54 to ground; accordingly, the collector of the other transistor 68 is connected to ground via a resistor 70 and a capacitor 72.

The end of the resistor 58 facing away from the collector of the transistor is also connected to the reset input 24 of the computer 20, and the end of the resistor 58 facing away from the collector of the other transistor 68 Resistor 70 to reset input 30 of further computer 22.

When the operating voltage is switched on by a switch (not shown here), the potential at the upper input 76 of the comparator 42 rises more slowly as a result of the action of the charging capacitor 36 than the potential specified by the reference diode 40 at the lower input 74 of the comparator 42. Thus, the output of the comparator 42 is at ground during a time period which is dependent on the dimensioning of the resistors 32, 34, 44, the charging capacitor 36 and the reference voltage of the reference diode 40, and thus switches the transistors 54 and 68 through.

Thus, the reset inputs 24 and 30 of the computers 20, 22 are approximately at the voltage potential of the operating voltage U. The reference voltage of the reference diode 40 is approximately 2.5 V. If the voltage at the charging capacitor 36 now increases, the voltage at the upper input 76 of the comparator 42 exceeds the reference voltage of the reference diode 40, the transistors 54 and 68 are blocked by the switching up at the comparator output, and the capacitors 60 and 72 are discharged via the internal "pull-down" resistors of the reset inputs 24 and 30 the computers 20, 22, so that the computers are released for operation. The delay time required to exceed the reference voltage specified by the reference diode 40 when the operating voltage U is switched on is approximately 30 ms, and the discharge time of the capacitors 60 and 72 via the internal pull-down resistors of the reset inputs 24 and 30 is of the order of a few microseconds (is). The first time delay means that the computers 20, 22 of the multi-computer system are only set to a defined initial state after a certain start-up time, when the entire system has set itself to a stabilized initial state. The case described so far relates to the reliable generation of the "power-on reset".

Furthermore, there is a requirement to put all computers in the reset state if the operating voltage U of, for example, 5 V falls below a certain value (for example 4.6 V). This requirement is also met by the comparator 42. If the operating voltage U becomes too low and thus the voltage potential at the upper input 76 falls below the voltage value of the reference voltage of the reference diode 40, the transistors 54 and 68 - as already described above - blocked. The reset inputs 24 and 30 thus reach the potential of the operating voltage U, ie the desired "undervoltage reset" results.

In the event that a computer identified as not working correctly is to be reset by one or more other computers in the system, the reset pulses are generated by interventions via the capacitors 56 and 66. For example, if the reset output 28 of the computer 22 switches from the operating voltage to ground (if the computer 22 detects an error in the other computer 20 and wants to reset the computer 20), the dynamic coupling of the capacitor 56 and the Resistor 52 of transistor 54 is briefly conductive, which triggers a reset pulse for computer 20. In a corresponding manner, the other reset output 26 of the computer 20 can be used to generate reset pulses for the computer 22 via the capacitor 66 and the resistor 64 and by means of the transistor 68. Capacitors 60 and 72, along with the internal pull-down resistors, determined the length of the dynamic reset pulses.

It can be seen with the control circuit shown in FIG. 2 that a power-on reset, an undervoltage Generate a reset and a monitoring reset. The dynamic coupling of the reset triggering from the computers 20, 22 prevents a permanent reset in the case of defective computers, which would block the computers working properly. An extension of the reset impulses in the case of very short reset triggers by the computers can prevent the computers from constantly resetting each other in the system cycle. With the new multi-computer system, it is in fact excluded that the pulse duration of the reset pulses is not sufficient to set all the registers of the computers internally in a defined state in an initial state.

Claims

Patent claims

1. Multi-computer system, the individual computers of which are supplied with a first switch-on reset pulse (“power-on reset pulse”) when the operating voltage is switched on, in order to set the computers in a defined state, the individual computers of which are also used second reset pulses are brought into a reset state when the operating voltage falls below a predetermined minimum value ("undervoltage reset"), and each computer can be reset (resetable) by one or more other computers by means of third reset pulses if this computer switches through monitoring is identified as working incorrectly, in particular multi-computer system for safety devices in motor vehicles, for example air bags or belt tensioners, characterized in that the computers (20, 22) are assigned a single common control circuit (10) which is connected to the switchable operating voltage (U) and which generates or processes the first, second and third reset pulses.

2. Multi-computer system according to claim 1, characterized in that the control circuit (10) comprises a delay circuit (14) which becomes effective when the operating voltage (U) is switched on, the output of which is assigned to each computer (20, 22) OR element (16, 18) with the reset pulse inputs (24, 30) of the computer (20, 22) is connected.

3. Multi-computer system according to claim 2, characterized ge indicates that the reset pulse output (26, 28) (at which a pulse occurs when the computer is faulty) of each computer (20, 22) via the OR gates (16, 18) with the reset pulse inputs (24, 30) of the respective other computer (20, 22) is connected.

4. Multi-computer system according to claim 2 and / or 3, characterized in that the delay circuit (14) is formed by a comparator (42), one input (74) of which is supplied with a reference voltage lower than the operating voltage, and whose other input (76) is connected to the operating voltage (U) via a charging resistor (32) and to ground via a charging capacitor (36).

5. Multi-computer system according to claim 4, characterized in that the output of the comparator is connected to the reset pulse inputs (24, 30) of the computer via a number of computers equal to the number of switching transistors (54, 68).

6. A multi-computer system according to claim 5, characterized in that the base of each switching transistor (54, 68) has a first resistor (50; .62) with the operating voltage (U) and a series connection of a second resistor (52; 64 ) and a capacitor (56; 66) is connected to the reset pulse outputs (28, 30) of the assigned computers.

7. Multi-computer system according to claim 6, characterized ge indicates that the output of the comparator (42) via a diode (46, 48) and via the second resistor (52; 64) controls the bases of the switching transistors (54, 68) whose collectors have load resistors (58; 70) with the reset pulse inputs

(24, 30) the computers are connected.

8. Method for controlling a multi-computer system with first switch-on reset pulses (“power-on reset”), with second reset pulses (undervoltage reset) occurring when the operating voltage drops and with third reset pulses generated by a faulty computer , in particular multi-computer system for safety devices in motor vehicles, for example Air bags or belt tensioners, characterized in that all the reset pulses mentioned are generated or processed in a single control circuit (10) common to the computers (20, 22).

9. Use of the multi-computer system and the method in a safety device with air bags in motor vehicles.