WO1988002210A1 - Dispositif d'isolation electrique - Google Patents

Dispositif d'isolation electrique Download PDF

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Publication number
WO1988002210A1
WO1988002210A1 PCT/AU1987/000313 AU8700313W WO8802210A1 WO 1988002210 A1 WO1988002210 A1 WO 1988002210A1 AU 8700313 W AU8700313 W AU 8700313W WO 8802210 A1 WO8802210 A1 WO 8802210A1
Authority
WO
WIPO (PCT)
Prior art keywords
low voltage
package
electrical isolation
connecting pins
voltage connecting
Prior art date
Application number
PCT/AU1987/000313
Other languages
English (en)
Inventor
Graham John Rogers
Original Assignee
Baysage Pty. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Baysage Pty. Ltd. filed Critical Baysage Pty. Ltd.
Publication of WO1988002210A1 publication Critical patent/WO1988002210A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/292—Modifications for introducing a time delay before switching in thyristor, unijunction transistor or programmable unijunction transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/79—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar semiconductor switches with more than two PN-junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262—Arrangements for regulating voltages or for using plural voltages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10446—Mounted on an edge
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Definitions

  • the present invention relates to electrical isolation devices, and in particular, to devices suited to provide adequate electrical isolation under predetermined conditions between consumer mains supplies of the order of 240 volts AC and low voltage control supplies (of the order of 10 volts).
  • Means for isolation between main supply and control circuit supplies are known.
  • One of the earliest forms involves the use of an electromechanical relay.
  • the coil is arranged to operate on either the high or the low voltage and the contacts operated by the relay coil are arranged to operate on the corresponding low or high voltage.
  • an electromechanical relay may be sufficient.
  • the relay does suffer from a number of drawbacks. These include:
  • the relay is susceptible to vibration
  • the relay characteristics can vary with temperature and age
  • the relay is susceptible to electrical leakage particularly in the smaller sizes and where the humidity or moisture level is relatively high;
  • the relay can be relatively bulky for the electrical isolation it affords.
  • An advantage of the relay is that it is relatively insensitive to electrical noise.
  • isolation device of the present invention is in amusement equipment, for example fairground games, video games and arcade games.
  • This form of equipment typically requires coin operation.
  • relay operated devices have formed part of the coin operation mechanism.
  • these relay devices suffer from certain disadvantages. Instances have been known in recent times where these devices have failed in such a way that electrocution of users of the device has resulted.
  • an isolation device which is simple, inexpensive, compact and preferably provides improved performance over the previously used relay based coin operation mechanisms, such device also providing the required electrical isolation under all necessary conditions and being capable of approval by the relevant safety and electrical authorities.
  • an electrical isolation assembly comprising a circuit board, an isolator device having high electrical isolation between high and low voltage terminals, sai d isolator device having a plurality of low voltage connecting pins located along a first edge and a plurality of high voltage connecting pins located along a second edge parallel to and opposite said first edge of said isolator device, certain ones of said high and low voltage connecting pins connected in an electrically conductive manner to electrically conductive tracks located on a surface of said circuit board and an elongate slot cut in said board; said isolator device located on said board so that said high and low voltage connecting pins are located on respective opposite elongate sides of said elongate slot; and wherein the minimum creep distance between respective ones of said high and low voltage connecting terminals is at least 8.0mm; and wherein the minimum distance between respective ones of said high and low voltage connecting terminals is at least 10.7mm.
  • the minimum creep distance is at least 8.2mm.
  • an electrical isolation assembly comprising a circuit board and at least one opto-isolator integrated circuit package having high electrical isolation between high and low voltage terminals thereon, said opt-isolator package having a plurality of low voltage connecting pins along a first surface and a plurality of high voltage connecting pins along a second surface; said opto-isolation package mounted on said circuit board so that said high and low voltage connecting pins are located on respective opposite elongate sides of an elongate slot cut in said board; the minimum width across said slot being at least 2.7mm, said slot being at least 16mm in length when located symmetrically beneath a standard IC DIP package.
  • the minimum width across said slot is 4mm.
  • the said slot is at least 16mm in length when located symmetrically beneath an MOC 3021 IC DIP package or other opto-isolator package of equal dimension.
  • the above electrical isolation assembly includes additional opto-isolator integrated circuit packages lying in line with said package, the longitudinal separation between ends of said packages being at least 8mm, said additional packages otherwise installed in the same manner as the above package.
  • the electrical isolation assembly includes additional packages lying in adjacent rows beside said package, said additional packages in said adjacent rows being separated from said package by an additional longitudinal slot cut in said board, said additional slot being at least 2.7mm in width, said additional packages otherwise being installed in the same manner as the package above described.
  • said additional slot is at least 4mm wide.
  • each said package or additional package is approximately 8mm long and approximately 6mm wide, with connecting pins lying along the longer sides.
  • said longitudinal slot beneath said package extends at least 4mm beyond both ends of said package.
  • the maximum voltage applied to the circuit on said board is in the range 120 volts (RMS) to 420 volts (RMS) at a frequency generally in the range 45 Hz to 65 Hz and more preferably in the range 50 Hz to 60 Hz.
  • a circuit comprising opto isolation means having high and low voltage connecting pins, said opto isolation means having conduction disable means operable during a predetermined period of time connected between a first one of said low voltage connecting pins, said opto isolation means having logical power supply means connected to a second one of said low voltage connecting pins, said logical power supply means arranged to supply power for a predetermined period of time to said second one of said low voltage connecting pins.
  • Preferably said predetermined period of time relating to said disable means is greater than said predetermined period of time relating to said logic power supply means.
  • Fig. 1 is a schematic diagram of a solid state electrical isolation device according to a preferred embodiment
  • Fig. 2 is a plan view of the underside of part of the circuit board incorporating the preferred embodiment.
  • Fig. 3 is a timing diagram illustrating the operation of the preferred embodiment.
  • Fig. 4 is a plan view of the top of a circuit board incorporating a plurality of isolator chips, laid out in accordance with a preferred embodiment of the present invention.
  • Fig. 1 there is shown two 555 timers IC1 and IC2 controlling an opto-isolator circuit IC3.
  • the low voltage circuit performs two functions:
  • IC1 provides an enable signal to the IC3 for a predetermined time after the coin operation switch is operated by a coin.
  • the component values and connections are arranged so that IC1 provides a predetermined ON time of approximately 60 seconds and IC2 provides an initial disable signal of approximately 70 seconds after power up.
  • the circuit of Fig. 1 is arranged so that the whole assembly is supplied with mains power at 240 volts AC.
  • a step down transformer T1 by means of suitable regulation circuitry provides 12 volt DC regulated input for the low voltage control circuit.
  • the same 240 volt AC supply is also connected by means of the TRIAC TC1 to a motor load or equivalent.
  • IC2 is arranged so that, upon turn on, PIN3 is high. Approximately 70 seconds later IC2 times out and PIN3 goes low. At this stage, if PIN3 of IC1 were to go high then a supply becomes available to PIN1 of IC3 which then connects via PIN2 of IC3 through diode Dl and via PIN3 of IC2 to common.
  • PIN 3 of ICl goes high when the coin switch is operated (by insertion of a coin in the machine). Upon insertion of a coin PIN3 goes high for a period of approximately 60 seconds i.e. for the intended predetermined period of operation of the machine.
  • TRIAC TCI is gated on by means of conduction through terminals 6 and 4 of IC3.
  • IC2 operates much more quickly than IC3. i.e. The rise time of the signal at terminal 3 of IC2 is much faster than the rise time of the output signal at terminal 4 of IC3. By-virtue. of this timing relationship, upon initial power up, IC2 will always inhibit IC3 (high on terminal 3 of IC2) before IC3 can gate TRIAC TC1 on).
  • terminal 3 of IC2 goes low, allowing IC3 to be enabled.
  • Opto-isolator circuit IC3 provides nominal 7.5kV isolation between its high and low voltage sides. To ensure this isolation is maintained once the integrated circuit is actually placed onto a circuit board, certain circuit board design constraints must be considered.
  • the integrated circuit placement and track layout therein disclosed has been found advantageous in maintaining the necessary electrical isolation even under conditions of high humidity and condensation on the board.
  • the parameters adopted are greater in magnitude than those usually specified.
  • IC3 has been located near an edge of the board with the high and low voltage pin pads stradling a slot of length 1 and width wl cut out of the board. Pins 1, 2, 4 and 6 of IC3 are shown connected to solder pads.
  • dimension 1 is 16mm and wl is at least 2.7mm, preferably 3mm and more preferably 4mm.
  • the distance w2 between the high and low voltage pins of IC3 is at least 10.7mm.
  • the creep distance being the minimum distance between any high and low voltage pad is at least 8mm and preferably 8.2mm.
  • the slot width wl is extended to be equal to w2. Tests on a circuit board prototype built using the dimensions and the circuit of the preferred embodiment disclosed above have exhibited an isolation of at least 7kV under required conditions of humidity and temperature.
  • the slot should be located symmetrically beneath the opto-isolator chip as generally shown in Fig. 2.
  • TRIAC TCI is rated at 15 amps, 400 volts with gate turn on current of 50mA (SC151D).
  • the opto-isolated TRIAC driver, IC3 is an M0C3021 TRIAC driver chip rated 7.5kV isolation.
  • MOC3021 The dimension of MOC3021 is approximately 8mm in length by 6mm in width by approximately 3mm in thickness (exluding pins). In general terms it is required that the slot extend 4mm beyond either end of the IC package. For this particular chip the slot length, when located symmetrically beneath the chip, is therefore 4mm plus 8mm plus 4mm equals 16mm.
  • the slot 13 should extend continuously with the chips all stradling the slot.
  • the minimum separation distance between chip ends is 8mm.
  • the slot width should be as previously specified, namely at least 2.7mm and most preferably 4mm or greater.
  • a separation slot 15 should be included which separates the rows of integrated circuit chips from each other, i.e. separates chips 10, 11 and 12 from chips 16, 17 and 18.
  • the above dimensions and isolation characteristics apply particularly for situations where the maximum voltage likely to be applied to the isolation device lies in the range 120 volts (RMS) to 420 volts (RMS) and being within the frequency range approximately 45 Hz to 65 Hz.
  • the isolator chip is a 6 pin DIL package located on a fibreglass circuit board of thickness in the range 0.3mm - 1mm and being sealed with an epoxy resin based sealant.
  • V is maximum RMS volts applied to the high voltage device activated by the isolator chip
  • F is frequency of V in cycles per second.
  • the isolation circuit of the present invention clearly has application in any environment which requires use of integrated circuit devices having high resistance to noise, high electrical isolation between high and low voltage circuits, and arranged to fail in the OFF condition.
  • the embodiments of the present invention can also be used to drive flood lamps, three phase motors and various household appliances (particularly where maximum current requirement is less than 16 amps at 240 volts AC).
  • the preferred embodiment is also suitable for encapsulation.
  • circuit of the present embodiment can be adapted and repeated threefold.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un dispositif d'isolation électrique et un circuit monté sur une carte de circuit sert à établir une isolation d'au moins 7kV entre des composants à basse tension (de l'ordre de 10 à 50 V) et des composants à haute tension (de l'ordre de 120V CA à 420V CA) montés sur la carte de circuit ou autres. On obtient l'isolation en partie en prévoyant dans la carte de circuit un interstice (13) de dimensions déterminées situé sous les puces (10, 11, 12) d'isolation du circuit intégré. Un circuit de commande logique particulier à basse tension pour une puce du circuit de commande à Triac à opto-isolation (IC3) est également décrit, ladite puce comportant des broches de connexion à haute et basse tension et un organe d'opto-isolation pourvu d'un organe (IC2) d'invalidation de la conduction pouvant fonctionner durant un temps prédéterminé et connecté entre la première des broches de connexion à basse tension. L'organe d'opto-isolation comprend un organe logique d'alimentation connecté à la deuxième des broches de connexion à basse tension (broche 2 de IC3). L'organe logique d'alimentation (IC1) est destiné à alimenter pendant un temps prédéterminé la deuxième (broche 1 de IC3) des broches de connexion à basse tension. Ledit dispositif sert en particulier de circuit de remplacement à semi-conducteur pour des mécanismes à relais de machines à sous, telles qu'on les utilise dans les foires et analogues.
PCT/AU1987/000313 1986-09-15 1987-09-15 Dispositif d'isolation electrique WO1988002210A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AUPH8046 1986-09-15
AU804686 1986-09-15

Publications (1)

Publication Number Publication Date
WO1988002210A1 true WO1988002210A1 (fr) 1988-03-24

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PCT/AU1987/000313 WO1988002210A1 (fr) 1986-09-15 1987-09-15 Dispositif d'isolation electrique

Country Status (1)

Country Link
WO (1) WO1988002210A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390662A (en) * 1992-03-02 1995-02-21 Fuji Photo Optical Co., Ltd. Electronic endoscope apparatus using circuit board having cavity

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1084155A (en) * 1955-07-22 1956-01-26 Acf Industries, Incorporated Improvements relating to the insertion of modules in printed circuits
GB1190554A (en) * 1966-12-03 1970-05-06 Int Computers Ltd Improvements in or relating to Electrical Circuit Structures.
US3708672A (en) * 1971-03-29 1973-01-02 Honeywell Inf Systems Solid state relay using photo-coupled isolators
US3816763A (en) * 1972-10-02 1974-06-11 Gen Electric Zero voltage switching photon coupled relay
US3866051A (en) * 1973-02-01 1975-02-11 Xerox Corp Digital interface module
GB2004127A (en) * 1977-09-12 1979-03-21 Thomson Csf A device for interconnecting microcircuits
US4222516A (en) * 1975-12-31 1980-09-16 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Standardized information card
JPS60182780A (ja) * 1984-02-29 1985-09-18 Fujitsu Ltd 光部品の構造
JPS6116594A (ja) * 1985-06-21 1986-01-24 株式会社日立製作所 半導体装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1084155A (en) * 1955-07-22 1956-01-26 Acf Industries, Incorporated Improvements relating to the insertion of modules in printed circuits
GB1190554A (en) * 1966-12-03 1970-05-06 Int Computers Ltd Improvements in or relating to Electrical Circuit Structures.
US3708672A (en) * 1971-03-29 1973-01-02 Honeywell Inf Systems Solid state relay using photo-coupled isolators
US3816763A (en) * 1972-10-02 1974-06-11 Gen Electric Zero voltage switching photon coupled relay
US3866051A (en) * 1973-02-01 1975-02-11 Xerox Corp Digital interface module
US4222516A (en) * 1975-12-31 1980-09-16 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Standardized information card
GB2004127A (en) * 1977-09-12 1979-03-21 Thomson Csf A device for interconnecting microcircuits
JPS60182780A (ja) * 1984-02-29 1985-09-18 Fujitsu Ltd 光部品の構造
JPS6116594A (ja) * 1985-06-21 1986-01-24 株式会社日立製作所 半導体装置

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Circuits for Electronics Engineers", Edited by S. WEBER, published 5 May 1981 (05.05.81) by McGraw-Hill Publications Co., see pages 359, 254-255. *
DERWENT ABSTRACT, Accession No. 86-065252/10; & JP,A,61 016 594 (HITACHI K.K.) 24 January 1986 (24.01.86). *
J. MARKUS, "Modern Electronic Circuits Reference Manual", published 22 September 1983 (22.09.83) see pages 1099 and 1082. *
PATENT ABSTRACTS OF JAPAN; & JP,A,60 182 780 (FUJITSU K.K.) 18 September 1985 (18.09.85) (Also corresponding Derwent Abstract Accession No. 85-272182/44). *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390662A (en) * 1992-03-02 1995-02-21 Fuji Photo Optical Co., Ltd. Electronic endoscope apparatus using circuit board having cavity

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