WO1987001531A1 - Recepteur de frequence radio numerique - Google Patents

Recepteur de frequence radio numerique Download PDF

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Publication number
WO1987001531A1
WO1987001531A1 PCT/US1986/001764 US8601764W WO8701531A1 WO 1987001531 A1 WO1987001531 A1 WO 1987001531A1 US 8601764 W US8601764 W US 8601764W WO 8701531 A1 WO8701531 A1 WO 8701531A1
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WO
WIPO (PCT)
Prior art keywords
signal
digital
band
sampled
wide
Prior art date
Application number
PCT/US1986/001764
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English (en)
Inventor
Robert Vincent Janc
Steven Charles Jasper
Lester Anderson Longley
Katherine Helen Lambert
William Joseph Turney
Ross James Lillie
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to KR870700384A priority Critical patent/KR880700532A/ko
Publication of WO1987001531A1 publication Critical patent/WO1987001531A1/fr
Priority to DK184287A priority patent/DK184287D0/da
Priority to FI871897A priority patent/FI85076C/fi

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/24—Homodyne or synchrodyne circuits for demodulation of signals wherein one sideband or the carrier has been wholly or partially suppressed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2245—Homodyne or synchrodyne circuits using two quadrature channels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/005—Analog to digital conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0052—Digital to analog conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques

Definitions

  • This invention relates to the field of radio communications and specifically to a radio frequency receiver which is substantially implemented with digital circuitry.
  • An additional advantage of a digital receiver structure is that the DSP and IF circuitry can be designed so that it can be "reversed” to perform the corresponding operations for a digitally implemented transmitter. For half-duplex operation, the circuitry might be switched so that it simply reverses "direction," while for full-duplex operation two IF filters would be needed.
  • the primary technology contribution leading to the feasibility of a substantially digital receiver is a high-speed (20-100 MHz), high-resolution (10-12 bits) A/D converter.
  • a secondary factor leading to the technical feasibility of a digital receiver structure is the high level of integration and high speeds attainable in VLSI IC implementations, ultimately permitting, for example, a
  • the present invention combines these new technologies with improved techniques for front-end analog processing and digital IF filtering to achieve a feasible design for a substantially digital receiver.
  • the receiver structure of the present invention permits a revolutionary change in the manufacturing technology and operating characteristics of mobile radios. Furthermore, this approach permits a radio to be built with a minimal number of parts, which at once reduces parts and manufacturing costs, while also improving radio reliability and serviceabilty.
  • the present invention contemplates an all digital radio receiver which operates on a received R.F signal which is converted to a digital form after preselection at the output of an antenna.
  • the receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and general-purpose digital signal processor (DSP) integrated circuits performing final selectivity or equalization, demodulation, and post-demodulation processing.
  • A/D analog-to-digital
  • IF intermediate-frequency
  • DSP general-purpose digital signal processor
  • Figure 1 is a block diagram showing the functions of the digital receiver of the present invention.
  • Figure 2 is a schematic diagram of the front-end circuitry of the digital receiver of the present invention.
  • Figure 3 is a block diagram of the digital zero I.F. selectivity section of the present invention.
  • Figure 4a is a schematic and block diagram of the digital oscillator referenced in Figure 1.
  • Figure 4b is a schematic diagram of a pseudorandom dither generator compatible with the digital zero I.F. selectivity section of Figure 3.
  • Figure 5a is a block diagram of a desired "fast", narrowband lowpass filter.
  • Figure 5b is a block diagram of a decomposed approximation to the fast lowpass filter of Figure 5 a.
  • Figures 6a through 6d are frequency diagrams detailing the characteristics of the fast lowpass filters of Figure 5.
  • Figure 7 is a schematic diagram of the second-order narrowband lowpass infinite-impulse-response (IIR) filter used in the decomposed "fast" lowpass filters of Figure 5b.
  • Figure 8 is a schematic diagram of the second-order finite-impulse-response
  • FIGS 9a through 9c are schematic diagrams of the time-division-multiplexed second-order lowpass IIR filter used in the time-division-multiplexed "slow" lowpass filters described in conjunction with
  • Figure 10 is a block diagram of the fifth-order lowpass FER filter used to further reduce the sampling rate from 80 to 40 kHz.
  • Figure 11 is a block diagram of the fourth-order lowpass IIR filter used for final selectivity and passband equalization, prior to demodulation.
  • FIG. 12 is a block diagram of an FM demodulator implemented with a general purpose DSP.
  • Figures 13a through 13c are diagrams-detailing the principles of phasors in the context of the present invention.
  • Figures 14a and 14b are flow diagrams detailing the operation of the background routine of the FM demodulator of the present invention.
  • Figures 15a through 15b are flow diagrams of the operation of the scale routine described in conjunction with Figure 15a.
  • Figures 16a through 16c are flow diagrams detailing the operation of the remaining portions of the digital demodulator of the present invention.
  • Figure 1 illustrates the functions of a digital receiver, comprising three major operations. While the diagram shows no example of receiver diversity, it will be obvious to one skilled in the art that various diversity approaches could be applied for use in a receiver of the present invention.
  • the "front-end" section 104 which is further detailed in Figure 2, interfaces an antenna 102, receiving an analog radio-frequency (RF) signal, to the digitally implemented EF selectivity section 110.
  • the preselector 106 provides wideband filtering of the incoming signal, to prevent aliasing in the subsequent A/D conversion process.
  • the A/D block 108 includes the gain and sample-and-hold operations necessary for the digital processing of the present receiver structure.
  • EF selectivity section 110 provides a quadrature local oscillator (LO) 116 which generates a complex exponential signal (quadrature signals sine and cosine). The frequency of this signal is selected by the system channel frequency input "A".
  • the quadrature mixers 112 use digital multipliers to frequency-shift the desired narrowband channel down to the EF frequency of approximatly zero Hz.
  • the high-speed selectivity section 114 includes several cascaded narrowband lowpass filter sections, which remove undesired signals at higher frequencies from the desired signal which is centered near zero frequency. This lowpass filtering permits gradual sampling rate reduction from the high rates at the output of the A/D convener
  • the "back-end” section 120 is used to "specialize" the general-purpose radio structure into one specifically tailored to a particular radio application, designated by a system radio-type input "B". Its best implementation may comprise a general-purpose digital signal processor (DSP).
  • DSP digital signal processor
  • the final selectivity section 124 provides any additional filtering needed prior to demodulation of the radio signal in accordance with the type of modulation and channel characteristics. For example, it may provide adaptive channel equalization for a digital data communications system.
  • This filter section 124 also provides adjacent channel attenuation , and passband equalization to compensate for imperfections in the characteristics of the high-speed selectivity filters 114, resulting from the coarse coefficient quantization needed to implement multiplierless (lowpass) filters.
  • the demodulation section 126 may be software-programmed to implement many types of demodulation, including FM demodulation for voice and frequency-shift-keyed (FSK) data.
  • the demodulated voice signal may be converted back to analog form, then amplified and played through a loudspeaker, as suggested by icons 121 and 122.
  • a digital voice message may be stored in digital a digital memory 123 for later playback.
  • the demodulated data symbols may be routed to a computer for further processing or to a computer terminal for immediate display.
  • control information to implement automatic frequency tracking 128 may be generated in the "back-end" section 120.
  • a clock-generation section 118 is required to control the input sampling rate of the A/D conversion as necessary for accurate down conversion, to operate the digital circuitry in a regular fashion, and to control the output sampling rate, perhaps for synchronizing with subsequent systems.
  • the sampling rate f s is taken to be 20 MHz, and the band of frequencies to be received is centered at approximately 875 MHz.
  • FIG. 2 is a schematic diagram of the front end circuitry of the digital receiver of the present invention.
  • This circuitry functions to digitize a selected band of radio frequency signals.
  • the present invention provides that sampling is done directly at R.F. frequencies. However, wideband pre-selection is provided by R.F. analog filters prior to sampling.
  • the function of the R.F. filters 202 and 206 is to provide selectivity to spurious responses. These spurious responses included the image, half I.F. spurs, Able-Baker spurs, etc. as found in a conventional receiver front-end. In addition to these spurs, selectivity must be provided to frequencies which can be aliased by the sampling process.
  • the receiver of the present invention provides an R.F. amplifier 204 having a gain of approximately 28 dB and a noise figure of approximately 5 dB.
  • Clock 212 and sampling pulse generator 210 provide clock signals and sampling pulses to the first sample and hold 208, second sample and hold 220, the analog to digital converter 222, and the digital zero-EF selectivity section (not shown). Clock generation may be accomplished by a 20 MHz crystal oscillator, which is widely available.
  • a 40 MHz signal for use by the digital signal processor (not shown) is derived by doubling the 20 MHz signal by an analog doubling circuit
  • the pulse generator 210 is used to shape the 20 MHz clock signal (an approximate sinusoid) into very narrow pulses.
  • the width of the sampling pulse depends on the highest frequency band desired to be received. A pulse width of approximately 300 psec. will generate a "comb" of harmonics with approximately uniform amplitude to approximately 1 GHz. This is necessary for operation at the operating frequency of approximately 875 MHz of the receiver of the present invention.
  • Pulse generation may be accomplished using a conventional step recovery diode and ringing circuit A circuit of this type is described in a publication entitled Harmonic Generation Using Step Recovery Diodes and SRD modules,
  • Hewlett Packard Application note #920 available from Hewlett Packard Microwave Semiconductor Division, 350 Trimble Rd., San Jose, Ca., 95131.
  • the band of signals amplified and selected by blocks 202, 204, and 206 is sampled by the first sample and hold 208.
  • This is analogous to down-converting in a conventional R.F. receiver.
  • a flash analog-to-digital converter effectively samples the signal
  • practical conveners have bandlimited inputs, thus requiring sampling prior to conversion.
  • all known high resolution (> 10 bits) high speed converters utilize a two-step conversion process. This type of converter necessitates the use of a second sample and hold circuit 220. Double sampling is necessary to overcome the practical limitations of acquisition time, accuracy, and droop.
  • the first sample and hold must acquire extremely fast in the range of 300 psec in the receiver of the present invention.
  • the first sample and hold (208) may be implemented according to conventional techniques using a Schottky diode bridge and a dual gate MOS FET as the buffer amplifier.
  • the second sample and hold may be realized using a Schottky diode bridge, with additional back biasing to limit droop in the hold mode.
  • a high speed amplifier consisting of J-FETS in differential configuration as inputs and high dynamic range bipolar followers serves as a buffer amplifier.
  • Wideband amplifier 209 is necessary to further amplify the signal in order to overcome the quantization noise of the analog to digital converter.
  • the amplifier 209 is used to amplify a sampled signal; hence it must be wideband. High dynamic range is also necessary to prevent amplifier nonlinearities from distorting the signal.
  • the amplier 209 noise figure is dependent on the amount of "takeover" gain provided by R.F. amplifier 204 and overall noise requirements for sensitivity.
  • a Motorola MHW591 CATV wideband amplifier is suitable for use as the wideband amplifier with the 800 MHz receiver of the present invention.
  • a dither signal 218 is added to the sampled signal at combiner/isolator 214.
  • the combiner/isolator helps prevent nonlinearities present in the wideband amplifier and dither source from translating the low passed noise to other frequencies.
  • the purpose of the dither 218 is to uniformly spread quantization noise of the analog-to- digital converter. The uniform spreading of the noise floor over the Nyquist bandwidth prevents intermodulation distortion caused by quantizing from being an inherent problem, and also allows signal recovery below the least significant bit level, thus reducing gain requirements before the A/D converter and easing the problems caused by non-linearities in the stages preceding the converter.
  • the dither signal 218 must be added before the second sample and hold 220 if a two-step converter is used since the signal must be held constant during the conversion period.
  • the dither source 218 can be realized by using an analog noise source such as a noise diode.
  • an analog noise source such as a noise diode.
  • Noise added to the signal should be spectrally isolated from the information.
  • the sampling performed in the 800 MHz receiver of the present invention places the information approximately between 3 and 7 MHz.
  • Low pass filter 216 prevents noise from being added to the information signal.
  • the receiver of the present invention is provided with a 5-pole elliptic filter with a 1.5 MHz cutoff frequency for low-pass filter 216.
  • the average voltage level of the dither signal over the noise equivalent bandwidth of the low pass filter 216 should be greater than approximately 5 step sizes of the analog to digital converter. Care must be exercised to prevent the dither signal from causing clipping at the A/D converter 222.
  • the analog-to-digital converter 222 converts the analog signal to a digital signal.
  • the converter must be capable of accepting signals over the dynamic environment of the intended receiver application.
  • the two factors of prime importance of the analog to digital converter 222 are sampling speed and step size.
  • the step size determines the amount of gain necessary prior to the converter in order to take over the quantization noise floor. The larger the step size, the larger the gain requirement. Large amounts of gain result in nonlinear effects prior to the converter. Conversion speed is also very important since this determines the allowable bandwidth of the front-end filters, and also reduces the gain requirement by spreading the quantization noise over a larger bandwidth.
  • An analog to digital converter 222 satisfactory for use with the 800 MHz digital receiver of the present invention is a two-step 10-bit converter with a step size of approximately 3 mV, which is capable of converting at rates greater than 50 MHz.
  • a front end gain of approximately 54 dB is necessary to realize a post detection signal to noise ratio of approximately 10 dB in a receiver having a 30 kHz bandwidth when receiving a 0.3 ⁇ v signal sampled at a 20 MHz rate.
  • the large amount of gain necessary prior to converter 222 limits the nonlinear performance of the system.
  • Intermodulation ratio (IMR) is limited to approximately 65 dB which is somewhat less than that achievable by conventional receivers.
  • a digital zero-EF selectivity section (DZISS) compatible with the practice of the present invention is depicted in block diagram form.
  • the digital zero-IF selectivity section is disposed between the front-end circuitry 200 of Figure 2 and the backend DSP 120 of Figure 1, and it operates to convert the modulated digital RF signal output by front end 200 to the baseband signal processed by the backend DSP 120.
  • the DZISS 300 is comprised of an in-phase mixer 304, a quadrature-phase mixer 306, a digital quadrature local oscillator (L0) 302 (providing an in-phase L0 signal 309 and a quadrature phase L0 signal 311), two "fast” digital lowpass filters 308 and 310, two “slow” digital lowpass filters 312 and 313, and a clock source (not shown).
  • L0 digital quadrature local oscillator
  • L0 digital quadrature local oscillator
  • the actual length of the digital word used in any given application is dependent upon many factors, including: the resolution required, the dynamic range required and the frequency of sampling the received RF signal. For example, a word length of 12 bits is considered to have an acceptable performance in receiving a typical radio signal sampled at 20MHz.
  • Mixers 304 and 306 have as a second input quadrature L0 lines 309 and 311, respectively.
  • the L0 signals are not single connections, but are multi-bit discrete time representations of signals that are 90 degrees apart in phase (i.e., sine and cosine waveforms).
  • Mixers 304 and 306 perform arithmetic multiplications of the A/D input word and the L0 word, rounding the result to form an output word that is applied from the output ports of mixers 304 and 306 to the input ports of digital lowpass filters 308 and 310, respectively.
  • the digital word lengths of the L0 and mixer output signals may be selected to yield acceptable noise performance. As the digital word is lengthened, more quantization levels are available to represent the signals.
  • the quadrature mixing performed by multipliers 304 and 306 acts to frequency-translate the desired signal to a center frequency of approximately zero Hz, where the amount of frequency translation maybe determined by channel frequency control 305.
  • the resultant quadrature signal may then be lowpass filtered to remove out-of-band noise and undesired signals.
  • this selectivity is provided in two stages. The first stage is formed by fast recursive digital filter sections 308 and 310. Digital filters 308 and 310 are identical in structure and may be formed from a recursive filter topology which will be described below in greater detail. The remaining selectivity is provided by "slower" recursive filters 312, and 313, respectively. This choice of architecture will be discussed in more detail below. Following the filtering process, the digital signals are output to a backend DSP 120 for further processing.
  • Figure 4a is a schematic and block diagram of the digital oscillator described in conjunction with Figure 3.
  • the function of the quadrature oscillator is to provide digitized, sampled versions of the cosine and sine waveforms utilized in the quadrature mixing process.
  • Implementation of the digital zero-EF selectivity section depends on the ability to generate accurate, stable digital representations of these waveforms.
  • a class of digital oscillator realizations particularly suited to the requirements of the present invention is based on the concept of ROM (read only memory) lookup.
  • f c is the desired oscillator frequency
  • e j2Hf c t cos2 ⁇ f c t + jsin2 ⁇ f c t
  • the desired cosine and sine waveforms may be regarded as the real and imaginary parts, respectively, of the complex sinusiod waveform.
  • the sampled version of e j2 ⁇ f c t is obtained by replacing the continuous time variable t by the discrete time variable nT, where n is a counting integer (1,2,3, ...) and T is the
  • direct ROM lookup basically involves the use of ROM table containing the 2 N pairs of values (cosine and sine), which is addressed by a register containing the integer nk (proportion to phase.)
  • the phase register is incremented by the incremented by the value k (corresponding to the desired frequency f c ) at each sample time (corresponding to n).
  • the direct ROM look-up technique may involve large amounts of ROM.
  • the ROM size may be reduced somewhat by taking advantage of the symmetric properties of cosine and sine waveforms. Such properties allow the number of table entries to be reduced from 2 N , to 2 N /8, pairs of numbers. Even with this reduction the ROM size may still be excessive. In such cases, a technique called Factored ROM lookup may be employed to further reduce ROM size.
  • the digital local oscillator 400 of the present invention uses the factored
  • the unit magnitude phasor e j ⁇ can be represented dividing the signal into e j ⁇ c ⁇ e j ⁇ f.
  • the unit magnitude phasor can be realized by having separate coarse value phasors and fine-value phasors stored in ROM which are multiplied together to get thediscrete time sine and cosine values required for the quadrature mixers.
  • the advantage of this factorization is that the amount of ROM necessary to store the coarse-value and fine value phasors is greatly reduced from that required for the direct ROM look-up approach.
  • the expense paid for this ROM size reduction is the introduction of circuitry to perform the complex multiplication of coarse and fine phasors.
  • a complex multiplication can be implemented with four multipliers and two adders.
  • the ROM for the cosine fine-value phasor can be eliminated. Further, by approximating the small angle cosine values as one, two multipliers can be eliminated from the multiplication structure required to generate a complex product. This results in both a cost and size savings in the factored ROM implementation.
  • phase accumulator 406 can be implemented as an N-bit binary latch which is used to hold the address of the next location of ROM to be addressed.
  • the output of phase accumulator 406 may be directly coupled to cosine coarse-value ROM 418, sine coarse-value ROM 416, and sine fine-value ROM 414 (recall that fine-value cosine ROM is not required, as it is being approximated by one).
  • phase accumulator 406 is fed back into summer 404 to be added (modulo 2 N ) to the binary number representing the channel frequency information located in the channel frequency latch 402.
  • the output of phase accumulator 406 is updated once every clock pulse, which is generally the sampling frequency.
  • the result of this binary addition is that phase accumulator 406 is holding the binary sum (proportional to phase) of the last address plus a binary vector contained in the channel frequency latch. This number indicates the next address to be required to create the quadrature local oscillator signals cos 2 ⁇ f c nT and sin 2 ⁇ f c nT.
  • the ROM size may be reduced, or equivalently, the frequency resolution may be improved without increasing the ROM size, by adding a digital dither signal to the output of phase accumulator 406 and truncating the result prior to addressing the ROM tables.
  • the frequency resolution of the local oscillator is defined by the data path width (N) of the phase accumulator and the sampling rate f s required.
  • N data path width
  • f s sampling rate
  • the most straight-forward method of increasing frequency resolution is to add more bits to the phase accumulator and increase the size of the ROM tables. However this can be an expensive solution since the ROM must double in size for each bit added to the phase accumulator.
  • Another option would be to add bits to the phase accumulator but truncate the additional bits before performing the ROM look-up. This introduces severe phase rounding and causes spurs in the local oscillator output. In order to avoid these spurs a low level dither signal is added to the accumulator output before truncation.
  • the frequency resolution of the digital oscillator may be enhanced, without increasing ROM size and without introducing spurs in the output, by adding a binary dither signal to the output of phase accumulator 406 before truncating.
  • digital oscillator 400 is provided with an L-bit dither source 408, which generates an L-bit wide, uniform probability density, pseudorandom "white noise" signal.
  • Dither source 408 is clocked at the sampling frequency f s , so as to provide a new L-bit dither word for every phase word output from phase accumulator 406.
  • This composite N-bit dither signal is added to the N-bit output of phase accumulator 406 by N-bit binary adder 410, in Modulo 2 N fashion.
  • the sum output of adder 410 is then truncated to M bits (truncation not shown). In practice this truncation process is achieved by simply ignoring the least significant bits produced at the output of digital adder 410.
  • the truncation operation itself allows for reduced ROM size.
  • Quantization or truncation of the binary phase word produces distortion or noise in the generated sine and cosine waveforms. Since the phase is a periodic function (sawtooth), the noise produced by quantization would also be periodic unless it is randomized somehow. Periodic noise would result in discrete "spurs" in the oscillator output spectrum which are undesirable in most applications if their level exceeds some threshold. Addition of the dither signal prior to phase quantization randomizes the phase noise, resulting in a more desirable white noise spectrum at the output
  • the binary phase word is represented by a binary word of N bits.
  • E(n) The spectrum of E(n) can be seen as simply a frequency translation (and unimportant scaling by j) of the spectrum of the phase quantization noise . Thus if is random or "white", so is E(n). Furthermore, the power of E(n) equals the power of ), allowing the output noise level created by the phase noise to be easily estimated.
  • the power level of the dither signal involves a tradeoff between noise whitening effect and output noise power level.
  • the dither power is increased (by increasing the number of bits, L, in the dither signal), the noise becomes more whitened, but the total phase noise power increases as well.
  • the number of dither bits L equals the number of bits discarded in the truncation process. It may be noted that dither signals exhibiting other than uniform probability density may be utilized.
  • the variance (power) of the phase noise is equal to 2 times the equivalent phase variance of the dither signal.
  • the frequency resolution of the digital oscillator is 19.07 Hz.
  • the frequency resolution of the digital oscillator for a given level of output noise, can be increased indefinitely by simply adding more bits to the frequency and phase latches, and to the dither signal.
  • the ROM size, determined by M, remains constant
  • the M-bit binary word retained after truncation is coupled to the ROM address latch 412, whose output is coupled to ROM's 418, 416, and 414.
  • ROM's 418, 416, and 414 Upon receiving an address, ROM's 418, 416, and 414 output the digital binary word located at the received address on their respective output ports.
  • the digital quadrature signals are then arithmetically generated from the three binary numbers.
  • the output signals of ROM 416, and 418 are binary numbers proportional to the cosine and sine of the coarse phase.
  • the output signal of ROM 414 is a binary number proportional to the sine of the fine phase.
  • the fine phase values used are the values centered around the positive axis.
  • the coarse phase is 2 ⁇ (Pc + 1/2) /2 M c, where P is the integer corresponding to the M c bit coarse address.
  • the fine phase is 2 ⁇ (p f 2 M f-1)/2 M , where P f is the integer corresponding to the Mf bit fine address.
  • P f is the integer corresponding to the Mf bit fine address.
  • the outputs of sine coarse-value ROM 418 and sine fine-value ROM 414 are first multiplied in multiplier 426.
  • the output of multiplier 426 is fed to summing circuit 440 where it is subtracted (2's complement form) from the output of cosine coarse-value ROM 416.
  • This arithmetic process yields the cosine-value which is output on port 441 and coupled to quadrature mixer 304 of Figure 3.
  • the outputs of the cosine coarse-value ROM 416 and sine fine value ROM 414 are multiplied in multiplier 428.
  • multiplier 428 is fed to a summing circuit 442 where it is summed with the output of sine coarse-value ROM 418.
  • Summing circuit 442 outputs via connection 443 the discrete time sine value digital word which is coupled to quadrature mixer 306 of Figure 3. Therefore, since the discrete time values of the sine and cosine signals are calculated mathematically, perfect 90° phase control is achieved using minimal ROM space.
  • Latches 420, 422, 424, 434 and 438 provide pipelining which facilitates high operating speed of the digital oscillator.
  • Delays 430 and 436 are provided to equalize the delays of the various signal paths.
  • the factored ROM LO reduces the ROM area while maintaining acceptable frequency resolution.
  • the coarse-value ROM's 416, 418 could each be implemented in a 1024 x 16 ROM and the fine-value sine ROM 414 could be implemented in a
  • a digital adder suitable for use with the apparatus of the present invention may be of a type constructed with several 74LS181 4-bit arithmetic logic unit devices, connected in parallel. These devices are shown and described in a data manual entitled “Motorola Schottky TTL Data Book", available from Motorola, Inc., Box 2092 Phoenix, Arizona, 85036.
  • ROMs 418, 416 and 414 may be formed by a variety of well known ROM devices such as a 82LS181 available from Signetics Corporation, 811 E. Argues Avenue, P.O. Box 3409, Sunnyvale, Calif. 94088, and described in the "Signetics Bipolar Memory Data Manual", 1984. Both multiplier 426 and 428 may be realized as, for example, an MPY016K manufactured by TRW, Inc., TRW Electronic Components Group, P.O. Box 2472, LaJolla, Ca. 92038.
  • the amount of coarse- value ROM required can be further reduced by taking advantage of symmetries in the cosine and sine wave forms, and thereby storing only the values of the unit magnitude phasor residing in the first octant (i.e., the first 45°) of the phasor unit circle.
  • the unit magnitude phasor represents sine or cosine values rotating through 360°. Due to the symmetrical nature of sinusoidal waveforms, the values of the cosine and sine waveforms over the first octant of the unit circle are identical to the values of these waveforms over any other octant except for possible sign changes and reversal of roles (i.e., sine becomes cosine and vice versa).
  • the only coarse-value phasors that are required are those in the first octant provided there is an indicator of which octant the phasor is currently residing, and there is circuitry present to negate (i.e., change sign) and/or exchange the outputs of coarse-cosine ROM 416 and coarse-sine ROM 418 according to the current octant.
  • An octant indicator is readily implemented using three binary bits of the ROM address. For example, the three most-significant-bits (MSB's) could be used to indicate the octant, and the remaining bits used to address the ROM for the coarse-valued phasor.
  • Figure 4b is a schematic diagram of an example of a type of digital dither generator compatible with the digital oscillator of the present invention.
  • a digital dither signal can be generated by any of several well-known pseudorandom sequence generation techniques.
  • One type of dither, or random number generator is shown and described in a paper by G. I. Donov, A High-Speed Random-Number Generator , RADIO ELECTRONICS AND COMMUNICATION SYSTEMS, Vol. 25,
  • FIG. 4b a feedback shift register pseudorandom sequence generator which may be advantageously employed in the practice of the present invention is shown in schematic form.
  • the sequence generator of Figure 4b is used to provide an L-bit digital dither signal to the binary adder 410 of Figure
  • the dither generator 408 includes an R-bit shift register 460 which may be formed of a plurality of flip-flops 464 through 499 which are connected in a cascade fashion. In the preferred practice of the present invention, a parallel 3-bit dither signal is tapped from the shift register at the outputs of flip-flops 478, 491 and 499 respectively.
  • the inputs to an Exclusive-Or gate 462 are coupled to the outputs of flip-flops 464; 493, 498 and 499.
  • the output of Exclusive-Or gate 462 is coupled to the input of flip-flop 464.
  • the shift register produces a 3-bit pseudo-random dither signal which is added to the output of the phase accumulator 406 of Figure 4a.
  • the flip-flops 464-499 and the Exclusive-Or gate 462 as well as the other devices used in the practice of the present invention may be any of several well known logic devices; however, high speed TTL devices are particularly well adapted for the practice of the present invention. Implementations employing other logic families will also be obvious to one of ordinary skill in the art.
  • the dither generator of Figure 4b is set forth as an example of one type of digital dither generator which performs satisfactorily with the digital oscillator of the present invention.
  • the intermediate-frequency (EF) filter section accepts data from the A/D converter at the rate of 20M samples/sec, mixes the received signal to dc (the zero EF frequency), lowpass filters the received signal to extract the desired signal, and sends the signal to the backend 120 of Figure 1 at a (drastically) reduced sampling rate.
  • the lowpass filtering and sample-rate reduction are not separate operations; instead, the sampling rate is gradually reduced between filter sections, as undesired signals (which could cause aliasing if not removed) are filtered out
  • FIG. 5a is a block diagram of the "fast", narrowband lowpass filters 308 and 310 of Figure 3.
  • the quadrature local oscillator 302 and mixers 304 and 306 are non-feedback circuits (primarily ROMs and multipliers) which are amenable to pipelining or other forms of parallelism to increase their speed.
  • the lowpass filter sections 308, 310 are implemented as recursive (infinite impulse response) filters, they cannot be pipelined to increase their speed. Their speed is determined by the maximum delay around a closed (feedback) path. For the lowpass filter implementation of the present invention, this path includes two digital adders and one latch. It is this path which limits the A/D sampling rate and, therefore, potentially limits the overall performance of a digital receiver. Because of problems in attaining this very high speed die filter was designed by interleaving two 10 MHz TTL filters. The aliasing problems that would ordinarily be associated with using a lower sampling rate are alleviated by adding zeroes near the unwanted filter poles.
  • the "Fast" lowpass section 546 of Figure 5a is decomposed into two half-speed sections plus a combining filter, as is shown in Figure 5b.
  • This modification permits the digital EF section to operate at twice the speed that would otherwise be possible, and potentially allows improved performance of die digital receiver of the present invention.
  • the "decomposed" filter of the present invention is shown in conjunction witii Figures 3 and 5.
  • Other filter decomposition techniques have been discussed, for example, in a paper, M. Bellanger, G. Bonnerott and M. Coudreuse, Digital Filtering by Polyphase Network: Application to Sample-Rate Alteration and Filter Banks. IEEE TRANSACTIONS ON ACOUSTICS, SPEECH, AND
  • the combining filter 554 is a nonrecursive filter.
  • Such a filter can be implemented with only adders and latches (i.e., without multipliers), and so adds minimal hardware.
  • Figure 6 illustrates the decomposition process in detail with several magnitude plots.
  • Figure 6a shows the response of the original version of the first two-pole section, for an input sampling rate f s of 20 MHz.
  • Figure 6b shows the "decomposed" characteristic which results from two 10-MHz sections, while Figure 6c shows the response of the subsequent "combining" filter.
  • Figure 6d shows the composite (i.e., cascade) of Figure 6b and Figure 6c, which is virtually indistinguishable from Figure 6a, except for the "notch" at 10 MHz (which results from the two zeros at f s /2, which cancel the two nearby poles).
  • the decomposed filter can be represented as follows:
  • x and y are complex filter inputs and outputs, respectively (i.e., they have both a real part and an imaginary part).
  • h d are the decomposed filter polynomial coefficients
  • decimating filter can be reexpressed as:
  • decimating-filter inputs x and outputs y can be decomposed into two streams, as shown in Figure 5a:
  • the pole-pairs are z p 2- and (zp 2 )*. Since
  • FIG. 5b A second-order HR filter is described in a paper, Agarwal, A.C., Burrus C.S., New Recursive Digital Filter Structures Having Very Low Sensitivity and Roundoff Noise, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-27, No. 12, Dec. 1975.
  • the filter structure II proposed by Agarwal and Burrus has been modified for minimum delay around all feedback loops for the purposes of the present invention.
  • the filter structure of the present invention is illustrated in Figure 7.
  • All digital filter structures are made up of basically the same three components: adders, multipliers, and delay circuits (generally latches or RAM).
  • adders, multipliers, and delay circuits generally latches or RAM.
  • the factors affecting the performance of a digital filter all have to do with the fact that the various parameters of the filters are quantized, that is, they have finite precision rather than the infinite precision available in analog -filters.
  • the finite precision of a digital filter basically gives rise to three major performance effects that must be controlled in any implementation of a digital filter.
  • Coefficient roundoff is one of these effects.
  • the constant valued coefficients found in a digital filter determine its frequency response.
  • the result of rounding these coefficients so that they may be represented digitally in a finite number of bits causes a permanent, predictable change in the filter response.
  • This is analogous to changing the RLC values in an analog filter, however, digital filters do not suffer the detriment of temperature variations as in analog filters.
  • the higher Q of the filter i.e. narrow bandwidth compared to the sampling rate
  • the more the frequency response is distorted by coefficient rounding, unless special structures are employed.
  • Judicious selection of the filter structure is of key importance in light of the fact that EF filters are generally extremely narrow band, or high-Q filters.
  • Round-off noise is another of the performance characteristics that must be controlled in a digital filter.
  • Data entering a digital filter has been rounded to a finite number of bits, and it is almost always necessary to perform additional roundings at certain points within the filter.
  • Such rounding operations create an error or noise signal in the digital filter. For example, if the digital word length used in a filter is 16 bits and the coefficients are represented in 10 bits each multiplication operation would create a 25 bit product, which must be rounded to 16 bits before the result may be put back into memory.
  • the last major effect that is controlled in a digital filter is the overflow level.
  • the fact that data samples are represented in a finite number of bits means that there is a maximum allowable absolute value associated with every node in the filter which, if exceeded, results in an overflow phenomenon (generally wrap-around if 2's complement binary arithmetic is used). This largest allowed data value, coupled with the level of roundoff noise described previously, determines the dynamic range of the filter.
  • a digital lowpass filter section 700 is depicted in block diagram form.
  • the filter employed in the DZISS is a recursive filter (i.e., the output signal is fed back, scaled, and summed at strategic points in the filter structure) having a narrow bandwidth and optimized for high-speed and low-sensitivity to the previously described detrimental effects of parameter quantization on digital filters.
  • the second-order narrowband lowpass infinite-impulse response (IER) filter of Figure 7 is used in the decomposed "fast" lowpass filter of Figure 5b, which operates at the speed of die A/D convener. Decomposition is useful in attaining this high operational speed, but requires additional hardware: two second-order IIR sections instead of one, and a second-order FIR section which would not otherwise be needed.
  • the digital low pass filter 700 provides the function depicted by the function blocks 550 and 552 of Figure 5b.
  • the digital lowpass filter 700 consists of four digital adders (2's complement) 704, 708, 712, and 716, two digital delays or latches 710 and 718, and two binary shifters 706 and 714.
  • the individual connections of lowpass filters 308, 310, and 312, and 313, as described in Figure 3 are multi-bit digital words and not single electrical lines.
  • the input signal to the digital filter 700 is applied to a non-inverting input 702 of the digital adder 704.
  • a second inverting input to the digital adder 704 is taken from digital delay 718 which is fed back from the output 720 of the filter circuit.
  • the difference (2's complement) result of digital adder 704 is next applied to the input of gain element 706 which presents the shifted first sum signal as one input of digital adder 708.
  • Bit shifter 706 shifts all bits of the data word outputted from digital adder 704 to the right (i.e., toward the least significant bit) by N c bits, effecting multiplication by a coefficient c equal to 2 -Nc .
  • This bit shift may be implemented by an appropriate routing of the data lines from digital ladder 704 to adder 708.
  • Digital adder 708 adds to the shifted first sum signal the last output of digital adder 708 as held in delay 710. Further, the last or previous output of digital adder 708 is applied to digital adder 712. A second inverted input to digital adder 712 is taken from digital delay 718 which, as previously mentioned, is taken from the output 720 of the digital filter. The result of digital adder 712 is applied to bit shifter 714 which is coupled to digital adder 716. Bit shifter 714 shifts all bits of the data word outputted from digital adder 712 to the right by N a bits, effecting multiplication by a coefficient a equal to 2 -N a. Bit shifter 714 also facilitates high operating speed since no time delay is incurred.
  • Digital adder 716 adds the second shifted sum signal to the previous output of 716 as held in delay 718.
  • the output of delay 718 is also the output of the digital lowpass filter section 700 and represents a band-limited representation of the input signal 702 that was previously applied to the input of summing circuit 704.
  • Figure 8 is a block diagram of the second-order combining finite-impulse-response (FIR) filter with a notch at half the sampling rate used in the decomposed fast lowpass filters of Figure 5b.
  • FIR finite-impulse-response
  • the input 802 to filter 800 is coupled to the output 720 of filter 700, as pictured in Figure 5b.
  • the digital filter 800 comprises digital shifters 804, 806, and 808 coupled to digital delays 810 and 814 and digital summers 812 and 816, respectively.
  • the digital shifters 804, 806, and 808 use gains of 1/4, 1/2, and 1/4, respectively, to implement a filter with two zeros on the unit circle, at half the sampling frequency.
  • These digital shifters perform right shifting of the input 802 by 2, 1, and 2 bits, respectively. Since such "bit shifting" may be implemented by routing the wiring connections in the appropriate manner, these gain operations consume no actual time and require no actual hardware.
  • a first partial sum is formed in adder 812 using the scaled output of gain element 806 as the first input and the previous, or last, scaled output of gain element 804 as the second input obtained from delay element 810.
  • the output 818 is obtained as the second partial sum formed in adder 816 using the scaled output of gain element 808 as the first input and the previous, or last, first partial sum of adder 812 as the second input, obtained from delay element 814.
  • the transfer function of this filter may be written:
  • this FIR filter needs only to perform one addition and one latch operation, compared witii two additions and one latch operation in the IIR sections, so that the FIR combining filter easily operates at the full input sampling rate (20-MHz).
  • An alternative design would allow the adder to run at a lower sampling rate by the use of additional control circuitry. This would permit the FIR filter to operate more slowly by incorporating decimation into the filter operation, i.e., computing only the outputs needed by subsequent filter sections operating at a reduced sampling rate.
  • power consumption is typically reduced when operational speed is reduced. Therefore, the power consumption of the FIR combining filter could be reduced at the expense of some control circuitry.
  • sampling rate reduction or decimation.
  • the degree of sampling rate reduction possible depends on the amount of attenuation provided by the "fast" lowpass filters. For example, if a 20 MHz input sampling rate is used, and the "fast" filters are implemented as decomposed filters with coefficients as listed below in table 3, then an output sampling rate of 2 MHz can be used with over 100 Db of aliasing protection provided by die "fast” filters.
  • the “slow" lowpass filters 312 and 313 can be implemented by several stages of two pole filter sections. For example, if three stages, each having the structure of Figure 9a, 9b, and 9c and the coefficients listed in Table 3 are used, wherein slow 1 slow 2 and slow 3 correspond to Figures Figure 9a, 9b, and 9c, respectively, then the sampling rate can be reduced from 2 MHz to 80 KHz.
  • An alternative hardware-saving design involves interleaving the in-phase and quadrature sample sample streams and using three stages of time-divisionmultiplexed filtering. This requires that the filters run at twice the rate they would operate with a non-multiplexed design but since the sampling rate is reduced by a factor of 10 from the fast filter, this multiplexed filter still can operate at one-fifth the rate of the first filtering stage.
  • Figure 9a is a block diagram of the first time-division-multiplexed second-order lowpass IIR filtering stage used in the time-division-multiplexed implementation of the "slow" lowpass filters.
  • Figure 9a through 9c represent a time-division multiplexed version of a filter structure similar to that depicted in Figure 7.
  • the main difference between the structure in Figure 7 and the multiplexed version in Figure 9 is that the delay elements have been doubled in length.
  • z - 1 elements implemented in hardware as single latches
  • z -2 elements are used which are implemented as two latches configured in series.
  • the effect of this structure is that the filter alternates each sample between processing in-phase and quadrature samples.
  • Figure 9 After processing by digital filter 900a, the signal is coupled to the second filtering stage 900b and subsequently to the third filtering stage, depicted by Figure 900c.
  • the overall filter structure of digital filters 900a, 900b, and 900c is identical, so only digital filter 900a is discussed in detail.
  • the data paths and filter responses of digital filters 900a, 900b and 900c vary slightly between the various stages, as shown by Figures 9a, 9b and 9c, respectively, as well as Table 3.
  • the digital lowpass filter 900a consists of four digital adders (2's complement) 904a, 908a, 912a, and 916a, four digital latches two each in 910a, and 918a, and two binary shifters 906a and 914a.
  • the input signal to the digital filter 900a is applied to a non-inverting input 902a of the digital adder 904a.
  • a second inverting input to the digital adder 904a is taken from digital latch pair 918a which is fed.back from the output 920a of the filter circuit.
  • the difference (2's complement) result of digital adder 904a is next applied to the input of bit shifter 906a which presents the shifted first sum signal as one input of digital adder 908a.
  • Bit shifter 906a shifts all bits of the data word outputted from digital adder 904a to die right (i.e., toward the least significant bit) by N c bits, effecting multiplication by a coefficient equal to 2 -N c.
  • This bit shift may be implemented by an appropriate routing of the data lines from digital adder 904a to adder 908a.
  • high operating speed of digital filter section 900a is facilitated, since there is no time delay associated with bit shifter 906a, as there would be in a coefficient multiplication implemented by a conventional multiplier circuit.
  • Digital adder 908a adds to the shifted first sum signal the output of digital adder 908a from two sample times past as held in latch pair 910a. Further, the output of digital adder 908a as held in latch 910a is applied to digital adder 912a. A second inverting input to digital adder 912a is taken from latch pair 918a which, as previously mentioned, is taken from the output 920a of the digital filter. The result of digital adder 912a is applied to bit shifter 914a which is coupled to digital adder 912a. Bit shifter 914a shifts all bits of the data word outputted from digital adder
  • Bit shifter 914a also facilitates high operating speed since no time delay is incurred.
  • Digital adder 916a adds the second shifted sum signal to the previous output of 916a as held in delay 918a.
  • the output of delay 918a is also the output of the digital lowpass filter section 900a and represents a band-limited representation of the input signal 902a that was previously applied to the input of summing circuit 904a.
  • the recovered digital signal comprises a received digital signal having quadrature components.
  • the quadrature characteristics of the received digital signal insures that phase information present in the original RF signal is preserved through the processing chain.
  • the received quadrature digital signals are coupled to the digital receiver backend 120 of Figure 1, which is advantageously implemented by a programmable, general purpose digital signal processing I.C., as mentioned above.
  • the radio backend 120 performs the additional processing required to generate the digital baseband signal used to provide a recovered data or audio signal.
  • the radio backend 120 can provide final predemodulation filtering and post-demodulation processing of the recovered signal.
  • Figures 10 and 11 detail digital filter structures suitable for performing final predemodualtion selectivity in the context of a digital signal processing I.C.
  • Figure 12 below details one technique which is suitable for demodulating an FM signal in accordance witii the teachings of the present invention.
  • Figure 10 shows a fifth-order nonrecursive filter 1000 which provides additional attenuation so that the sampling rate may be further reduced from 80 to 40 kHz while causing negligible aliasing distortion of the desired band. Because this filter is operating at the relatively low output sampling rate of 40 kHz (complex samples), it is possible to implement it in a general-purpose digital signal processor. Such processors are typically well suited to pipelined multiply operations 1004, 1010, 1016, 1026, 1030, 1036, and accumulate operations 1006, 1012, 1020, 1024, and 1032, so that the "direct-form" filter structure was chosen.
  • Figure 11 shows a direct-form filter structure 1100 with four poles and four zeros, which is employed to smooth out the passband response of the composite receiver filter, it may be implemented with a series of multiply operations 1104, 1112, 1118, 1120, 1126, 1132, 1140, 1146, and 1150, an-accumulate operations 1106, 1114, 1116, 1122, 1108, 1130, 1136, and 1144 in a general-purpose digital signal processor. Because single-precision (typically 16-bit wordlength) operations do not afford sufficient dynamic range for mobile-radio applications, it is necessary to use double-precision calculations in the DSP implementation.
  • multiply operations 1104, 1112, 1118, 1120, 1126, 1132, 1140, 1146, and 1150 an-accumulate operations 1106, 1114, 1116, 1122, 1108, 1130, 1136, and 1144 in a general-purpose digital signal processor. Because single-precision (typically 16-bit wordlength) operations do not afford sufficient dynamic range for mobile-radio applications, it is necessary
  • Figure 12 is a diagram of a digital FM demodulator compatible with the digital radio architecture of the present invention.
  • digital demodualtion is one task, among others, performed by a digital signal processor I. C.
  • limiter section 1202 comprises the scaling stage 1204 together with the in-phase channel inverse calculation generator 1210 and the product multiplier 1212 where the reciprocal of the scaled and rotated in-phase (I) component is multiplied with the scaled and rotated out-of-phase (Q') component producing a term equal to the value of the tangent of the phase angle of the scaled and rotated signal vector sample.
  • the action of digital multiplier 1212 performs an ideal limiting of any amplitude variations of the input signal vector that may be present
  • the term passed from the digital multiplier 1212 represents die tangent of the rotated and scaled signal vector sample. This term is processed by the arctangent generator stage 1214 whose output equals the phase angle of the rotated and scaled signal vector.
  • This quantity when added by digital summer 1214 to the coarse phase value output from the coarse phase accumulator 1206 represents the total phase angle of the input signal vector sample.
  • the difference signal generated at the output of digital summer 1218 between the phase angle of the current signal vector sample and the negative of the delayed output generated by digital delay 1220 represents 1 sample of the output demodulated message.
  • Figures 13a through 13c are diagrams detailing the principles of phasors in the context of the present invention.
  • the sealer's 1204 function is to scale the amplitude of the input signal vector of varying magnitude to the shaded region shown.
  • the coarse phase accumulator 1206 determines the coarse phase angle of the signal vector, ⁇ c , and the output of the arctangent generator stage 1212 equals the fine phase of the signal vector, ⁇ f , as depicted in fig. 13b.
  • the signal vector 0f is constrained by the vector rotation to lie in the range of - ⁇ /4 ⁇ ⁇ f ⁇ + ⁇ /4 (shaded region of Figure 13b.)
  • the sum of these 2 quantities generated at the output of digital summer 1214 represents the total phase angle of the input signal vector sample, ⁇ (n).
  • the stream of samples representing the demodulated output message may be low passed filtered to remove noise outside the message bandwidth, as is typically performed subsequent to FM detection.
  • digital demodulator described in the figures above could be implemented with discrete hardware digital multipliers, adders, registers, etc.
  • the digital demodulator of the present invention is particularly suitable for implementation with a class of devices known as digital signal processors.
  • the present invention would perform satisfactorily with a variety of well known digital signal processors such a NEC D7720, available from NEC Electronics U.S.A. Inc., One Natick Executive Park, Natick, Mass. 01760, or a TMS 32010 available from Texas Instruments Inc, P.O. Box 225012, Dallas, Texas 752265.
  • Digital signal processors generally include hardware high speed digital multipliers as well as the ability to process a digital data stream in accordance with a predetermined algorithm.
  • Figures 14a and 14b are flow diagrams detailing the background processing of the present invention as implemented with a digital signal processor.
  • the in-phase and out-of-phase signal vector components will hereinafter be referred to as the components I and Q respectively.
  • the algorithm of the present invention begins at 1402, which causes the digital signal processor to execute decision 1404 to determine the sign of the I component. Based on the outcome of decision 1404, the sign of the Q component is determined by decisions 1406 and 1448. Next, the difference of the I and Q components is determined by items 1410, 1408, 1472, and 1450 which generate values comprising the values of Q -I, I -Q, Q - 1, and Q + I, respectively.
  • the sign of the respective results is determined by decisions 1430, 1412, 1474, and 1452, respectively. Based on the results of these decisions, the component (I or Q) which has the greater absolute value is known, and the octant (i.e. multiple of ⁇ /4) in which the signal vector lies is also known. This value, if less than zero, is complemented by items 1420, 1486, 1476, and 1462, respectively.
  • the value that represents the greatest absolute value of either the I or Q channel is pushed onto a program stack by items 1442, 1432, 1422, 1414, 1488, 1478, 1466, or 1454, respectively, and is hereafter referred to as the quantity SMAX.
  • the quantity SMAX is used by the call to the scale subroutine by items 1444, 1434, 1424, 1416, 1490, 1480, 1466, or 1456, respectively, to determine me correct amount of scaling to be applied to the input signal vector sample.
  • the scale subroutine returns correcdy scaled signal vector components I and Q.
  • a coarse phase value, based on the octant location of the signal vector is stored to a temporary storage location by items 1446, 1436, 1426, 1418, 1492, 1482, 1468, or 1460, respectively.
  • This value will always be a multiple of ⁇ /2 radians over die range of - ⁇ ⁇ ⁇ (c) ⁇ ⁇ .
  • the signal vector is th en geometrically rotated by the negative of the coarse phase value that was saved by items 1440, 1428, 1492, 1484, 1470, or 1460, respectively.
  • the scaled and rotated signal components that result are hereafter referred to as the I' and Q' signal vector components.
  • the effect of this vector rotation is to rotate the signal vector such that the rotated signal vector components I' and Q' yield a composite vector with a phase angle in the range of - ⁇ /4 ⁇ ⁇ f ⁇ ⁇ /4.
  • FIGs 15a and 15b are flow diagrams of the operation of the scale subroutine described in conjunction with Figure 14a above.
  • the scaling subroutine 1500 examines the value of SMAX to determine the correct amountofscaling to be applied to the signal vector components I and Q.
  • the operation of this subroutine is dependent on the resolution or number of bits used to represent the signal vector components.
  • the operation of the scale subroutine will be explained in the context of using 32 bit long words to represent the signal vector components.
  • the most significant word (MSW) of the quantity SMAX is compared to zero by decision 1504. If the MSW of SMAX is greater than zero, the least significant word (LSW) of SMAX will be discarded, and the MSW will be compared to a scaling threshold value by item 1506. If the MSW of SMAX is found to equal zero, then the MSW will be discarded, and the
  • LSW will be compared to a scaling threshold value by item 1528.
  • the results of the comparisions generated by items 1506, and 1528, respectively, are tested against zero by decisions 1508, and 1530, respectively, and if the result is found to be greater than zero, no scaling of the signal vector components is necessary, and the subroutine exits through item 1550 to die point where the routine activated subroutine 1500.
  • the retained word (i.e. MSW or LSW) of SMAX is less than the threshold value, die retained word is tested to see if it absolute magnitude is greater than 255 by decisions 1510, and 1532, respectively. This is equivalent to determining if die upper 8 bits of the retained word of SMAX are greater than or equal to zero. If the result of this test is true (i.e.
  • die retained word is divided by 256 by items 1514 or 1536. respectively. This has the effect of shifting the upper 8 bits of the retained word of SMAX into the lower 8 bits of this word. If the result of decision 1510, or 1532 indicates that die retained word is less than 255, then no division is performed.
  • This quantity is now used as an address offset by items 1516, 1512, 1538, or 1534 to select values stored in ROM data table, and a scaling factor is retrieved from a ROM by items 1520, 1540. This factor is adjusted to the correct value necessary to scale this signal vector components, depending on previous decisions 1510 or 1532.
  • the signal vector components are scaled to the correct region for use by the approximations applied within the demodulator by items 1522 and 1524 or 1542 and 1546 and the routine exists back to the calling procedure tiirough items 1526 or 1548.
  • f(x) (1/x) ⁇ ⁇ [[[[[[[[[C7(x-1)-C6 ](x- 1)- C5 ](x-1)+C4 ](x-1)+C3 ](x-1)-C2 ](x-1)-C1 ⁇
  • the Q component is pushed On a program stack storage area by item 1604 and the quantity (l- 1 ) is calculated by item 1606, hereinafter referred to as the quantity ARG.
  • Coefficient C7 is fetched from data ROM by item 1608 and is multiplied with ARG by item 1610 forming a quantity TMP.
  • Coefficient C6 is fetched from as data ROM by item 1612 and added to TMP by item 1614 yielding the new value for TMP.
  • the value of the arctangent of the quantity (Q'/l) is computed by items 1656 through 1692.
  • the result of this process is a signed value representing the phase angle of the rotated signal vector, or the fine phase angle of the input signal vector sample.
  • the value of the coarse phase of the input signal vector sample is retrieved from a temporary storage location by item 1694 and is summed with the result of the arctangent calculation by item 1696.
  • phase angle of the input signal vector sampie This result represents the phase angle of the input signal vector sampie.
  • the phase angle of the previous input signal vector sample. ⁇ n- 1 is fetched from a program stack by item 1700.
  • the current phase sample is pushed onto a program stack by item 1702.
  • the difference of the previous phase sample and the current phase sample is calculated by item 1704 thus yielding an output sample of the demodulated message m(n)
  • the message sample m(n) comprises the demodulated voice signal in a sampled . form.
  • the demodulated voice signal may be converted back to analog form, then amplified and played through a loudspeaker as mentioned above.
  • a digital voice message may be stored in digital a digital memory 123 for later use
  • demodulated data symbols may be routed to a computer for further processing or to a computer terminal for immediate display.
  • the digital receiver of the present invention contemplates an all digital radio receiver which operates on a received signal which is converted to a digital form after preselection at die output of the antenna.
  • the receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and general-purpose digital signal processor
  • DSP digital filter

Abstract

Le récepteur de fréquence radio numérique (100) de la présente invention consiste en un récepteur radio numérique qui fonctionne sur un signal analogique reçu ayant été converti en une forme numérique après présélection à la sortie de l'antenne. Le récepteur numérique (100) de la présente invention comprend un présélecteur (106), un convertisseur haute vitesse (108) analogique/numérique (A/D), une section de sélectivité (110) de fréquence intermédiaire numérique (IF) ayant un signal de sortie sensiblement à des fréquences de bandes de base, et un circuit (120) d'un processeur de signaux numériques (DSP) effectuant une démodulation et un filtrage audio. L'architecture radio de la présente invention est adaptable de manière programmable à pratiquement tous les schémas de modulation connus et est particulièrement appropriée aux circuits intégrés.
PCT/US1986/001764 1985-09-03 1986-08-25 Recepteur de frequence radio numerique WO1987001531A1 (fr)

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KR870700384A KR880700532A (ko) 1985-09-03 1986-08-25 신호 처리 장치 및 방법
DK184287A DK184287D0 (da) 1985-09-03 1987-04-10 Digital radiofrekvensmodtager
FI871897A FI85076C (fi) 1985-09-03 1987-04-29 Digital radiofrekvensmottagare.

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US77173685A 1985-09-03 1985-09-03
US771,736 1985-09-03

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AU (4) AU591181B2 (fr)
CA (1) CA1304786C (fr)
DK (1) DK184287D0 (fr)
FI (1) FI85076C (fr)
MY (1) MY103057A (fr)
WO (1) WO1987001531A1 (fr)

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US4808939A (en) * 1988-04-04 1989-02-28 Unisys Corporation Variable rate rectangular matched filter
EP0398981A1 (fr) * 1988-01-28 1990-11-28 Motorola Inc Agencement pour un convertisseur sigma/delta destine a des signaux de bande passante.
NL9001816A (nl) * 1989-08-14 1991-03-01 Int Mobile Machines Abonnee-eenheid voor draadloos digitaal abonnee-communicatiesysteem.
EP0429948A2 (fr) * 1989-11-15 1991-06-05 Hitachi, Ltd. Démodulateur pour un signal modulé en phase et récepteur de radio avec un tel démodulateur
EP0470505A2 (fr) * 1990-08-08 1992-02-12 National Semiconductor Corporation Détection synchrone de signaux modulés par sauts de fréquence
EP0616434A1 (fr) * 1993-03-15 1994-09-21 Alcatel Mobile Communication France Récepteur numérique à fréquence intermédiaire et procédé de filtrage en bande de base mis en oeuvre dans ce récepteur
GB2282925A (en) * 1993-09-30 1995-04-19 Plessey Semiconductors Ltd Direct conversion receivers
US5644602A (en) * 1989-08-14 1997-07-01 Interdigital Technology Corporation Direct digital frequency synthesizer for use in a subscriber unit of a wireless digital communication system
NL9700007A (nl) * 1989-08-14 1997-12-01 Interdigital Tech Corp Abonnee-eenheid voor een draadloos digitaal communicatiesysteem.
WO2000041322A1 (fr) * 1998-12-30 2000-07-13 Infineon Technologies Ag Circuit pour un terminal de communication a plusieurs normes
EP1123609A1 (fr) * 1998-10-19 2001-08-16 Motorola Inc. Sous-systeme de recepteur multimode sigma-delta dans la bande passante a limitation d'interference, et son procede d'utilisation
GB2362279A (en) * 2000-05-12 2001-11-14 Global Silicon Ltd Radio receiver
EP1611688A2 (fr) * 2003-02-28 2006-01-04 Silicon Laboratories, Inc. Circuit d'accord pour recepteurs haute frequence et procede correspondant
US7358885B2 (en) 2003-02-28 2008-04-15 Silicon Laboratories, Inc. Mixing DAC architectures for a radio frequency receiver
US7425995B2 (en) 2003-02-28 2008-09-16 Silicon Laboratories, Inc. Tuner using a direct digital frequency synthesizer, television receiver using such a tuner, and method therefor
US7447493B2 (en) 2003-02-28 2008-11-04 Silicon Laboratories, Inc. Tuner suitable for integration and method for tuning a radio frequency signal
US7599676B2 (en) 2007-01-31 2009-10-06 Silicon Laboratories, Inc. Power consumption reduction techniques for an RF receiver implementing a mixing DAC architecture
US7676210B2 (en) 2003-09-29 2010-03-09 Tod Paulus Method for performing dual mode image rejection calibration in a receiver
US7773968B2 (en) 2006-11-30 2010-08-10 Silicon Laboratories, Inc. Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures
EP2242176A3 (fr) * 2001-11-27 2014-03-19 Qualcomm Incorporated Conversion directe de signaux RF à bande étroite

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US6633550B1 (en) 1997-02-20 2003-10-14 Telefonaktiebolaget Lm Ericsson (Publ) Radio transceiver on a chip
RU2726281C1 (ru) * 2019-08-26 2020-07-10 Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации Активная фазированная антенная решетка

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Cited By (48)

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EP0398981A4 (en) * 1988-01-28 1991-05-15 Motorola, Inc. Method and arrangement for a sigma delta converter for bandpass signals
EP0398981A1 (fr) * 1988-01-28 1990-11-28 Motorola Inc Agencement pour un convertisseur sigma/delta destine a des signaux de bande passante.
US4808939A (en) * 1988-04-04 1989-02-28 Unisys Corporation Variable rate rectangular matched filter
US6587516B2 (en) 1989-08-14 2003-07-01 Interdigital Technology Corporation Subscriber unit producing a modulated digital frequency
FR2652464A1 (fr) * 1989-08-14 1991-03-29 Int Mobile Machines Unite d'abonne pour systeme de communication numerique sans fil.
US6449317B1 (en) 1989-08-14 2002-09-10 Interdigital Technology Corporation Digital synthesizer
US5644602A (en) * 1989-08-14 1997-07-01 Interdigital Technology Corporation Direct digital frequency synthesizer for use in a subscriber unit of a wireless digital communication system
US6078629A (en) * 1989-08-14 2000-06-20 Interdigital Technology Corporation Digital synthesizer
US6724851B2 (en) 1989-08-14 2004-04-20 David Norton Critchlow FIR chip for use in a wireless subscriber unit
BE1005310A5 (fr) * 1989-08-14 1993-06-22 Internat Mobile Machines Corp Unite d'abonne pour systeme de communication numerique sans fil.
US5694430A (en) * 1989-08-14 1997-12-02 Interdigital Technology Corporation Subscriber unit for wireless digital subscriber communication system
NL9700008A (nl) * 1989-08-14 1997-12-01 Interdigital Tech Corp Abonnee-eenheid voor een draadloos digitaal communicatiesysteem.
NL9001816A (nl) * 1989-08-14 1991-03-01 Int Mobile Machines Abonnee-eenheid voor draadloos digitaal abonnee-communicatiesysteem.
NL9700007A (nl) * 1989-08-14 1997-12-01 Interdigital Tech Corp Abonnee-eenheid voor een draadloos digitaal communicatiesysteem.
EP0429948A2 (fr) * 1989-11-15 1991-06-05 Hitachi, Ltd. Démodulateur pour un signal modulé en phase et récepteur de radio avec un tel démodulateur
EP0429948A3 (en) * 1989-11-15 1992-10-21 Hitachi, Ltd. Direct conversion frequency/phase shift keying demodulator
EP0470505A3 (en) * 1990-08-08 1992-12-02 National Semiconductor Corporation Synchronous fsk detection
EP0470505A2 (fr) * 1990-08-08 1992-02-12 National Semiconductor Corporation Détection synchrone de signaux modulés par sauts de fréquence
US5619536A (en) * 1993-03-15 1997-04-08 Alcatel Radiotelephone Digital superheterodyne receiver and baseband filter method used therein
FR2702902A1 (fr) * 1993-03-15 1994-09-23 Alcatel Radiotelephone Récepteur numérique à fréquence intermédiaire et procédé de filtrage en bande de base mis en Óoeuvre dans ce récepteur.
EP0616434A1 (fr) * 1993-03-15 1994-09-21 Alcatel Mobile Communication France Récepteur numérique à fréquence intermédiaire et procédé de filtrage en bande de base mis en oeuvre dans ce récepteur
GB2282925A (en) * 1993-09-30 1995-04-19 Plessey Semiconductors Ltd Direct conversion receivers
GB2282925B (en) * 1993-09-30 1998-04-15 Plessey Semiconductors Ltd Direct conversion receivers
EP1445871A1 (fr) * 1998-10-19 2004-08-11 Motorola, Inc. Sous systeme de récepteur multimode sigma-delta dans la bande passante à limitation d'interférence et son procédé d'utilisation
EP1123609A1 (fr) * 1998-10-19 2001-08-16 Motorola Inc. Sous-systeme de recepteur multimode sigma-delta dans la bande passante a limitation d'interference, et son procede d'utilisation
EP1123609A4 (fr) * 1998-10-19 2003-01-08 Motorola Inc Sous-systeme de recepteur multimode sigma-delta dans la bande passante a limitation d'interference, et son procede d'utilisation
US6697438B2 (en) 1998-12-30 2004-02-24 Infineon Technologies Ag Circuit configuration for a multistandard communications terminal
WO2000041322A1 (fr) * 1998-12-30 2000-07-13 Infineon Technologies Ag Circuit pour un terminal de communication a plusieurs normes
GB2362279B (en) * 2000-05-12 2004-12-29 Global Silicon Ltd Radio receiver
WO2001086919A3 (fr) * 2000-05-12 2002-10-17 Global Silicon Ltd Recepteur radio
EP2012437A2 (fr) * 2000-05-12 2009-01-07 GS IP Limited Liability Company Methode pour supprimer une fréquence hétérodyne dans une récepteur radio
WO2001086919A2 (fr) * 2000-05-12 2001-11-15 Global Silicon Limited Recepteur radio
USRE45443E1 (en) 2000-05-12 2015-03-31 GS IP, Limited Liability Company Radio receiver
GB2362279A (en) * 2000-05-12 2001-11-14 Global Silicon Ltd Radio receiver
US7672411B2 (en) 2000-05-12 2010-03-02 Morgan James Colmer Radio receiver
EP2012437A3 (fr) * 2000-05-12 2009-01-28 GS IP Limited Liability Company Methode pour supprimer une fréquence hétérodyne dans une récepteur radio
EP2007017A1 (fr) * 2000-05-12 2008-12-24 GS IP Limited Liability Company Récepteur radio
EP2242176A3 (fr) * 2001-11-27 2014-03-19 Qualcomm Incorporated Conversion directe de signaux RF à bande étroite
US7358885B2 (en) 2003-02-28 2008-04-15 Silicon Laboratories, Inc. Mixing DAC architectures for a radio frequency receiver
US7447493B2 (en) 2003-02-28 2008-11-04 Silicon Laboratories, Inc. Tuner suitable for integration and method for tuning a radio frequency signal
US7548742B2 (en) 2003-02-28 2009-06-16 Silicon Laboratories, Inc. Tuner for radio frequency receivers and associated method
US7558546B2 (en) 2003-02-28 2009-07-07 Silicon Laboratories, Inc. Selectable high-side/low-side mix for high intermediate frequency (IF) receivers
US7425995B2 (en) 2003-02-28 2008-09-16 Silicon Laboratories, Inc. Tuner using a direct digital frequency synthesizer, television receiver using such a tuner, and method therefor
EP1611688A4 (fr) * 2003-02-28 2006-05-31 Silicon Lab Inc Circuit d'accord pour recepteurs haute frequence et procede correspondant
EP1611688A2 (fr) * 2003-02-28 2006-01-04 Silicon Laboratories, Inc. Circuit d'accord pour recepteurs haute frequence et procede correspondant
US7676210B2 (en) 2003-09-29 2010-03-09 Tod Paulus Method for performing dual mode image rejection calibration in a receiver
US7773968B2 (en) 2006-11-30 2010-08-10 Silicon Laboratories, Inc. Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures
US7599676B2 (en) 2007-01-31 2009-10-06 Silicon Laboratories, Inc. Power consumption reduction techniques for an RF receiver implementing a mixing DAC architecture

Also Published As

Publication number Publication date
EP0235264A4 (fr) 1990-02-26
EP0235264A1 (fr) 1987-09-09
AU4010089A (en) 1989-12-07
AU611584B2 (en) 1991-06-13
AU591181B2 (en) 1989-11-30
KR880700532A (ko) 1988-03-15
DK184287A (da) 1987-04-10
AU611318B2 (en) 1991-06-06
AU6335586A (en) 1987-03-24
AU4010189A (en) 1989-12-07
DK184287D0 (da) 1987-04-10
FI85076B (fi) 1991-11-15
FI871897A (fi) 1987-04-29
FI85076C (fi) 1992-02-25
CA1304786C (fr) 1992-07-07
JPS63500766A (ja) 1988-03-17
MY103057A (en) 1993-04-30
AU611317B2 (en) 1991-06-06
JP2829605B2 (ja) 1998-11-25
AU4009989A (en) 1989-12-07
FI871897A0 (fi) 1987-04-29

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