WO1986001660A1 - Systeme de compression et d'expansion de donnees pour la transmission ou le stockage de donnees - Google Patents

Systeme de compression et d'expansion de donnees pour la transmission ou le stockage de donnees Download PDF

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Publication number
WO1986001660A1
WO1986001660A1 PCT/EP1985/000450 EP8500450W WO8601660A1 WO 1986001660 A1 WO1986001660 A1 WO 1986001660A1 EP 8500450 W EP8500450 W EP 8500450W WO 8601660 A1 WO8601660 A1 WO 8601660A1
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WIPO (PCT)
Prior art keywords
data
output
input
register
counter
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PCT/EP1985/000450
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German (de)
English (en)
Inventor
Peter Scheffler
Gerald Knabe
Original Assignee
Dr. Gerald Knabe Gmbh
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Application filed by Dr. Gerald Knabe Gmbh filed Critical Dr. Gerald Knabe Gmbh
Publication of WO1986001660A1 publication Critical patent/WO1986001660A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
    • H03M7/48—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind alternating with other codes during the code conversion process, e.g. run-length coding being performed only as long as sufficientlylong runs of digits of the same kind are present

Definitions

  • Data compression and data expansion device for transmitting or storing data
  • the invention relates to a data compression device for transmitting data with a register for receiving an information unit of input data, a converter device for converting the data and an output for the converted data, a controller, a comparator connected to the output of the register and one controlled by the latter Counter.
  • the invention further relates to an associated data expansion device for transmitting data input via an input, with a register for receiving an information unit of data, a converter device for converting the data and an output for the converted data, and a controller, one connected to the input Counter is provided and the controller is designed such that an information unit input via the input, which has no corresponding identification bit, is fed to the output, and when a corresponding identification bit occurs, the information unit is added to the counter, and so often to the output, while simultaneously advancing an information unit is fed to the counter by one at a time until the counter reading assumes a predetermined count.
  • the invention relates to a data transmission system with a data converter arranged on the input side, a data converter on the reception side and a transmission link therebetween, and a data transmission system with a data memory having an input and an output.
  • DE-OS 27 23 523 describes a method and a device for compressing and decompressing digital data to be stored. In the method described there, however, a complicated identification field in the data memory is necessary for compression or decompression.
  • a data compression device of the type described at the outset is known from European laid-open specification A 1-0012173, in which the resolution of an image to be transmitted is reduced in order to reduce storage or transmission costs. This also reduces the amount of information describing this changed image, so that the storage or transmission costs are reduced due to the smaller amount of data. However, it is not possible to reproduce the image with its original resolution at the receiving end or at the output of the memory.
  • the object of the invention is to provide a data compression device or an associated data expansion device and an associated data transmission system, with which it is possible not only to reduce the amount of data to be transmitted to save storage or transmission costs, but to change them so that the complete amount of data with its original information content can also be restored from the reduced amount of data at the exit.
  • a data compression device of the type described at the outset which is characterized in accordance with the invention in that the comparator checks for the equality of all the data in the information unit, and the control is designed in such a way that the contents of the register are fed to the output and at if they are not equal Equality produces a characteristic bit and the counter is incremented by one, and the counter reading together with the characteristic bit is fed to the output if two successive information units do not match.
  • the data expansion device is characterized in that the data of the information unit are all identical to one another and that the information unit is supplied by the control when a characteristic bit occurs.
  • a data transmission system with a data converter arranged on the input side, a data converter on the receiving side and a transmission path between them is characterized in that the input-side converter is a data compression device of the type described above and the data converter is a data expansion device of the type described above.
  • the data transmission system with a data memory having an input and an output is characterized in that a data compression device of the type described above is provided on the input side and a data expansion device of the type described above is provided on the output side.
  • FIG. 1 shows a block diagram of a data compression device according to the invention
  • FIG. 2 shows a block diagram of a data expansion device according to the invention
  • FIG. 3 shows an exemplary embodiment of a circuit of the data compression device according to the invention
  • FIG. 4 shows an exemplary embodiment of a circuit of the data expansion device according to the invention
  • 5 shows a schematic representation of the data compression and data expansion process using an example
  • 6 shows a schematic illustration of an initial state of the data compression device according to the invention according to FIG. 3;
  • FIG. 7 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 in the first period according to FIG. 5;
  • FIG. 8 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the second period according to FIG. 5;
  • FIG. 9 shows a schematic illustration of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the third period according to FIG. 5; 10 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the fourth period in FIG. 5;
  • FIG. 11 shows a schematic representation of the state of the data compression device according to the invention
  • FIG. 12 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the fifth period according to FIG. 5; 13 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the (5 + 126) th period according to FIG. 5;
  • FIG. 3 at the beginning of the (5 + 126 + 1) th period according to FIG. 5;
  • FIG. 15 shows a schematic representation of the state of the data compression device according to the invention according to FIG. 3 at the beginning of the (5 + 126 + 2) th period after
  • Fig. 16 is a schematic representation of the state of the data compression device according to the invention according to Fig. 3 at the beginning of the (5 + 126 + 3) th period of
  • FIG. 17 shows a block diagram of a further embodiment of a data compressor device according to the invention.
  • FIG. 1 shows a block diagram of the data compressor 1 according to the invention
  • FIG. 2 shows a block diagram of the data expander 2 according to the invention.
  • the data compressor 1 has four circuit blocks, namely a converter 3, a sequence controller 4, a control input part 5 and a memory 6.
  • the data expander 2 has a comparable structure with likewise four circuit blocks, namely a converter 7, a sequence controller 8, a control input part 9 and a memory 10.
  • the memory 10 can be designed as a memory different from the memory 6 or as the same memory as the memory 6.
  • the data compressor 1 has a first input 11 for the data to be compressed and a second input 12 for the switch-on signal.
  • the data expander 2 has an input 13 for the switch-on signal and an output 14 for the data to be output.
  • the connection of the individual circuit blocks 3, 4, 5, 6 and 7, 8, 9, 10 with one another is shown schematically in FIGS. 1 and 2 and is intended in connection with the detailed description of the structure of the individual blocks in the following in connection with the 3 and 4 are shown.
  • the converter 3 shows the circuit of a data compressor 1 according to the invention.
  • the converter 3 has a shift register 15, a counter 16 and a comparator 17.
  • the shift register 15 is formed by two registers 74 LS 598 and has eight register locations with eight parallel outputs 18, which can be made high-resistance.
  • the register has a first input 19.
  • the shift register 15 is given a pull-up and pull-down option.
  • the register 15 also has a second input 20 which forms the serial data input of the shift register 15 and forms an input to the first register location 21 which is connected to the first input 11 of the data compressor 1.
  • the shift register 15 also has a clock input 22. Instead of via the serial data input 20, the input data can of course also be supplied via a parallel data input of the register 15.
  • the counter 16 is formed by a component 74 AS 869 and has eight memory locations which can be loaded in parallel.
  • the counter 16 has eight parallel inputs 23, of which the first seven are each connected to corresponding register locations of the shift register 15 via the outputs 18 in such a way that the first register location 21 is connected to a first memory location 24 of the counter 16 which points to the first register location 21
  • the following second register location is connected to the next storage location following the first storage location 24, etc.
  • the eighth storage location is set to zero.
  • the first seven memory locations of the counter 16 are routed in parallel to the outside and form a data output 25 of the converter 3.
  • the counter 16 also has a charging input 26, counter input 27 and clock input 28, which is led outwards, and an output 29, which is also led out, for displaying the Counting minimum, in this case the counting value zero.
  • the comparator 17 is formed by a component 74 AS 866 and has nine comparator inputs 30 and an output 31 for the comparison result.
  • the first eight of the inputs 30 are each connected to a corresponding output of the eight parallel outputs 18 of the shift register 15.
  • the rest of the input of the comparator inputs 30 is connected to the output of an EXNOR element 32, one input of which is connected to the output of the second register position of the shift register 15 following the first register position 21 and the other input of which is connected to the sequencer 4 in a manner described later .
  • the exit 31 is also led to the outside.
  • the output of the first register location 21 is also connected to the output of an open collector NAND element 33, the first input 34 of which is connected to the first input 19 of the shift register 15 is connected and led to the outside and the second input 35 is connected to the sequence control 4 in a manner to be described later.
  • the memory 6 has eight parallel data inputs 36, of which the first seven are each connected to one of the seven data outputs 25 of the counter 16. The eighth data input is connected to the sequential control system in a manner to be described later.
  • the memory 6 also has a read / write input 37 and an address input 38 for the address trigger signal.
  • the memory has a plurality of addresses, in each of which an information unit, e.g. can be stored in the form of a byte, which is formed by the data at the data inputs 36.
  • the control input part 5 has a clock generator 39 and a shift register 40.
  • the input 41 of the clock generator 39 is connected to the output of an OR gate 42, one input of which is connected to the second input 12 of the data compressor 1 and the other input of which is connected to the sequencer 4 in a manner to be described later.
  • the output 43 of the clock generator 39 is connected to the clock input 22 of the shift register 15, the clock input 28 of the counter 16 and a clock input 44 of the shift register 40.
  • the clock generator 39 is formed by a component 74 S 132 and is designed such that when a signal with a high level is applied to the input, it outputs 12 clocks of a predetermined controllable frequency, preferably between 7 and 100 MHz and in particular approximately 20 MHz at its output 43 .
  • the shift register 40 is formed by two registers 74 95 and has seven consecutive register locations, each with one output.
  • the output of the seventh register location is connected via a return line 45 to a data input 46 to the first register location, so that the shift register 40 as
  • the output 47 of the first register Space, the output 48 of the second register space and the output 49 of the third register space are connected to the sequencer 4 in a manner to be described later.
  • the outputs of the fourth to seventh register locations are each connected to inputs of a NOR gate 50, the output of which is connected via a line 51 to the read / write input 37 of the memory 6.
  • the NOR gate is formed by a 7425 component.
  • the outputs 48 and 49 are each connected to inputs of an OR gate 52, the output of which is connected via a line 53 to the input 19 of the shift register 15 and the first input 34 of the NAND gate 33.
  • the shift register 40 is also connected to a set input 54, by means of which the shift register 40 can be set to 1000000 in parallel or in series.
  • the sequence control has a start-stop register 55, a zero value register 56 and a characteristic value register 57.
  • the start-stop register 55 is formed by three D flip-flops E, E 'and E' ', which by connecting the Q output of the flip-flop E to the D input of the flip-flop E' and the Q- Output of the flip-flop E 'are connected to the D input of the flip-flop E' '.
  • the characteristic value register 57 is formed by two D flip-flops K 'and K' ', the Q output of the K' flip-flop being connected to the D input of the K '' flip-flop.
  • the zero value register 56 is formed by a simple D flip-flop.
  • Registers 55, 56, 57 each have reset inputs CP, data inputs D, preset inputs pr and outputs Q. and ⁇ and are connected as follows:
  • the D input 58 of the start-stop register 55 is connected to the second input 12 of the data compressor 1 and the CP input 59 of the E flip-flops and the CP input 60 of the zero value register 56 connected to the output of the fifth register position of the shift register 40.
  • the CP inputs 61, 62 of the K'- and K '' flip-flops are both connected to the output of the first register location of the shift register 40.
  • the D input 63 of the zero value register 56 is connected to the output 29 of the counter 16 and the D input 64 of the K 'flip-flop of the characteristic value register 57 together with the pr-E input of the zero value register 56 with the output of a NAND Member 66 connected.
  • the NAND gate 66 has two inputs 67, 68, of which one input 67 is connected to the output 31 of the comparator 17.
  • the other input 68 is connected via an inverter 69 to the output of an AND gate 70 with two inputs, one input of which is connected to the Q output 71 with the interposition of an inverter 72 and the other input of which is connected to the Q output of the E 'flip -Flops is connected.
  • the output of the AND gate 70 is also connected to an input of a further AND gate 73, the other input of which is connected to the output 49 of the third register location of the shift register 40 and the output of which is connected to a first input of an OR gate 74 having three inputs is.
  • the second input of the OR gate 74 is connected to the output of an AND gate 75, one input of which is connected to the output 31 of the comparator 17 or input 67 of the NAND gate 66 and the other input of which is connected to the output 47 of the first register position of the shift register 40 is connected.
  • the third input of the OR gate 74 is connected to the output of an AND gate 76 with three inputs, one input of which is connected to the output 49 of the third register location of the shift register 40, the second input of which is connected to the Q output of the K'-flip Flops of the characteristic value register 57 and its third input with the interposition of an inverter 77 with the output of an AND
  • Link 78 is connected to two inputs, the first input of which is connected to the Q output of the K ′′ flip-flop of the characteristic value register
  • an AND gate 80 with four inputs is provided, the first input of which is connected to the Q output of the K 'flip-flop of the characteristic value register 57, the second input of which is connected to the output of the AND gate 78, and the third input of which is connected to the output of a NAND gate 81 and its fourth input is connected to the output 49 of the third register location of the shift register 40.
  • the output 82 of the AND gate 80 is connected to the count input 27 of the shift register 16.
  • the NAND gate 81 has three inputs, one with the Q output of the E 'flip-flop, the second with the output of the inverter 71 and the third with the Q output of the K' 'flip-flop of the characteristic value register 57 is connected by interposing an inverter 83.
  • the output of the NAND gate 81 is connected to one of four inputs of a NAND gate 84, the further inputs of which are connected to the output of the AND gate 78 or the Q output of the K 'flip-flop and the output of one
  • NAND gate 85 are connected to two inputs, one input of which is connected to the Q output of the E ′′ flip-flop and the other output of which is connected to the Q output of the E ′ flip-flop with the interposition of an inverter 86.
  • the output of the NAND gate 84 is connected to an input of an AND gate 87 with three inputs, the further inputs of which are connected to the output 48 of the second register position of the shift register 40 or to the output of an OR gate 88 with two inputs , one input of which is connected to the Q output of the E '' flip-flop and the other input of which is connected to the Q output of the E 'flip-flop.
  • the output 89 of the AND gate 87 is connected to the address input 38 of the memory 6.
  • a line 90 is also provided, which is the second input of the EXNOR gate 32 connects to the output of the NAND gate 88, and a line 91 which connects the second input of the open collector NAND gate 33 to the output of the NAND gate 81.
  • Another line 92 connects the second input of the OR gate 42 to the Q output of the E ′′ flip-flop.
  • the start-stop register 55 and the characteristic value register 57 also each have clear inputs 93, 94, which are each connected to the output of the OR gate 42.
  • a line 92 ' is provided which connects the Q output of the K' flip-flop of the characteristic value register 57 to the eighth input of the data inputs 36 of the memory 6.
  • the OR gates 42, 52 and 88 are preferably each by a component 74 S 32, the inverters 69, 71, 77, 83 and 86 each by a component 74 S 04 and the AND gates 70, 73 and 78 by one Component 74 S 08 realized.
  • a component is preferably found for each of the two NAND elements 66 and 85
  • 75 and 76 is preferably realized by a component 74 S 64.
  • the memory 10 which can be a memory shared by several compressors and expanders and other systems, has eight data outputs 95 connected in parallel.
  • the first seven of these eight outputs 95 are each connected to corresponding register locations 1 to 7 of shift register 15 and to corresponding storage locations 1 to 7 of counter 16.
  • the eighth output is connected to the sequencer 8 in a manner to be described later.
  • the eighth memory location of counter 16 is set to the value 1.
  • the counter 16 is used as an up counter and has an output 96 for displaying the maximum counter status.
  • the second input 20 of the shift register 15 is set to zero.
  • the shift register 15 has two further inputs, namely a shift input 97 for serial shifting and a loading input 98 for parallel loading.
  • the shift register 15 has an output 99 for outputting the data in serial form.
  • the control input part 9 differs from the control input part 5 of the data compressor 1 in that the output 47 of the first register location of the shift register 40 is not required.
  • the outputs 48, 49 of the second and third register locations are connected to the sequence controller 8 in a manner to be described later.
  • the register positions 4 to 7 are in turn via the NOR gate 50 and the line 51 with the read input
  • the sequencer 8 has four registers, each of which is formed by a simple D flip-flop: a reload register 100, a characteristic register 101, a load inhibit register 102 and an address control register 103. Each of these registers 100, 102 and 103 has a CP input , a preset input pr, a D input and a Q and a und output. Register 101 has a clear input c1, a CP input, a D input and a Q and ⁇ output. The CP input of the reloading register 100 is connected to the output 48 of the second register location of the shift register 40 and the CP input of the load inhibiting register 102 is connected to the output 49 of the third register location of the shift register 40 connected.
  • the CP input of the characteristic value register 101 is connected via an inverter 104 to the output of an AND gate 105 with two inputs, the first input of which is connected to the Q output of the load inhibit register 102 and the other output of which is connected to the output of the seventh register position of the shift register 40 is.
  • the pr input of register 100 and the c1 input of register 101 are each connected to input 13 of the data expander.
  • the pr input of the load inhibit register 102 is connected to the output of an AND gate 106 with two inputs, one input of which is connected to the input 13 of the data expander 2 and the other input of which is connected to the output of a NAND gate 107 with two inputs.
  • One input of the NAND gate 107 is connected to the output of the fifth register position of the shift register 15 and the other input is connected to the output 96 of the counter 16 via an inverter 108.
  • the D input of the reloading register 100 is also connected to the output 96 of the counter 16, the D input of the characteristic value register 101 to the eighth, free output of the data outputs 95 of the memory 10 and the D input of the charge blocking register 102 to the ⁇ output of the Characteristic register 101 connected.
  • the ⁇ output of the characteristic value register 101 is connected to a first input of an AND gate 109 with two inputs, the other input of which is connected to the Q output of the reload register 100 and the output of which is connected to the shift input 97 of the shift register 15. Furthermore, two AND gates 110, 111 are provided, each with three inputs, the first input of which is connected to the output of the AND gate 105 and the third input of which is connected to the Q output of the reload register 100 is connected.
  • the second input of the AND gate 110 is connected via an inverter 112 and the second input of the AND gate 111 directly to the eighth data output of the data outputs 95 of the memory 10.
  • the output of the AND gate 110 is connected to the load input 98 of the shift register 15 and the output of the AND gate 111 to the load input 26 of the counter 16.
  • Another AND gate 113 with two inputs is connected at its first input to the Q output of the reload register 100, at its second input to the output 49 of the third register location of the shift register 40 and at its output to the counter input 27 of the counter 16.
  • the address control register 103 has a clear input, a preset input pr and a ⁇ output.
  • the clear input of the register 103 is connected to the output of a NOR gate 114 with two inputs, one input of which is connected to the output 48 of the second register location of the shift register 40 and the other input of which is connected to the input 13 of the data expander via an inverter 115 connected is.
  • the pr input of register 103 is connected to the output of a further two-input NOR gate 116, the first input of which is connected to the output of AND gate 110 and the second input of which is connected to the output of AND gate 111.
  • the ⁇ output of register 103 is connected to address input 38 of memory 10.
  • the NAND elements 109 and 110 as well as 111 and 113 are each realized together by a component 74 S 15.
  • the same components as for the corresponding circuit parts of the data compressor 1 are used for the other circuit parts of the data expander 2.
  • the operation of the data compressor 1 and the data expander 2 is to be shown on the basis of a bit pattern for the data to be compressed, as is shown in FIG. 5.
  • the successive data are shown as strips with black and white sections, of which a unit length of the black section should represent a binary zero and a unit length of the white section should represent a binary one.
  • the top line I represents the data stream to be compressed which is fed to the input 11 of the data compressor 1, the middle line II the compressed data record stored or to be transmitted in the memory 6 or 10 and the bottom line III the data expander 2 after the expansion Expanded data stream leaving output 14.
  • the data stream to be compressed in line I is, in accordance with the function of the compressor explained in the following, divided into periods 1, 2 ... with seven data units each, to which reference should be made below.
  • the data stream in line I in FIG. 5 is fed to the data compressor 1 in such a way that the data units reach the input 11 of the data compressor 1 one after the other from the left edge of line I.
  • FIGS. 6 to 17 The states of the data compressor 1 in the individual periods shown in FIG. 5 are shown in FIGS. 6 to 17, a register content of zero in the registers 15, 16, 55, 56 and 57 being identified by a black circle.
  • the initial state of the data compressor 1, in the at the input 12 is an "off" signal is shown in Fig. 6.
  • the “off” signal in the start-stop register 55 and in the characteristic value register 57 the content zero and via the set input 54 in the first register position of the shift register 40 a logical one and in the remaining register positions of the shift register 40 a logical one Set to zero.
  • the content of the shift register 15 and the counter 16 is still arbitrary.
  • the clock generator 39 is switched on via the OR gate 42 and supplies synchronous clock pulses to the shift register 15, the counter 16 and the shift register 40 via the clock inputs 22, 28 and 44
  • these clock signals have the effect that with each clock signal a further bit of the data stream present at the input 11 is transferred to the shift register 15 or in the shift register 15 each bit is shifted to the right by one register position in FIG.
  • this clock causes logic one to move one place up to the higher register locations with each clock signal, i.e. 6 is shifted to the right in FIG. 6, the remaining register locations having logic zeros, since the content of register location 7 determines the content of register location 1 in the subsequent cycle in each case via line 45.
  • Fig. 7 shown.
  • the logical one from register position 1 has moved to register position 5 of shift register 40.
  • the content of the E flip-flop is set to 1 via the connection of the CP input 59 of the start-stop register 55 to the register location 5.
  • the data stream present at input 11 has advanced five places into shift register 15 according to line I in FIG. 5.
  • a write command to the memory occurs via the OR gate 50 and the line 51 6 and the current content of the counter 16 is transferred to the memory 6.
  • this content will be overwritten at a later point in time since there is still no signal for changing the address at address input 38.
  • the comparator 17 produces a value K with level 1 at the output 31, which supplies a signal with level 1 to the charging input 26 of the counter 16 via the AND gate 75 and the OR gate 74 in cycle 1, so that the content of the first seven register locations of the shift register 15 are fed to the first seven memory locations of the counter 16. This content also appears at the data outputs 25 of the counter 16.
  • FIG. 9 shows the state of the data compressor 1 after the first two periods shown in FIG. 5, that is to say at the beginning of the third period.
  • the next seven bits of the incoming data stream namely seven zeros
  • the newly entered seven-bit sequence is "reason". This means that there are only zeros in shift register 15 at cycle 1 of the third period.
  • FIG. 11 shows the state of the data compressor 1 after the end of the fourth period shown in FIG. 5, that is to say at the beginning of the fifth period.
  • a clock signal is thus sent to the charging input 26 via the AND gate 75 and the OR gate 74, so that the content of the first seven Register positions of the shift register 15 are loaded in cycle 1 onto the first seven storage locations of the counter 16 and the next incoming data can then enter the shift register 15.
  • the output of the NAND gate 84 thus becomes 1 and in cycle 2 a signal with level 1 appears at the output 89, so that the address of the memory 6 is changed and the count 10111111 stored in the second address of the memory in the fourth period can no longer be overwritten and thus remains stored.
  • neither a load signal appears at output 79 nor a count signal at output 82 so that the content loaded in cycle 1 from shift register 15 into counter 16 is retained and is written into address 3 of memory 6 in cycles 4 to 7 can.
  • FIG. 12 shows the state of the data compressor 1 after the end of the fifth period shown in FIG. 5, that is to say at the beginning of the sixth period.
  • a signal with level 0 thus appears at the output 79 and it can be in cycle 1 the value from register 15 cannot be loaded into counter 16.
  • Fig. 5 is shown, each seven-bit sequences in the shift register 15, the bits of which were all the same. Therefore, the count of counter 16 has been reduced by 1 in each period in the manner described above in connection with the third period, so that counter 16 now has the content 00000000. The counter 16 has therefore given a signal at the end of the preceding period at the output 29 which indicates the zero level. This counter reading is now together with the identification bit
  • the signal from the output 29 is fed to the D input 63 of the zero value register 56 and sets the content of this register to zero.
  • the state of the data compressor 1 at the beginning of the following (5 + 126 + 1) th period is shown in FIG. 14.
  • the “off” signal was received at the input 12.
  • the ring counter formed by the shift register 40 also continues to run and sets the clock in clock 5 Contents of the memory E of the start-stop register 55 to zero.
  • This mark consists of a stop byte with the bit sequence 11111111. This bit sequence does not otherwise occur in the memory, since when a seven-bit sequence of unequal bits is stored, the identification bit 0 is stored and when successive seven-bit Following the same bits, a counter reading is stored which has at least one zero. The stop byte is therefore clearly recognizable as a stop mark.
  • the open collector NAND gate 33 is controlled via the NAND gate 81 in such a way that the output of the first register location 21 and thus the value of the first memory location 24 of the memory 16 during clocks 2 and 3 Level 1 is set.
  • the content 11111110 is thus loaded into the memory 16 with the loading signal generated in cycle 3 at the charging input 26.
  • the first seven bits of this memory content are written to the first seven memory locations of the present address of the memory 6 together with the identification bit 1 in the eighth memory location, so that the stop byte 11111111 is now stored there.
  • bar 5 the
  • the clock 39 is switched off in the next period of the ring counter 40.
  • the information arriving at clock 3 in counter 16 and stored in memory 6 during clocks 4 to 7 will be overwritten by new information which arrives after the next "on" signal.
  • cycle 5 the content zero is transferred from memory E 'to memory E'', so that a signal with level 0 appears at the Q output of memory E' * and the second input of OR gate 42 is also set to zero .
  • the output of the OR gate is striking Zero and the clock 39 is turned off.
  • the mode of operation of the data expander 2 will be explained using the circuit diagram in FIG. 4 and the schematic information representation in FIG. 5.
  • the information shown in FIG. 16 is present in the memory.
  • Registers 100 and 102 are also at value 1.
  • Register 101 and address control register 103 are at value 0.
  • the clock generator 39 is switched on, which clocks the shift register 15, the counter 16 and the ring counter 40 in the same way as for the data compressor.
  • the output of the NOR gate 114 drops to zero and the signal at the address input 38 of the memory 10 thus remains at a high level, so that the address has not yet been changed.
  • the content of address 1 of memory 10 is read from memory 10 and made available at data outputs 95.
  • the content read from memory at the end of bar 7 is still available due to the gate runtimes.
  • the preset 1 input of the address control register 103 is set to zero via the NOR gate 116 and the first address change from address 1 to address 2 is thus prepared.
  • a clear signal is applied to the address control register 103 via the NOR gate 114 and the output Q from A is thus set to 1 again.
  • the contents of address 2 are then read in cycles 4 to 7 and made available at the data outputs 95.
  • the last bit of the first seven bits shifted from the shift register 15 thus remains at the seventh register location of the shift register 15.
  • the output of the AND gate 111 goes high and causes the loading of the first seven bits of the data of the second address at the data outputs 95 into the counter 16.
  • the NOR gate 116 in turn causes the next address Prepared for change, which is carried out in bar 2 in the same way as in the second period.
  • the output of the AND gate 113 goes high and causes the counter to count up from the previously loaded content 10111111 to the content 01111111.
  • a value of zero is added to the CP input of the load inhibit register 102 via the output 49
  • Load inhibit register 102 is loaded, as a result of which the output Q of the load inhibit register 102 becomes zero and thus the output of the AND gate 111 is kept at a low level via the AND gate 105 and further charging is prevented until the clock 3 in a later period maximum counter reading of counter 16 is reached. In cycles 4 to 7, the content of the next address 3 is again made available at the data outputs 95.
  • the output of the AND gate 109 is always at a low level, so that the data in the shift register 15 are not shifted and with each clock signal from the clock generator 39 a bit is output by the shift register 15 which corresponds to the seventh register position of the Shift register corresponds to 15 standing bits. This bit is the last of the figure bytes shifted from register 15 in the second period, namely a zero bit.
  • the content of the first seven bits of the address 4 is loaded into the counter 16 because the identifier.
  • Q bit at the eighth position of address 4 1.
  • K 1 1 and thus the serial shifting of the shift register 15 is interrupted, so that the last bit of the preceding figure byte remains in the seventh position of the shift register 15 and is output in each case with the following clock signals from the clock generator 39. Zeros were added via input 20.
  • the address change is prepared as above, which is carried out in cycle 2 in the same way as described above.
  • the counter 16 is increased from the counter reading 20 00000001 loaded at the beginning of the sixth period to the counter reading 10000001.
  • the shift register 15 outputs a bit for each clock of the clock generator 39, which corresponds to the last figure bit of the last preceding figure byte 30 in the seventh register position of the shift register 15.
  • the counter reading of counter 16 is increased by 1. Since no more loading takes place, the address in cycle 2 is not changed.
  • the counter reading 11111111 is reached in cycle 3. A signal is thus generated at the output 96 of the counter 16 and the charge lock 102 is switched off at clock 5. However, since this counter reading is only reached in cycle 3, the counter reading in cycle 2 was still unequal
  • the principle of the data expander 2 is therefore that when a characteristic bit with the value 0 is detected in the eighth place of the data outputs 95 of the memory 10, the information from the first seven positions of the outputs 95 is loaded in parallel with a register (shift register 15) , which supplies this data serially to the data output 14, and that when a characteristic bit with the value 1 is detected, the content of the first seven places of the data outputs 95 of the memory 10 is interpreted as a counter reading and loaded into a counter (counter 16), from which the data are not supplied to data output 14.
  • the counter is incremented by 1 for each period and seven bits are output by the register (shift register 15), which are each equal to the bit that came from the memory 10 to the register (shift register 15) to the first register position 21 when the data was last loaded in parallel.
  • the data expander 2 is switched off.
  • the expander thus has a "switch” which directs the data from the data outputs 95 of the memory 10 depending on the identification bit either to the register and from there to the output or to the counter.
  • the identification bits are no longer required from the turnout and are removed from the information flow.
  • the data compressor 1 also contains one
  • Output switch which, depending on the output signal of the comparator 17, either passes on the "figure byte" with identification bit or the counter reading + identification bit.
  • the length of the "Bytes" resp. Bit sequences in a period can of course take any value. In this case, only the size of the register 15, the counter 16 and the memory 6 or 10 has to be adapted to the selected length of the bit sequence. Any number of identification bits can also be selected. With more identification bits, for example, "colors" of the spaces formed by the "basic bytes” can also be represented, for example four "color tones" with two identification bits. In another case, two identification bits can also identify a supplementary byte which, with f bits, identifies a color of an image part that is different from 2 f .
  • n-dimensional application 17 shows a further embodiment of a data compressor according to the invention.
  • the circuit has a converter 3, a controller 200 connected to the converter 3 and a buffer memory 210.
  • the buffer memory 210 is divided into an information data area 212, which is connected to the controller 200 via a line 202, and a control data area 211, which is connected to the controller via a line 201.
  • the buffer memory 210 has an output 213, which is connected to an external memory 6.
  • the converter 3 receives serial data at its data input 11, which it converts into parallel data.
  • the parallel data are present as eight bit-wide information units at the output 25 of the converter 3.
  • the controller 200 receives this information unit via the connection 203.
  • a comparator present in the controller 200 checks whether all data bits of the information unit are the same and correspond to the last data bit of the previous information unit. If this condition is not met, the information unit is written directly into the information data area 212 of the buffer memory 210 via the connection 202. Furthermore, an element counter contained in the controller 200 is increased by one.
  • the controller 200 then sets a bit in the control data area 211 of the buffer memory 210 to one via the connection 201, whose position in the control data area 211 corresponds to the counter reading of the element counter.
  • a repetition counter also present in the controller 200 is set to zero.
  • the comparator provides the match of all data bits of the information unit and the correspondence with the last data bit of the previous information unit, the repetition counter is increased by one.
  • the next information unit can then be supplied to the controller 200 via the connection 203. If the comparator again determines equality, the counter is increased again by one. If this does not determine equality, the counter reading of the repetition counter is written into the information data area 212.
  • the element counter is incremented by one and the controller 200 sets in the control data area
  • the length of the data record is dependent on the size of the buffer memory 210.
  • the status of the element counter is also written into the control data area 211 via the connection 201.
  • the controller 200 sets a further bit in the control data area 211 to the value one if compression of information units was possible, i.e. , if the comparator found equality while processing a data set, and set it to zero if it was not possible to compress information units.
  • the buffer memory 210 then transfers the entire control data area 211 and information data area in the event that the last bit set has the value one
  • a compression of the same information units in successive data sets can also be carried out with this circuit.
  • the current information units are compared in controller 200 with the respective information units of the previous data record. If a match is found, the corresponding information unit is not transferred to the information data area 212, and a bit in a corresponding position is set to the value one in a separate area of the control data area 211. In addition, a further bit is also set to one here if a line-by-line compression could take place and to zero if this compression was not possible.
  • the data stored in memory 6 are rotated through 90 ° to compress successive data sets, i.e. the rows and columns of the data stored in matrix form are interchanged. Data compression is then carried out again as described above.
  • the controller 200 is also designed such that the control data present in the control data area 211 can itself be compressed again at the end of a data record. The compression method described above is used for this, the newly obtained control data being written in a further control data area of the buffer memory 210.
  • the data compressed in this way is converted back into original data using the data expander shown in FIG.
  • the data expander has essentially the same functional blocks as the data compressor of FIG. 17.
  • the circuit of Fig. 18 differs from the circuit in Fig. 17 only in that the directions of the data paths are reversed. The mode of operation of the data expander is described below with reference to FIG. 18.
  • a data record is transferred from memory 6 to buffer memory 210.
  • the controller 200 now reads from the control data area 211 the bit that characterizes compression of the data record. If this bit has the value zero, it is, as described above, an uncompressed data record.
  • the information units in the information data area 212 are then output unchanged by the controller 200 to the converter 3, which converts them into a serial data stream and outputs the data at the data output.
  • the controller 200 If it is a compressed data record, the controller 200 reads the element counter reading from the control data area 211 into the element counter present in the controller 200. The first information unit is then transmitted to the controller 200 from the information data area 212. On the basis of the control data bit in the control data area 211, the position of which corresponds to the position of the information unit in the information data area 212, the controller 200 decides whether the information unit is a compressed data byte or an uncompressed data byte. In the case of an uncompressed
  • the information unit is output directly to the converter 3 and the element counter is decreased by one.
  • the controller 200 then reads the next information unit.
  • the read-in information unit is interpreted by the controller 200 as a counter reading.
  • the controller 200 outputs a number of data bytes corresponding to this counter reading to the converter 3, the data bits of which are identical to one another and equal to the last data bit of the preceding information unit.
  • the element counter is decreased again by one and the next information unit is transmitted to the controller 200. This process is repeated until the element counter is counted to zero and the entire data set is thus output.
  • the next data record is then transferred from the memory 6 to the buffer memory 210.
  • the compressed information stored in the memory 6 can thus be completely recovered.
  • the reduction in the amount of data achieved in this way can save a considerable amount of storage space when storing the data, for example when storing matrices with unoccupied fields on magnetic disks, which also increases the access speed accordingly.
  • the data is reduced or the access speed is increased by at least a factor of 10.
  • the transmission of the compressed data also saves on transmission time.
  • "gaps" saved between the data to be transmitted for example, duplicates of the data to increase the transmission security, parts of other programs in the multiplex process for better channel utilization or, in addition, color information, for example, can also be transmitted.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Un système de compression (1) de données utilisé pour transmettre des données comprend un registre (15) où une unité d'information de donnée d'entrée est enregistrée, un système de conversion pour transformer les données et une sortie (25) pour les données transformées, de même qu'un système de commande (4, 5). Afin de pouvoir exécuter le compactage des données sans pertes d'informations, l'invention comprend un comparateur connecté à la sortie du registre (15), et un compteur (16) commandé par le comparateur. Le comparateur (17) vérifie toutes les données de l'unité d'information, et le système de commande (4, 5) est conçu pour introduire le contenu du registre (15) dans la sortie (25) en cas de non-uniformité, et pour produire un bit de repère et faire avancer le compteur d'une position en cas d'uniformité. Lorsque deux unités successives d'information ne s'accordent pas, l'état du compteur est introduit avec le bit de repère dans la sortie (25). Un système associé d'expansion de données (2) contient les données de sortie du système de compactage (1), vérifie le bit de repère et transmet à sa sortie une unité d'information n'ayant pas de bit de repère correspondant; d'autre part, si un bit de repère correspondant est présent, l'unité d'information est introduite dans un compteur et une unité d'information dont les données sont identiques à celles de la première et ont une valeur prédéterminée est introduite dans la sortie, en même temps que le compteur (16) est incrémenté à chaque fois d'une position, autant de fois qu'il ne faut pour que l'état du compteur atteigne une valeur prédéterminée.
PCT/EP1985/000450 1984-09-06 1985-09-05 Systeme de compression et d'expansion de donnees pour la transmission ou le stockage de donnees WO1986001660A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19843432837 DE3432837A1 (de) 1984-09-06 1984-09-06 Datenkompressions- und datenexpandiereinrichtung zum uebertragen bzw. speichern von daten
DEP3432837.8 1984-09-06

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WO1986001660A1 true WO1986001660A1 (fr) 1986-03-13

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EP (1) EP0193553A1 (fr)
AU (1) AU4774785A (fr)
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US5012470A (en) * 1988-09-22 1991-04-30 Ricoh Company, Ltd. Data terminal equipment and data transmission control method
DE19921298A1 (de) * 1999-05-07 2000-11-16 Bosch Gmbh Robert Verfahren zur Komprimierung und Dekomprimierung von Daten und Vorrichtung

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GB8629531D0 (en) * 1986-12-10 1987-01-21 Fitzpatrick P C Exercise apparatus
AU624205B2 (en) * 1989-01-23 1992-06-04 General Electric Capital Corporation Variable length string matcher

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AU2889671A (en) * 1971-05-14 1972-11-16 Encoding technique for digitised facsimile and data transmissions
DE2607848B1 (de) * 1976-02-26 1976-12-23 Licentia Gmbh Verfahren und vorrichtung zum speichern eines zweiwertigen digitalen signals
US4057834A (en) * 1973-04-12 1977-11-08 Kokusai Denshin Denwa Kabushiki Kaisha Signal compression system for binary digital signals

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IT964421B (it) * 1971-09-08 1974-01-21 Honeywell Inf Systems Metodo per condensare dati per la trasmissione fra dispositivi di comunicazione di dati
US4054951A (en) * 1976-06-30 1977-10-18 International Business Machines Corporation Data expansion apparatus

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AU2889671A (en) * 1971-05-14 1972-11-16 Encoding technique for digitised facsimile and data transmissions
US4057834A (en) * 1973-04-12 1977-11-08 Kokusai Denshin Denwa Kabushiki Kaisha Signal compression system for binary digital signals
DE2607848B1 (de) * 1976-02-26 1976-12-23 Licentia Gmbh Verfahren und vorrichtung zum speichern eines zweiwertigen digitalen signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012470A (en) * 1988-09-22 1991-04-30 Ricoh Company, Ltd. Data terminal equipment and data transmission control method
DE19921298A1 (de) * 1999-05-07 2000-11-16 Bosch Gmbh Robert Verfahren zur Komprimierung und Dekomprimierung von Daten und Vorrichtung
US6737991B1 (en) 1999-05-07 2004-05-18 Robert Bosch Gmbh Method and device for compressing and decompressing data

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AU4774785A (en) 1986-03-24
DE3432837A1 (de) 1986-03-06
EP0193553A1 (fr) 1986-09-10

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