WO1982004515A1 - Dispositif de reglage de synchronisation de bits - Google Patents

Dispositif de reglage de synchronisation de bits Download PDF

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Publication number
WO1982004515A1
WO1982004515A1 PCT/GB1982/000161 GB8200161W WO8204515A1 WO 1982004515 A1 WO1982004515 A1 WO 1982004515A1 GB 8200161 W GB8200161 W GB 8200161W WO 8204515 A1 WO8204515 A1 WO 8204515A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit
synchronization
data processing
processing system
codeword
Prior art date
Application number
PCT/GB1982/000161
Other languages
English (en)
Inventor
Inc Motorola
Original Assignee
Beesley Graham Edgar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beesley Graham Edgar filed Critical Beesley Graham Edgar
Publication of WO1982004515A1 publication Critical patent/WO1982004515A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H04B14/044—Sample and hold circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Definitions

  • This invention relates to a data processing system of the kind (hereinafter referred to as the kind set forth) in which there is a transmission of data of a code format having a pattern that provides a plurality of reversals 1011010 etc. from which it is desirable to maintain bit synchronization for the incoming data once initial synchronization is obtained.
  • This desideratum is achieved according to the present invention by a data processing system of the kind set forth wherein after a first synchronization codeword is recognized at least a part of any following synchronization codeword is sampled at least twice per bit and compared with the known structure of the bits of known synchronization codeword to enable the bit structure of best fit with the known bit structure to be accepted by the system to derive the best sample instant of the transmission of said data.
  • the best fit may conveniently be a running total or summation of least errors when compared with the structure.
  • the codewords are sampled not twice but three times of which one time is both early and late of the other times and comparison is performed with the known structure of the synchronization codeword.
  • the said one time is taken substantially at the position corresponding to the optimum sampling time obtained from the previous synchronization.
  • One satisfactory analysis of a 32 bit synchronization codeword is to take three samples, of which the inner is both early and late of the two other samples by say l/8th of a bit width.
  • Other spacings than 1/8th may be used to advantage but owing to drift error it should not come too close to the value of the said error. For example where the drift error is about 1/13th of a bit width, the sample spacing should exceed that value.
  • Figure 1 shows seven bits of a 32 bit synchronization codeword.
  • Figure 2 is a functional block diagram of one bit synchronization adjuster
  • Figure 3 is a flow diagram of operations to be performed by the memory and microprocessor of Figure 2.
  • the substantially centrally placed sample is conveniently called the inner sample (l) and the sample early of I (E) and the sample late of I (L). Error computation is given with relation to Figure 1 of the drawing and this is compared with the known bit structure of the synchronization codeword which is shown as K. It is readily seen from the figure that the received synchronization codeword R has blemishes due to noise and is sampled three times at I.E. and L where I is substantially centrally placed of the bit width B W the distances between I and E and I and L being in each case 1/8 B W .
  • the circuitry of one data processing system operates as follows: During the reception of the codeword a number of separate sampling instants are used and repeated in the same relationship for each bit of the codeword. In this way a number of versions of the received codeword may be built-up one corresponding to each of the sampling instants used. The version of the codeword having the least errors and giving the best fit with the known structure of the code word will then
  • FIG. 2 One specific embodiment of this function utilizes a microprocessor based system ( Figure 2).
  • Figure 3 The flow chart associated with this function is Figure 3 and a listing is attached in the appendix A.
  • a radio pager comprises a receiver board 10 having an aerial 11 by which a signal enters a radio frequency amplifier 12 a 1st mixer 13 coupled to a 1st oscillator 14 to a 1st intermediate frequency amplifier 15; from which it passes inter alia via a 2nd mixer 16 to an audio limiter 17 connected to the input/output of the microprocessor IS (MC 146805 E2) which is related to the memory of ROM (MCM65516) 19.
  • the MPU will receive from the ROM a logical sequence set out in the flow sheet of Figure 2 wherein:-

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Systeme de traitement de donnees du type dans lequel a lieu une transmission d'un format de code possedant une forme presentant une pluralite d'inversions 1011010 etc. a partir de laquelle il est souhaitable de maintenir la synchronisation de bits pour les donnees d'entree une fois que la synchronisation initiale est obtenue. Le systeme se caracterise en ce qu'apres qu'un premier mot de code de synchronisation est reconnu, au moins une partie de tout mot de code de synchronisation suivant est echantillonne au moins deux fois (ou trois fois) par bit et compare a la structure connue des bits d'un mot de code de synchronisation connu pour permettre a la structure de bit de s'adapter au mieux a la structure de bit connue afin d'etre acceptee par le systeme pour echantillonner les donnees d'entree. Le meilleur ajustement peut etre constitue par un total cumule ou par une somme des plus petites erreurs comparees a la structure.
PCT/GB1982/000161 1981-06-16 1982-05-28 Dispositif de reglage de synchronisation de bits WO1982004515A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB08118501A GB2101851A (en) 1981-06-16 1981-06-16 Bit synchronization adjuster
GB8118501810616 1981-06-16

Publications (1)

Publication Number Publication Date
WO1982004515A1 true WO1982004515A1 (fr) 1982-12-23

Family

ID=10522546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1982/000161 WO1982004515A1 (fr) 1981-06-16 1982-05-28 Dispositif de reglage de synchronisation de bits

Country Status (4)

Country Link
EP (1) EP0081500A1 (fr)
JP (1) JPS58501488A (fr)
GB (1) GB2101851A (fr)
WO (1) WO1982004515A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268694A1 (fr) * 1986-11-22 1988-06-01 ANT Nachrichtentechnik GmbH Méthode pour la synchronisation sur des signaux émis en multiplexage par répartition dans le temps et pour la récupération d'horloge
EP0282202A2 (fr) * 1987-03-03 1988-09-14 Advanced Micro Devices, Inc. Circuit de recherche et de synchronisation de préambule
EP0306002A1 (fr) * 1987-09-01 1989-03-08 Siemens Aktiengesellschaft Procédé d'ajustement adaptatif de phase dans un dispositif d'interconnexion de signaux numériques synchronisés à large bande

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2225198B (en) * 1988-09-20 1993-05-05 Texas Instruments Ltd Improvements in or relating to digital signal processors
US6914947B2 (en) 2001-02-28 2005-07-05 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for handling time-drift

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3435424A (en) * 1967-03-03 1969-03-25 Burroughs Corp Synchronizing system
FR2180988A1 (fr) * 1972-04-19 1973-11-30 Int Standard Electric Corp
US4189622A (en) * 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
FR2460072A1 (fr) * 1979-06-22 1981-01-16 Henry Michel Dispositif de regeneration de signaux electriques impulsionnels cadences notamment de signaux a modulation par impulsions de codage
GB2086106A (en) * 1980-10-13 1982-05-06 Motorola Ltd Pager Decoding System with Intelligent Synchronisation Circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3435424A (en) * 1967-03-03 1969-03-25 Burroughs Corp Synchronizing system
FR2180988A1 (fr) * 1972-04-19 1973-11-30 Int Standard Electric Corp
US4189622A (en) * 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
FR2460072A1 (fr) * 1979-06-22 1981-01-16 Henry Michel Dispositif de regeneration de signaux electriques impulsionnels cadences notamment de signaux a modulation par impulsions de codage
GB2086106A (en) * 1980-10-13 1982-05-06 Motorola Ltd Pager Decoding System with Intelligent Synchronisation Circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268694A1 (fr) * 1986-11-22 1988-06-01 ANT Nachrichtentechnik GmbH Méthode pour la synchronisation sur des signaux émis en multiplexage par répartition dans le temps et pour la récupération d'horloge
EP0282202A2 (fr) * 1987-03-03 1988-09-14 Advanced Micro Devices, Inc. Circuit de recherche et de synchronisation de préambule
EP0282202A3 (fr) * 1987-03-03 1990-04-25 Advanced Micro Devices, Inc. Circuit de recherche et de synchronisation de préambule
EP0306002A1 (fr) * 1987-09-01 1989-03-08 Siemens Aktiengesellschaft Procédé d'ajustement adaptatif de phase dans un dispositif d'interconnexion de signaux numériques synchronisés à large bande

Also Published As

Publication number Publication date
GB2101851A (en) 1983-01-19
EP0081500A1 (fr) 1983-06-22
JPS58501488A (ja) 1983-09-01

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