Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Definitions

• This invention relates to processes for manu- facturing semiconductor non-volatile memory devices of the kind having a gate structure which includes a gate oxide layer provided on a semiconductor substrate, a nitride layer provided on said gate oxide layer and a polysilicon gate electrode overlying said nitride layer.
• SNOS silicon (polysilicon)-nitride-oxide- semiconductor.
• SONOS is silicon (polysilicon)-oxide-nitride- oxide-semiconductor.
• Gate oxide refers to the silicon oxide dielectric formed between the semiconductor and the silicon nitride (SNOS, SONOS) in the active area of a device such as a capacitor or field-effect transistor.
• Interfacial oxide refers to the silicon oxide layer formed between the polysilicon and the silicon nitride dielectric in SONOS structures. Retention and endurance are two very important characteristics of thin gate oxide, nitride non-volatile memory devices. Retention is a measure of the ability of the memory device to retain its stored charge sub ⁇ sequent to a write or erase operation. Endurance is a measure of the retention of the memory device as a function of the number of write-erase cycles to which the device has been subjected.
• High temperature processing is considered to be that at a temperature substantially higher than the nitride deposition temperature.
• the memory nitride which can be deposited at a temperature of about 700°C.-750°C. , is subjected to subsequent high temperature processing at, for example, 900°C. to 1000°C. , which degrades memory characteristics such as retention and endurance.
• This high temperature processing in ⁇ cludes for example, the high temperature (900°C.) phos ⁇ phorus diffusion step used in doping source, drain and polysilicon gates and oxidation of the polysilicon at 900°C.-1000°C. for generating masking oxide.
• silicon gate memory structures frequently have relatively low retention and endurance as compared to metal gate struc ⁇ tures (such as aluminum or aluminum alloy metal gate structures).
• metal gate struc ⁇ tures such as aluminum or aluminum alloy metal gate structures.
• the article relates to improved SONOS structures and discusses the relatively poor retention of silicon gate structures: for example, Chen indicated that 15 Angstrom thick gate oxide provides retention measured in years in typical MNOS structures, but only in hours in SONOS structures. Chen increased the retention of his SONOS devices by increasing the thickness of the gate oxide to 30 Angstroms. However increasing the gate oxide thickness has the disadvantage of slowing write and erase speeds.
• a process for manufacturing a semi ⁇ conductor non-volatile memory device of the kind speci ⁇ fied characterized by the steps of loading the device into an annealing vessel, raising the temperature of the vessel to within the range 600-1100°C. in hydrogen ambient, maintaining the temperature and hydrogen ambient for a sufficient time to anneal the device, and reducing the temperature of the vessel to about 100°C. or less while maintaining the hydrogen ambient.
• Fig. 1 is a cross-sectional representation of a silicon gate memory device which can be fabricated using the hydrogen anneal of the present invention.
• Fig. 2 is a schematic representation of apparatus for hydrogen annealing devices using the method of the present invention.
• Fig. 3 is a graphical represention of the retention and endurance characteristics of unannealed SONOS devices.
• Fig. 4 is a graphical representation of the retention and endurance characteristics of SONOS devices which have been hydrogen annealed using the method of the present invention.
• FIG. 1 A cross section of a fabricated n-channel SONOS memory trans ⁇ istor 10 is shown in Fig. 1.
• the difference between an SNOS device (not shown) and the illustrated SONOS device 10 is the absence in the SNOS device of the interfacial oxide layer 13.
• the invention will be described with reference to the SONOS device 10, keeping in mind that it is applicable to SNOS devices as well.
• the illustrated transistor 10 is formed by the well-known LOCOS (localized oxidation of silicon) process, although certainly the invention is not limited to this process.
• LOCOS localized oxidation of silicon
• source 17 and drain 18 are formed in ⁇ silicon substrate 16 by n-type impurities such as phosphorus (or p-type impurities such as boron for p-channel) using diffusion or ion implantation techniques.
• Field oxide 21 can be formed by wet thermal oxidation of the substrate 16, to a typical thickness of 14kA to 16kA (14,000 to 16,000 Angstroms).
• Memory gate oxide 11 of thickness 10-30 Angstroms is preferably formed by dry thermal oxidation, typically within the approximate range 600-750°C. in an oxygen-nitrogen ambient.
• the memory memory nitride 12 can be deposited by the chem- ical vapor deposition technique in a vertical reactor at a temperature of about 700-750°C. using an ammonia- silane-nitrogen ambient, to a thickness of about 350- 550 Angstroms.
• Interfacial oxide 13 may be formed by several methods, for example by high temperature (975°C.) wet oxygen thermal conversion of a portion of the top layer of the memory silicon nitride 12 to oxide 13. Inter ⁇ facial oxides 13 of 70-150 Angstroms thickness have been used.
• Polysilicon gate 14 can be deposited by either the atmospheric CVD (Chemical Vapor Deposition) or low pressure CVD technique over the temperature range
• Oxide isolation layer 22 is a low temperature ( 425°C) , deposited oxide 6kA° to 12kA° in thickness.
• the memory silicon nitride 12 is subjected to the high temperature ( 900°C.) phosphorus diffusion step used in doping source, drain and polysilicon gates.
• the nitride may also be subjected to a 1000°C. doped oxide reflow step in a nitrogen ambient.
• the SONOS transistor 10 is subjected to the hydrogen anneal of this invention, as described below, to enhance retention and endurance.
• the hydrogen anneal is performed after opening contact windows such as 35, 37 and 38, etc. in the oxide isolation layer 22 using standard photolithographic masking and etching techniques.
• contacts 25, 27 and 28 of material such as aluminum are formed using standard metallization techniques.
• a vertical reactor system 40 for practicing the hydrogen anneal of of the present invention.
• the system comprises a vessel such as a glass bell jar 41, a graphite suscep- tor 42 for holding the devices 10, cooling (water and rf heating coil) 43, and gas inlet tube 44.
• Gas here 2 and H 2
• the gas mixture and flow rate are controlled by valves 48, 49 and 51.
• Valves 48 and 49 can be used to control the relative proportions of hydrogen and nitrogen in the mixture, and valve 51 to control the gas flow rate.
• Gas flow rate is indicated by meter 52.
• a suitable hydrogen anneal process comprises: 1. loading the silicon gate trans ⁇ istor 10 onto the susceptor 42 of the reactor 40; 2. purging the reactor with nitrogen.
• OMPI WIPO e.g., for five minutes, typically at or near room temperature (valves 48 and 51 open; valve 49 closed) ;
• step 1 the loading step
• pre-condi ⁇ tion clean the bell jar 41 by heating to about 900°C. and maintaining the temperature for about 15 minutes in the presence of nitrogen (flow rates of about 48 liters/ min. have been used) , then shutting off the temperature and gas flow.
• the silicon wafer 16 from which the device is fabricated be in a 100% hydro ⁇ gen ambient when the temperature is raised from room temperature to the annealing temperature during step 4, and when the temperature is lowered from 800°C. during step 6 to avoid negating the beneficial effects of the hydrogen anneal.
• O PI V/IPO nealing vessel and system are not restricted to the particular vertical reactor 40 or to a vertical reactor at all: for example, a furnace tube (not shown) with suitable safety precautions should constitute a suitable annealing chamber.
• Figs. 3 and 4 The retention and endurance characteristics of unannealed SONOS devices and hydrogen-annealed SONOS devices 10 are shown in Figs. 3 and 4, respectively.
• the devices comprised the n- channel silicon gate field-effect transistors 10 de ⁇ scribed previously.
• the transistors were formed in accordance with the exemplary procedures described above.
• the substrate 16 was ⁇ 100> p-type, 15-20 ohm- cm silicon.
• the field oxide 21 was about 15kA thick as grown; oxide 22 was about 6kA thick.
• the approximate dimensions of the gate structure 15 are 10-15 Angstroms for the gate memory oxide 11; 500 Angstroms for the gate memory nitride 12; 70 Angstroms for the interfacial oxide 13; and 3.5kA for the polysilicon gate 14.
• annealed devices were annealed as described above in accordance with the principles of this invention.
• the anneal temperature was 800°C; the hydrogen flow rate was 48 liters/min. (steps 4, 5 and 6).
• the metallization was 14kA° thick aluminum. The parts were packaged in metal cans to facilitate handling and testing and avoid interaction with the ambient.
• the retention-endurance data of Figs. 3 (unannealed) and 4 (annealed) were obtained by: (1) initializing the FETs by determining the initial written (or "1") and erased (or "0") threshold voltages V ⁇ ; (2) generating uncycled retention-curves by storing the devices at an elevated temperature (125°C) for the times
• OMPI shown in Figs. 3 and 4 and determining the threshold voltages at intervals during this time; (3) write-erase cycling the FETs 10 times; (4) reinitializing the FETs per step 1; (5) and generating retention curves for the _ 5 - 10 cycles by again storing at elevated temperature per step 2.
• the initialization procedure (steps 1 and 4), i.e. obtaining the initial written and erased state threshold voltages, involved applying +25 volts for
• step 3 was done at room 5 temperature using an applied gate voltage of +_ 25 volts and a 10 millisecond pulse width for both polarities.
• the source, drain and substrate were all tied to ground during the write-erase cycling.
• the storage-at-temperature data for the 0 uncycled and cycled parts were obtained by first placing the packaged parts in an oven at 125°C. in an air ambient to accelerate charge decay. The parts were removed from the oven at various time intervals and the gate voltage (V tint) required for a 20 5 microamp drain-source current (I> DS ) was measured and recorded at room temperature.
• VERT gate voltage
• I> DS microamp drain-source current
• the absolute threshold voltage decay rates are sig ⁇ nificantly improved for the hydrogen annealed devices as compared to the non-annealed parts. More important ⁇ ly, the normalized threshold voltage window closure is lower for the hydrogen annealed parts than for the non- annealed parts.
• memory gate nitride layer 12 was deposited in a vertical reactor at atmospheric pressure, it is expected that the beneficial effects of hydrogen annealing should also be manifested by memory nitride layers deposited by other techniques, for example, low pressure CVD nitride layers.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Plasma & Fusion (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Non-Volatile Memory (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Static Random-Access Memory (AREA)

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• 1980
  • 1980-08-07 JP JP50199380A patent/JPS56501028A/ja active Pending
  • 1980-08-07 WO PCT/US1980/001020 patent/WO1981000487A1/en not_active Application Discontinuation
• 1981
  • 1981-02-24 EP EP19800901693 patent/EP0034168A4/en not_active Withdrawn

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