UST977006I4 - Read only memory with optimized dimension for improved performance and chip area utilization - Google Patents
Read only memory with optimized dimension for improved performance and chip area utilization Download PDFInfo
- Publication number
- UST977006I4 UST977006I4 US05/899,615 US89961578A UST977006I4 US T977006 I4 UST977006 I4 US T977006I4 US 89961578 A US89961578 A US 89961578A US T977006 I4 UST977006 I4 US T977006I4
- Authority
- US
- United States
- Prior art keywords
- dimension
- read
- memory
- lines
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US74714076A | 1976-12-03 | 1976-12-03 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US74714076A Continuation | 1976-12-03 | 1976-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST977006I4 true UST977006I4 (en) | 1978-12-05 |
Family
ID=25003811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US05/899,615 Pending UST977006I4 (en) | 1976-12-03 | 1978-04-24 | Read only memory with optimized dimension for improved performance and chip area utilization |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | UST977006I4 (https=) |
| JP (1) | JPS5369553A (https=) |
| FR (1) | FR2373164A1 (https=) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3541543A (en) * | 1966-07-25 | 1970-11-17 | Texas Instruments Inc | Binary decoder |
-
1977
- 1977-10-18 FR FR7732159A patent/FR2373164A1/fr active Granted
- 1977-10-26 JP JP12770577A patent/JPS5369553A/ja active Pending
-
1978
- 1978-04-24 US US05/899,615 patent/UST977006I4/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2373164A1 (fr) | 1978-06-30 |
| JPS5369553A (en) | 1978-06-21 |
| FR2373164B1 (https=) | 1980-08-08 |
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