UST977006I4 - Read only memory with optimized dimension for improved performance and chip area utilization - Google Patents

Read only memory with optimized dimension for improved performance and chip area utilization Download PDF

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Publication number
UST977006I4
UST977006I4 US05/899,615 US89961578A UST977006I4 US T977006 I4 UST977006 I4 US T977006I4 US 89961578 A US89961578 A US 89961578A US T977006 I4 UST977006 I4 US T977006I4
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US
United States
Prior art keywords
dimension
read
memory
lines
word
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Pending
Application number
US05/899,615
Inventor
Peruvemba S. Balasubramanian
Edwin C. Grazier
John D. Henke
Robert P. Latham
Martin J. Myers
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of UST977006I4 publication Critical patent/UST977006I4/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

a read only memory on a semiconductor substrate having metal word lines and diffused bit lines with optimized dimensions for a selected performance and storage capacity with the metal lines being along an X dimension and the diffused lines being orthogonally related to the metal lines along a Y dimension. The X dimension for the substrate is given by the relation X = 2N · WL · K1 where 2N is an integer definitive of the number of words on a metal line where N is any integer power greater than zero; WL is word length which equals the number of storage devices per word selected for a word and K1 is a constant definitive of the average spacing in mils between the storage devices along the first length, and the Y dimension being given by a second relation Y = K2 · QN where K2 is a constant definitive of the spacing in mils between the adjacent rows of storage devices along the second length and Q is the number of said words. Changing the aspect ratio for an array permits the performance of a read only memory to be changed to a different set of X and Y dimensions.
US05/899,615 1976-12-03 1978-04-24 Read only memory with optimized dimension for improved performance and chip area utilization Pending UST977006I4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74714076A 1976-12-03 1976-12-03

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US74714076A Continuation 1976-12-03 1976-12-03

Publications (1)

Publication Number Publication Date
UST977006I4 true UST977006I4 (en) 1978-12-05

Family

ID=25003811

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/899,615 Pending UST977006I4 (en) 1976-12-03 1978-04-24 Read only memory with optimized dimension for improved performance and chip area utilization

Country Status (3)

Country Link
US (1) UST977006I4 (en)
JP (1) JPS5369553A (en)
FR (1) FR2373164A1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder

Also Published As

Publication number Publication date
FR2373164B1 (en) 1980-08-08
FR2373164A1 (en) 1978-06-30
JPS5369553A (en) 1978-06-21

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