USRE41841E1 - Method for making a silicon substrate comprising a buried thin silicon oxide film - Google Patents

Method for making a silicon substrate comprising a buried thin silicon oxide film Download PDF

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Publication number
USRE41841E1
USRE41841E1 US11/208,132 US20813200A USRE41841E US RE41841 E1 USRE41841 E1 US RE41841E1 US 20813200 A US20813200 A US 20813200A US RE41841 E USRE41841 E US RE41841E
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silicon
germanium
buffer layer
layer
thin
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Malgorzata Jurczak
Thomas Skotnicki
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Mind Fusion LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Definitions

  • the present invention generally relates to a method of fabricating a silicon substrate having a thin buried silicon oxide layer (SOI substrate) and in particular to a method of this sort which makes it possible to produce an SOI substrate having a buried silicon oxide layer that is extremely thin and has excellent uniformity.
  • SOI substrate thin buried silicon oxide layer
  • a first method of fabricating an SOI substrate known by the name of “SIMOX technology”, consists of forming the buried SiO 2 layer in a silicon substrate by implanting oxygen at high dose followed by annealing at a temperature greater than 1300° C.
  • a major drawback of this method is that it requires nonstandard equipment. Furthermore, the length of time for the process of implanting oxygen at high dose considerably reduces the production efficiency.
  • the substrates obtained by this method also suffer from inadequate quality of the buried silicon oxide layer and of the thin silicon layer (high pinhole density).
  • the thin layers are determined by the implantation process, this method makes it difficult to achieve thicknesses of less than 50 nm for the thin silicon layer and 80 nm for the buried SiO 2 layer.
  • a second method known by the name of “BESOI technique”, consists of forming a thin SiO 2 film on a surface of a first silicon body, then bonding this first body to a second silicon body by means of the thin SiO 2 film, and finally, removing part of one of the silicon bodies by mechanical grinding and polishing in order to form the thin silicon layer above the buried silicon oxide layer.
  • the silicon oxide layer on the first silicon body is formed by successively oxidizing the surface of this first body, then etching the oxide layer formed in order to obtain the desired thickness.
  • This method only allows relatively thick buried silicon oxide layers and silicon layers to be produced on the buried silicon oxide because of the poor control of the etching method. Furthermore, the thin layers obtained by this method have poor uniformity.
  • a third method known by the name of “SMART CUT technology”, consists of forming, by oxidation, a thin silicon oxide layer on a first silicon body, then implanting H + ions in the first silicon body in order to form a cavity plane in this first silicon body under the thin silicon oxide layer. Subsequently, by means of the thin silicon oxide layer, this first body is bonded to a second silicon body and then the assembly subjected to thermal activation in order to transform the cavity plane into a cleaving plane. This makes it possible to recover, on the one hand, an SOI substrate and, on the other hand, a reuseable silicon body.
  • This method requires the implantation of a high dose of hydrogen atoms. In spite of using atoms of smaller size for the implantation, the surface of the thin silicon layer obtained is also damaged. Furthermore, since the thickness of the thin silicon layer is defined by the implantation energy of the hydrogen atoms, it is difficult to make this thickness less than about 50 nm.
  • a method of fabricating an SOI substrate that can be implemented in standard equipment may also be desired.
  • the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
  • the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
  • the method of fabricating a silicon substrate having a thin buried silicon oxide layer includes:
  • the thin buffer layers made of Ge and germanium-silicon alloys of the first element may be produced by epitaxial deposition.
  • the thin buffer layers are produced by well-known methods of vapor deposition or of molecular beam epitaxial deposition, such that the thin silicon layer may have a very small thickness of a few nanometers while still having a suitable uniformity, typically from 1 to 50 nm.
  • the thin buried oxide layer may be produced by a known thermal oxidation method, such that it is possible to obtain an oxide layer of very high quality with a virtually arbitrary thickness that can vary from 2 nm to 400 nm.
  • the bonding of the first and of the second elements can be carried out by using the Van der Waals forces.
  • the assembly can possibly be subjected to annealing.
  • the buffer layer of the first element may consist of pure germanium, of a silicon-germanium alloy or of a silicon-germanium alloy containing carbon. More particularly, Si 1-x Ge x alloys (0 ⁇ x ⁇ 1) or Si 1-x-y Ge x C y alloys (0 ⁇ x ⁇ 0.95 and 0 ⁇ y ⁇ 0.05) can be used.
  • the germanium and the Si 1-x Ge x and Si 1-x-y Ge x C y alloys have very high selectivity to chemical etching by solutions or to anisotropic plasma etching.
  • the proportion of germanium in the alloy is at least equal to 10% by weight, and preferably equal to or greater than 30% by weight.
  • the use of the silicon-germanium alloy containing a small proportion of carbon makes it possible to reduce the high stresses between the silicon layers and the buffer layer. Thus, it is possible to use alloys with higher germanium concentrations and, consequently, with better etching selectivity, while producing a relaxation of the stresses. It is also possible to form a buffer layer made of a silicon-germanium alloy having a germanium concentration gradient (relaxed SiGe buffer layer). In this type of buffer layer, the germanium concentration increases from the silicon body of the first element.
  • the buffer layers may have a surface free of dislocations (all the dislocations and defects being located in the low part of the buffer layer), which provides good conditions and good continuity for the epitaxial growth of the thin single-crystal silicon layer which is to be deposited later.
  • the concentration profile of the germanium can be nonuniform.
  • the Ge concentration can be 0%, then increase to 50% (or 70% and even 100%), and then decrease down to 0%.
  • a high molar fraction of Ge in the SiGe alloy (in particular in the middle of the layer) provides, on the one hand, a very high selectivity of the etching method and, on the other hand, freedom from the risk of relaxation of the Si film.
  • FIGS. 1a to 1 e depict the main steps of a first embodiment of the method of the invention.
  • FIGS. 2a to 2 e depict the main steps of a second embodiment of the method of the invention.
  • a first embodiment of the method of the invention starts, as shown in FIG. 1a , with the successive deposition by epitaxy (for example, by chemical vapor deposition or by molecular beam epitaxy) of a layer 2 a of germanium, or a silicon-germanium alloy possibly including a small proportion of carbon, then of a thin silicon layer 3 a.
  • epitaxy for example, by chemical vapor deposition or by molecular beam epitaxy
  • the buffer layer 2 a and the silicon layer 3 a have a thickness of from 1 to 50 nm.
  • a first element A is made, having a silicon body 1 a with a main surface coated with a buffer layer 2 a made of germanium, or of a germanium-silicon alloy, and with a thin silicon layer 3 a, in that order.
  • a thin silicon oxide layer 2 b is formed on a silicon body 1 b, distinct from the previous silicon body, by a conventional thermal oxidation method.
  • the first element A and the second element B are bonded, as is shown in FIG. 1c , such that the thin silicon layer 3 a of the first element A is in contact with the silicon oxide layer 2 b of the second element B.
  • the first and second elements A and B are bonded one to the other, in a known manner, using the Van der Waals forces.
  • the selective removal of the buffer layer 2 a is then carried out, as shown in FIG. 1 d.
  • a well-known oxidizing chemistry may be used, such as a solution comprising 40 ml of 70% HNO 3 +20 ml of H 2 O 2 +5 ml of 0.5% HF or by anisotropic plasma etching.
  • the silicon substrate includes a buried silicon oxide layer 2 b.
  • the SOI substrate obtained does not require additional polishing as is the case in the techniques of the prior art, in particular the techniques known as “BESOI” and “SMART CUT”.
  • the silicon body 1 a is not lost and can be recycled to be used.
  • the silicon body 1 a may be used as a silicon body for the fabrication of the elements A or B.
  • FIGS. 2a to 2 e show the main steps of a variant of the method described above.
  • the method of this variant differs from the method described in relation to FIGS. 1a to 1 e in that a thin silicon oxide layer 4 a has been made to grow on the thin silicon layer 3 a of the first element A above.
  • the thin silicon oxide layer 4 a may be grown by thermal oxidation. This may produce a first element A comprising a silicon substrate 1 a, a main surface of which is coated with a buffer layer 2 a made of germanium, or of a silicon-germanium alloy, a thin silicon layer 3 a, and finally, with a thin silicon oxide layer 4 a, in that order.
  • the second element B shown in FIG. 2b , is identical to that of the previous method.
  • the first element A and the second element B are then bonded as above, such that the silicon oxide layer 4 a of the first element A is in contact with the silicon layer 2 b of the second element B, as shown in FIG. 2 c.
  • the first element A and the second element B can be bonded by means of Van der Waals forces
  • the assembly can be heated to a temperature of 1000° C. for a duration of about 30 minutes (as in the BESOI technology).
  • the method is finished as above and as shown in FIGS. 2d and 2e , by removing the buffer layer, so as to obtain an SOI substrate having a buried silicon layer produced by the bonding of the silicon oxide layers 3 a and 2 b of the first and second elements, and a reuseable silicon substrate 1 a.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
US11/208,132 1999-06-14 2000-06-08 Method for making a silicon substrate comprising a buried thin silicon oxide film Expired - Lifetime USRE41841E1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9907496A FR2794893B1 (fr) 1999-06-14 1999-06-14 Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie
FR9907496 1999-06-14
PCT/FR2000/001570 WO2000077846A1 (fr) 1999-06-14 2000-06-08 Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie

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US10/018,680 Reissue US6607968B1 (en) 1999-06-14 2000-06-08 Method for making a silicon substrate comprising a buried thin silicon oxide film

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USRE41841E1 true USRE41841E1 (en) 2010-10-19

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US11/208,132 Expired - Lifetime USRE41841E1 (en) 1999-06-14 2000-06-08 Method for making a silicon substrate comprising a buried thin silicon oxide film

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US (2) US6607968B1 (fr)
EP (1) EP1186024B1 (fr)
FR (1) FR2794893B1 (fr)
WO (1) WO2000077846A1 (fr)

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EP1588415B1 (fr) * 2003-01-07 2012-11-28 Soitec Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouche apres separation d'une couche mince de celle-ci
FR2849715B1 (fr) * 2003-01-07 2007-03-09 Soitec Silicon On Insulator Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince
FR2849714B1 (fr) * 2003-01-07 2007-03-09 Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince
JP4949014B2 (ja) * 2003-01-07 2012-06-06 ソワテク 薄層を除去した後の多層構造を備えるウェハのリサイクル
US7060592B2 (en) * 2004-09-15 2006-06-13 United Microelectronics Corp. Image sensor and fabricating method thereof
US7361574B1 (en) * 2006-11-17 2008-04-22 Sharp Laboratories Of America, Inc Single-crystal silicon-on-glass from film transfer
FR2929758B1 (fr) 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
CN101615590B (zh) * 2009-07-31 2011-07-20 上海新傲科技股份有限公司 采用选择腐蚀工艺制备绝缘体上硅材料的方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371862A2 (fr) 1988-11-29 1990-06-06 The University Of North Carolina At Chapel Hill Méthode pour fabriquer une structure de semi-conducteur non-silicium sur isolant
US5218213A (en) 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5476813A (en) 1993-11-15 1995-12-19 Kabushiki Kaisha Toshiba Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor
WO1996015550A1 (fr) 1994-11-10 1996-05-23 Lawrence Semiconductor Research Laboratory, Inc. Compositions silicium-germanium-carbone et processus associes
EP0779649A2 (fr) 1995-12-12 1997-06-18 Canon Kabushiki Kaisha Procédé et dispositif pour la fabrication d'un substrat SOI
US6100166A (en) 1996-12-18 2000-08-08 Canon Kabushiki Kaisha Process for producing semiconductor article
US6143628A (en) 1997-03-27 2000-11-07 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US6294478B1 (en) 1996-02-28 2001-09-25 Canon Kabushiki Kaisha Fabrication process for a semiconductor substrate

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371862A2 (fr) 1988-11-29 1990-06-06 The University Of North Carolina At Chapel Hill Méthode pour fabriquer une structure de semi-conducteur non-silicium sur isolant
US5218213A (en) 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5476813A (en) 1993-11-15 1995-12-19 Kabushiki Kaisha Toshiba Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor
WO1996015550A1 (fr) 1994-11-10 1996-05-23 Lawrence Semiconductor Research Laboratory, Inc. Compositions silicium-germanium-carbone et processus associes
US5906708A (en) 1994-11-10 1999-05-25 Lawrence Semiconductor Research Laboratory, Inc. Silicon-germanium-carbon compositions in selective etch processes
EP0779649A2 (fr) 1995-12-12 1997-06-18 Canon Kabushiki Kaisha Procédé et dispositif pour la fabrication d'un substrat SOI
US6294478B1 (en) 1996-02-28 2001-09-25 Canon Kabushiki Kaisha Fabrication process for a semiconductor substrate
US6100166A (en) 1996-12-18 2000-08-08 Canon Kabushiki Kaisha Process for producing semiconductor article
US6534382B1 (en) 1996-12-18 2003-03-18 Canon Kabushiki Kaisha Process for producing semiconductor article
US6143628A (en) 1997-03-27 2000-11-07 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
French Search Report, French Application No. 9907496; Prepared Feb. 29, 2000.

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Publication number Publication date
WO2000077846A1 (fr) 2000-12-21
EP1186024A1 (fr) 2002-03-13
EP1186024B1 (fr) 2006-11-15
US6607968B1 (en) 2003-08-19
FR2794893B1 (fr) 2001-09-14
FR2794893A1 (fr) 2000-12-15

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