USRE41722E1 - Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof - Google Patents

Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof Download PDF

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Publication number
USRE41722E1
USRE41722E1 US10105236 US10523602A USRE41722E US RE41722 E1 USRE41722 E1 US RE41722E1 US 10105236 US10105236 US 10105236 US 10523602 A US10523602 A US 10523602A US RE41722 E USRE41722 E US RE41722E
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Prior art keywords
substrate
electrode pads
main surface
pads
semiconductor pellet
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US10105236
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Atsushi Nakamura
Kunihiko Nishi
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Renesas Technology Corp
Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • BPERFORMING OPERATIONS; TRANSPORTING
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    • B29C45/14639Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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    • H01L2924/351Thermal stress

Abstract

A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.

Description

This is a continuation of reissue application Ser. No. 09/613,541, filed Jul. 7, 2000, the subject matter of which is incorporated by reference herein.

More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,777,391. These reissue applications are: ( 1 ) Ser. No. 09/613,541, filed Jul. 7, 2000; ( 2 ) the present application, Ser. No. 10/105,236, filed Mar. 26, 2002; ( 3 ) Ser. No. 11/182,039, filed Jul. 15, 2005; ( 4 ) Ser. No. 11/182,040, filed Jul. 15, 2005; ( 5 ) Ser. No. 11/256,620, filed on Oct. 24, 2005; ( 6 ) Ser. No. 11/256,621 filed on Oct. 24, 2005; ( 7 ) Ser. No. 11/285,729, filed on Nov. 23, 2005; and ( 8 ) Ser. No. 11/285,730, filed on Nov. 23, 2005.

The present reissue application also claims the benefit under 35 USC §120 of the filing date of Dec. 11, 1995 of Ser. No. 08/570,646, now U.S. Pat. No. 5,777,391, and benefit under 35 USC §119 of Japanese Application No. 6 - 316,444, filed on Dec. 20, 1994 and Japanese Application No. 7 - 126405, filed May 25, 1995, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method of manufacture thereof and more particularly to a technology effectively applied to a semiconductor device and a method of manufacture thereof, the device having a structure in which a semiconductor pellet is mounted on a pellet mounting area on the main surface of a base substrate and in which a first electrode pad on the back of the base substrate is electrically connected to an external terminal on the main surface of the semiconductor pellet.

A semiconductor device with a ball grid array (BGA) structure has been introduced as a semiconductor device having a high level of integration in the Nikkei Electronics. Feb. 28, 1994, pp. 111-117, published by Nikkei McGraw-Hill. The BGA structure of such as semiconductor device, as shown in FIG. 16 (cross section of an essential part), has a semiconductor pellet 2 mounted on a pellet mounting area of the main surface of the base substrate 1 and a plurality of bump electrodes 4 arranged in grid on the back of the base substrate 1 opposite the main surface.

The base substrate 1 may be made from a printed wiring board of two-layer wiring structure. Second electrode pads 1A are arranged in a peripheral area of the main surface of the base substrate 1 (around the pellet mounting area), while first electrode pads 1B are arranged on the back of the base substrate 1 opposite the main surface. The second electrode pads 1A are electrically connected to through-hole conductors 1C via conductors 1A1 arranged on the main surface of the base substrate 1. The first electrode pads 1B are electrically connected to the through-hole conductors 1C via conductors 1B1 arranged on the back of the base substrate 1.

The semiconductor pellet 2 may comprise mainly a semiconductor substrate 2B of single-crystal silicon. On the main surface of the semiconductor substrate 2B (device forming surface) is formed a logic circuit system, a memory circuit system or a combination of these. A plurality of bonding pads 2A are arranged on the main surface of the semiconductor substrate 2B. The bonding pads 2A are formed in the top of the interconnect layers formed on the main surface of the semiconductor substrate 2B.

The bonding pads 2A on the semiconductor pellet 2 are electrically connected to the second electrode pads 1A on the main surface of the base substrate 1 through bonding wires 6. In other words, the bonding pads 2A on the semiconductor pellet 2 are electrically connected to the first electrode pads 1B through the bonding wires 6, second electrode pads 1A, conductors 1A1, through-hole conductors 1C and conductors 1B1.

The semiconductor pellet 2 and the bonding wires 6 are sealed with a resin sealing body 7 formed on the main surface of the base substrate 1. The resin sealing body 7 is formed by transfer molding.

The bump electrodes 4 are electrically and mechanically connected to the surfaces of the first electrode pads 1B on the base substrate 1. The bump electrodes 4 may be formed from an alloy material, such as Pb-Sn.

The semiconductor device of such a BGA structure is mounted on a mounting board, with the bump electrodes 4 electrically and mechanically connected to electrode pads arranged on the mounting surface of the mounting board.

Another example of semiconductor device having a high circuit density is disclosed in U.S. Pat. Ser. No. 5148265, which shows a semiconductor device in which the base substrate is made from a filmlike flexible substrate. In this semiconductor device, the semiconductor pellet is mounted, with its main surface downward, on the pellet mounting area of the main surface of the base substrate made of a flexible substrate, and the bonding pads arranged on the main surface of the semiconductor pellet are electrically connected to the second electrode pads arranged on the back of the base substrate through the bonding wires. The second electrode pads on the base substrate are electrically connected to the first electrode pads on the back of the base substrate through conductors that are also arranged on the back. Bump electrodes are electrically and mechanically connected to the surfaces of the first electrode pads.

The semiconductor device of the above construction is mounted on the mounting surface of a mounting board, with its bump electrodes electrically and mechanically connected to the electrode pads arranged on the mounting surface of the mounting board.

SUMMARY OF THE INVENTION

In the semiconductor device with the BGA structure, as shown in FIG. 16, the second electrode pads 1A arranged on the main surface of the base substrate 1 are electrically connected through the through-hole conductors 1C to the first electrode pads 1B arranged on the back of the base substrate 1. The through-hole conductors 1C comprises a hole area formed within a through-hole in the base substrate 1 and a land area (fringe portion) formed on the main surface and back surface of the base substrate 1. The inner diameter of the through-hole may be around 0.3 mm and the outer diameter of the land area of the through-hole conductor 1C may be about 0.6 mm. The inner diameter of the through-hole and the outer diameter of the land area of the through-hole conductor 1C are set large compared to the widths of the conductors 1A1 electrically connecting the second electrode pads 1A and the through-hole conductors 1C and also compared to the widths of the conductors 1B1 electrically connecting the first electrode pads 1B and the through-hole conductors 1C.

The circuit systems framed on the typical semiconductor pellets 2 have tended to grow in their level of integration and the number of functions they perform. With enhanced integration and more diversified functions of the circuit system, the number of bonding pads 2A of the semiconductor pellet 2 and the number of second electrode pads 1A of the base substrate 1 increase. That is, the number of through-hole conductors 1C electrically connecting the second electrode pads 1A and the first electrode pads 1B increases as the integration and function of the circuit system are enhanced. Hence, there has been a problem that the external size of the base substrate 1 increase with the increasing number of the through-hole conductors 1C, which in turn increases the size of the semiconductor device as a whole.

There is also another problem which the inventors have considered. The intervals between the through-hole conductors formed by copper foil thick film printing, etching or electroplating techniques are greater than the intervals of the bonding pads of the semiconductor pellet formed by photolithography. For this reason, in a semiconductor device with the BGA structure, as the number of the through-hole conductors 1C increases, they are positioned outwardly away from the semiconductor pellet 2. This inevitably extends the length of the conductors 1A1 electrically connecting the second electrode pads 1A and the through-hole conductors 1C and the length of the conductors 1B1, electrically connecting the first electrode pads 1B and the through-hole conductors 1C. This, in turn, increases inductance and reduces the operating speed of the semiconductor device.

In the semiconductor device using a flexible substrate for the base substrate, the flexible substrate may for example be formed of a polyester film or polyimide film. This flexible substrate has a small Young's modulus and is soft (low hardness) compared with a rigid substrate impregnated with epoxy resin or polyimide resin, as represented by the FR4 substrate according to the NEMA Standard. Therefore, when the bonding pads arranged on the main surface of the semiconductor pellet are connected with the second electrode pads arranged on the back of the base substrate through bonding wires, the bonding force applied to the second electrode pads is absorbed by the base substrate, preventing the bonding force and ultrasonic vibrations from being transmitted to the second electrode pads effectively. This gives rise to an apprehension that the connection strength between the bonding wires and the second electrode pads may decrease, leading to connection failures of bonding wires and reduced electric reliability of the semiconductor device.

In semiconductor devices that use a flexible substrate for the base substrate, the flexible substrate has a large thermal expansion coefficient in the planar direction and a small Young's modulus (small rigidity), which means that it is easy to bend, compared with the rigid substrate. Therefore, when the semiconductor device is mounted on the mounting surface of the mounting board, the reflow heat used during the process of mounting causes deformations to the base substrate, such as warping and twisting, which in turn reduces the flatness of the back of the base substrate with respect to the mounting surface of the mounting board, thereby lowering the mounting precision of the semiconductor device.

An object of this invention is to provide a technology that allows a reduction in the size of the semiconductor device.

Another object of this invention is to provide a technology that allows an increase in the operating speed of the semiconductor device.

Still another object of this invention is to provide a technology that can enhance electric reliability of the semiconductor device.

A further object of this invention is to provide a technology that can enhance mounting precision of the semiconductor device.

A further object of this invention is to provide a manufacturing technology for the semiconductor device that can accomplish the above objectives.

These and other objects and novel features of this invention will become apparent from the following description of this specification and the accompanying drawings.

Representative aspects of this invention may be briefly summarized as follows.

A semiconductor device in accordance with invention comprises a semiconductor pellet mounted on the pellet mounting area of the main surface of the base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to the bonding pads on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to second electrode pads also arranged on the back side of the base subtrate. The semiconductor pellet is mounted, with its main surface downward, on the pellet mounting area of the main surface of the base substrate, and its bonding pads are electrically connected to the second electrode pads on the base substrate through bonding wires extending through slits formed in the base substrate.

A method of manufacturing a semiconductor device is also provided, in which a semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate and in which first electrode pads arranged on the back of the base substrate are electrically connected to the bonding pads on the main surface of the semiconductor pellet. In particular, the method includes a step of mounting the semiconductor pellet, with its main surface downward, on the pellet mounting area of the main surface of the base substrate made of a rigid substrate, and a step of connecting the bonding pads on the semiconductor pellet to the second electrode pads electrically connected to the first electrode pads of the base substrate and arranged on the back of the base substrate through bonding wires extending through slits formed in the base substrate.

According to the above construction of this invention, the bonding pads of the semiconductor pellet and the first electrode pads of the base substrate can be electrically connected through the bonding wires and the second electrode pads, so it is possible to eliminate the through holes used to electrically connect the second electrode pads and the first electrode pads in prior structures. This allows the external size of the base substrate to be reduced by an amount corresponding to an area occupied by the through holes (land area), thus reducing the size of the semiconductor device as a whole.

Further, because the first electrode pads can be put closer to the second electrode pads by an amount corresponding to an area occupied by the through holes, the conductors of the base substrate that electrically connect the second electrode pads and the first electrode pads can be reduced in length. As a result, inductance can be reduced and the operating speed of the semiconductor device increased.

Further, the rigid substrate has a higher Young's modulus than a flexible substrate; therefore, when the bonding pads arranged on the main surface of the semiconductor pellet and the second electrode pads arranged on the back of the base substrate are electrically connected by bonding wires, the bonding force applied to the second electrode pads can be prevented from being absorbed by the base substrate. This assures effective transmission of the bonding force and the ultrasonic vibrations to the second electrode pads. Thus, the connection strength between the bonding wires and the second electrode pads is increased, making it possible to prevent connection failure of the bonding wires and to enhance electric reliability of the semiconductor device.

Furthermore, the rigid substrate has a small inplane thermal expansion coefficient and a high Young's modulus compared with a flexible substrate, which means the rigid substrate is harder to bend. This prevents the base substrate from being deformed (warped or twisted) due to reflow heat produced during the process of mounting the semiconductor device on the mounting surface of the mounting board. This ensures a sufficient flatness of the back of the base substrate with respect to the mounting surface of the mounting board, thus enhancing the mounting precision of the semiconductor device.

According to the above-mentioned manufacturing method of this invention, the bonding pads of the semiconductor pellet and the first electrode pads of the base substrate are electrically connected through bonding wires and second electrode pads, so the through holes electrically connecting the second electrode pads and the first electrode pads can be eliminated, making it possible to use a base substrate reduced in external size by an amount corresponding to the occupied area of the through holes. This in turn allows the manufacture of reduced-size semiconductor devices.

Further, because the bonding pads of the semiconductor pellet and the first electrode pads of the base substrate are electrically connected through bonding wires and second electrode pads, the through holes electrically connecting the second electrode pads and the first electrode pads can be eliminated, making it possible to use a base substrate whose conductors electrically connecting the second electrode pads and the first electrode pads are reduced by a length corresponding to the occupied area of the through holes. This in turn allows the manufacture of semiconductor devices with faster operating speeds.

The base substrate uses a rigid substrate having a high Young's modulus compared with a flexible substrate; therefore, when the bonding pads arranged on the main surface of the semiconductor pellet and the second electrode pads arranged on the back of the base substrate are electrically connected by bonding wires, the bonding force applied to the second electrode pads can be prevented from being absorbed by the base substrate, ensuring effective transfer of the bonding force and ultrasonic vibrations to the second electrode pads. This enhances the connection strength between the bonding wires and the second electrode pads, allowing the manufacture of the semiconductor device with high electric reliability.

Furthermore, the base substrate used is formed of a rigid substrate having a small planar thermal expansion coefficient and a high Young's modulus compared with those of a flexible substrate, which means the rigid substrate is harder to bend. As a result, the rigid base substrate is free from deformations (warping or twisting) due to reflow heat during the process of mounting the semiconductor device on the mounting surface of the mounting board. As a result, a sufficient degree of flatness of the back of the base substrate with respect to the mounting surface of the mounting board can be secured, which in turn allows the manufacture of semiconductor devices with high mounting precision.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of the main surface side of the semiconductor device, as a first embodiment of this invention, that employs a BGA structure;

FIG. 2 is a cross section taken along the line A—A of FIG. 1;

FIG. 3 is an enlarged cross section of an essential part of FIG. 2;

FIG. 4 is an enlarged plan view showing the state of the back side of an essential part of the semiconductor device with the resin sealing body removed;

FIG. 5 is a cross section showing an essential part of a molding the for the resin sealing body of the semiconductor device;

FIG. 6 is a cross section showing the method of manufacturing the semiconductor device;

FIG. 7 is a cross section of an essential part of the semiconductor device showing the method of manufacture thereof;

FIG. 8 is a cross section of an essential part of the semiconductor device showing the method of manufacture thereof;

FIG. 9 is a cross section of an essential part of the semiconductor device showing the method of manufacture thereof; FIG. 10 is a cross section showing an essential part of the semiconductor device mounted on a mounting board;

FIG. 11 is a cross section showing a variation of the semiconductor device;

FIG. 12 is a cross section of the semiconductor device, as a second embodiment of this invention, that employs the BGA structure;

FIG. 13 is an enlarged plan view showing the state of the back side of an essential part of the semiconductor device with the resin sealing body removed;

FIG. 14 is a plan view showing the state of the back side of an essential part of the semiconductor device, as a third embodiment of this invention, that employs the BGA structure with the resin sealing body removed;

FIG. 15 is a plan view showing the state of the back side of an essential part of the semiconductor device, as a fourth embodiment of this invention, that employs the BGA structure and is removed of the resin sealing body removed; and

FIG. 16 is a cross section showing an essential part of the semiconductor device that employs the conventional BGA structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The construction of this invention is described in the following in conjunction with embodiments that apply this invention to a semiconductor device using the BGA structure.

In the drawings used for explaining the embodiments, components with identical functions are given like reference numerals and their explanations are not repeated.

Embodiment 1

The outline construction of a semiconductor device, as a first embodiment of this invention, that uses the BGA structure is shown in FIG. 1 (plan view of the main surface side), FIG. 2 (cross section taken along the line A—A of FIG. 1), FIG. 3 (enlarged cross section of an essential part of FIG. 2) and FIG. 4 (enlarged plan view showing the back side of an essential part of the semiconductor device with the resin sealing body removed).

As shown in FIGS. 1, 2, 3 and 4, the semiconductor device has a semiconductor pellet 2 mounted on a pellet mounting area of the main surface of a base substrate 1, with a plurality of bump electrodes 4 arranged in grid on the back of the base substrate 1 opposite the main surface.

The base substrate 1 may be formed of a printed circuit board. The printed circuit board may, for example, have a structure in which wiring is formed over the surface of a rigid substrate of glass fiber impregnated with epoxy resin, polyimide resin or maleimide resin. In other words, the base substrate 1 is formed of a rigid substrate. The rigid substrate has a high Young's modulus and is hard compared with a flexible substrate made of polyester film or polyimide film. The rigid substrate has a small thermal expansion coefficient in a planar direction, a high Young's modulus and is difficult to bend compared with the flexible substrate. For example, the rigid substrate made of a glass fiber impregnated with epoxy resin or polyimide resin has a Young's modulus of around 16-22 GPa and a thermal expansion coefficient of about 10-20×10−61/° C. Flexible substrates made of polyester film or polyimide film have a Young's modulus of about 2-5 GPa and a thermal expansion coefficient of about 20-25×10−61/° C.

On the back of the base substrate 1 are formed a plurality of second electrode pads 1A and first electrode pads 1B, which are electrically interconnected through conductors 1B1 on the back of the base substrate 1. The second electrode pads 1A, first electrode pads 1B and conductors 1B1 are formed of a Cu film, for example.

On the surfaces of the first electrode pads 1B are formed bump electrodes 4 that are electrically and mechanically connected to them. The bump electrodes 4 may be formed of, for instance, a Pb-Sn alloy.

The semiconductor pellet 2 is mounted, with its main surface (underside in FIG. 2 and 3) downward, on the pellet mounting area of the main surface of the base substrate 1. That is, the semiconductor pellet 2 is mounted facedown on the pellet mounting area of the main surface of the base substrate 1. Interposed between the main surface of the semiconductor pellet 2 and the pellet mounting area of the main surface of the base substrate 1 is an insulating layer 3, which may be formed of a polyimide-, epoxy- or silicon-base low-elasticity resin.

The semiconductor pellet 2 may be rectangular and may mainly be comprised of a semiconductor substrate 2B made of single-crystal silicon. On the main surface (device forming surface) of the semiconductor substrate 2B are formed a logic circuit system, a memory circuit system or a combination of these. Also on the main surface of the semiconductor substrate 2B, a plurality of bonding pads 2A are arranged along the sides of the rectangular surface. The bonding pads 2A are formed on the top of interconnect layers on the main surface of the semiconductor substrate 2B. That is, the bonding pads 2A are arranged in the periphery of the main surface of the semiconductor pellet 2 along each of the four sides.

The bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1 are electrically connected to each other through bonding wires 6 running in slits 5 formed in the base substrate 1. The bonding wires 6 may be of gold (AU), copper (Cu) or aluminum (Al), and may be coated with insulating resin. The bonding wires 6 may be connected by a bonding method that utilizes ultrasonic vibrations in combination with thermocompression.

The slits 5 in the base substrate 1 are formed in the directions of the rows of the bonding pads 2A that are arranged along each side of the main surface of the semiconductor pellet 2. That is, the base substrate 1 of this embodiment has four slits 5, each of which is located above the bonding pads 2A of the semiconductor pellet 2.

The second electrode pads 1A of the base substrate 1 are placed in both areas of the back of the base substrate 1 divided by the slits 5. The second electrode pads 1A located in one of the areas of the back of the base substrate 1 demarcated by the slits 5 (inside the semiconductor pellet 2) are supplied with a power supply such as an operation voltage (3.3 V for instance) and a reference voltage (0 V for instance). The second electrode pads 1A located in the other area of the back of the base substrate 1 demarcated by the slits 5 (outside the semiconductor pellet 2) receive a signal such as an input/output signal and a control signal.

The semiconductor pellet 2 are provided with 100 bonding pads 2A on each side at a pitch of about 100 μm. The number of bonding pads 2A is increased as the level of integration and the operating speed of the circuit system mounted on the semiconductor pellet 2 increase.

The first area of the back of the base substrate 1 demarcated by the slits 5 is provided with, for example, 50 second electrode pads 1A for each side of the semiconductor pellet 2; and the second area is provided with, for instance, 50 second electrode pads 1A for each side of the semiconductor pellet 2. Because the second electrode pads 1A cannot be made as small as the bonding pads 2A of the semiconductor pellet 2, the pitch of the second electrode pads 1A is set wider than that of the bonding pads 2A, for instance, at around 200 μm. That is, because the second electrode pads 1A of the base substrate 1 are arranged in two rows for each side of the semiconductor pellet 2, the length of the second electrode pads 1A corresponding to one side of the semiconductor pellet 2 can be made almost equal to that of the bonding pads 2A arranged along one side of the semiconductor pellet 2 even if the pitch of the second electrode pads 1A of the base substrate 1 is set to two times that of the bonding pads 2A of the semiconductor pellet 2. Furthermore, the second electrode pads 1A of the base substrate 1 can be located at positions racing the corresponding bonding pads 2A of the semiconductor pellet 2.

The peripheral area of the main surface of the base substrate 1 excluding the pellet mounting area is covered with a resin sealing body 7, which seals the bonding wires 6. That is, the resin sealing body 7 is formed on the main surface side and the back surface side of the base substrate 1. The resin sealing body 7 is made from epoxy resin 7A containing a phenol-base hardener, silicone rubber and filler for reducing stresses.

The back of the base substrate 1 facing the main surface of the semiconductor pellet 2 is exposed from the resin sealing body 7 that covers the peripheral area of the base substrate 1.

The resin sealing body 7 is formed by the transfer molding that uses a molding die 10 shown in FIG. 5 (cross section of an essential part). The molding the 19 has a cavity 11 defined by an upper die 10A and a lower die 10B, an inflow gate 13 connected to the cavity 11, and, though not shown, a pot and a runner. The pot communicates with the cavity 11 through the runner and the inflow gate 13.

The cavity 11 comprises a recess 11A formed in the upper die 10A and a recess 11B formed in the lower die 10B. The resin 7A is supplied into the recess 11A from the pot through the runner and the inflow gate 13. The base substrate 1 is placed in the recess 11B.

The recess 11B is formed with recesses 12, which are located at positions facing the slits 5 of the base substrate 1 and which extend in the same directions as the slits 5. Placed in the recesses 12 are a part of bonding wires 6 electrically connecting the bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1, and also the second electrode pads 1A of the base substrate 1. The resin 7A is supplied from the recess 11A through the slits 5 of the base substrate 1 into the recess 11A.

Though not shown in FIG. 12, the recesses 12 are provided with a gas vent to prevent voids due to bubbles.

Next, the method of manufacturing the above-mentioned semiconductor device is described by referring to FIGS. 6 through FIG. 9.

First, a base substrate 1 made of a rigid substrate is prepared. The base substrate 1 includes slits 5 as well as second electrode pads 1A, first electrode pads 1B and conductors 1B1 on its back.

Next, as shown in FIG. 6 (cross section), the semiconductor pellet 2 is mounted on the pellet mounting area of the main surface of the base substrate 1. The semiconductor pellet 2 is fixed to the pellet mounting area of the main surface of the base substrate 1 through an insulating layer 3.

Next, the base substrate 1 is mounted on a bonding stage (heat block) 14 with the semiconductor pellet 2 at the bottom. The bonding stage 14 has a recess 14A that accommodates the semiconductor pellet 2. The base substrate 1 and the semiconductor pellet 2 are heated to about 200° C. on the bonding stage 14.

Next, as shown in FIG. 7 (cross section of an essential part), the bonding pads 2A arranged on the main surface of the semiconductor pellet 2 and the second electrode pads 1A arranged on the back of the base substrate 1 are electrically connected by the bonding wires 6. The bonding wires 6 running in the slits 5 are connected to the bonding pads 2A of the semiconductor pellet 2 and to the second electrode pads 1A of the base substrate 1. The connection of the bonding wires 6 is accomplished by ultrasonic thermocompression bonding. In this process, the base substrate 1 is made from a rigid substrate with a high Young's modulus compared with the flexible substrate used in conventional structure, so that the bonding farce applied to the second electrode pads 1A is prevented from being absorbed by the rigid base substrate 1, thus allowing the bonding force and the ultrasonic vibrations to be transferred effectively to the second electrode pads 1A. Further, because the base substrate 1 is made of a rigid substrate that has a smaller thermal expansion coefficient in the planar direction than that of a flexible substrate and a higher Young's modulus—which means it is harder to bend—it is possible to reduce positional deviations of the second electrode pads 1A and of the bonding pads 2A of the semiconductor pellet 2 due to thermal expansion of the base substrate 1.

Then, as shown in FIG. 8 (cross section of an essential part), the base substrate 1 and the semiconductor pellet 2 are put in the cavity 11 defined by the upper die 10A and the lower die 10B of the molding die 10, with the base substrate 1 fit in the recess 11B of the cavity 11. A part of the bonding wires 6 and the second electrode pads 1A of the base substrate 1 are placed in the recesses 12 formed in the recess 11B. The molding die 10 is preheated to around 170°-180° C. to heighten the fluidity of the resin 7A supplied into the cavity 11. Because the base substrate 1 is made from a rigid substrate with a smaller thermal expansion coefficient in the planar direction than the flexible substrate and with a higher Young's modulus, which means the base substrate 1 is harder to bend, the base substrate 1 can be prevented from being deformed (warped or twisted) due to the heating of the molding die 10 to about 170°-180° C. during this process.

Next, resin tablets are charged into the pot of the molding die 10, nothing that they are preheated by a heater to lower the viscosity before being charged. The resin tablets in the pot are heated by the molding die 10, further lowering the viscosity.

The resin is then pressurized by a plunger of the transfer molding device, forcing the resin 7A from the pot through the runner and the gate 13 into the recess 11A and the recesses 12 of the cavity 11 to cover the peripheral area of the main surface of the base substrate 1, leaving the back of the semiconductor pellet 2 exposed. In this way, a resin sealing body 7 that seals the bonding wires 6 is formed. The resin 7A is forced into the recesses 12 through the slits 5 of the base substrate 1 from the recess 11A. In this process, the resin 7A supplied from the recess 11A to the recesses 12 through the slits 5 flows in the axial direction of the bonding wires 6, i.e., in the vertical direction, from one end side of the bonding wires 6. This vertical flow of resin prevents the bonding wires 6 from being deformed whereas the horizontal flow along the surface of the base substrate 1 may deform them.

Then, the base substrate 1 is taken out of the molding die 10, and bump electrodes 4 are electrically and mechanically connected to the surfaces of the first electrode pads 1B on the back of the base substrate 1. Thus, a nearly completed semiconductor device shown in FIG. 1, 2, 3 and 4 is obtained.

After this, the semiconductor device is shipped as a product. The semiconductor device shipped as a product is mounted on a mounting surface of a mounting board 15, with the bump electrodes 4 of the semiconductor device electrically and mechanically connected to electrode pads 15A arranged on the mounting surface of the mounting board 15, as shown in FIG. 10 (cross section). The connection between the bump electrodes 4 of the semiconductor device and the electrode pads 15A of the mounting board 15, although it depends on the material of the bump electrodes 4, may be accomplished in an atmosphere at a reflow temperature of, for instance, around 210°-230° C. In this mounting process, because the base substrate 1 is made from a rigid substrate which has a smaller thermal expansion coefficient in the planar direction and a higher Young's modulus—which means it is more difficult to bend—than a flexible substrate, the base substrate 1 can be prevented from being deformed due to reflow heat.

This embodiment offers the following advantages.

A semiconductor device comprises a semiconductor pellet 2 mounted on a pellet mounting area of the main surface of a base substrate 1, in which first electrode pads 1B arranged on the back of the base substrate 1 are electrically connected to bonding pads 2A arranged on the main surface of the semiconductor pellet 2. The base substrate 1 is formed of a rigid substrate, and its first electrode pads 1B are electrically connected to the second electrode pads 1A arranged on its reverse side. The semiconductor pellet 2 is mounted on the pellet mounting area of the main surface of the base substrate 1, with its main surface downward, and its bonding pads 2A are electrically connected with the second electrode pads 1A of the base substrate 1 through bonding wires 6 passing through slits 5 formed in the base substrate 1. Because with this construction the bonding pads 2A of the semiconductor pellet 2 and the first electrode pads 1B of the base substrate 1 can be electrically connected through the bonding wires 6 and second electrode pads 1A, it is possible to eliminate the through holes used to electrically connect the second electrode pads 1A and the first electrode pads 1B. This in turn allows the base substrate 1 to be reduced in size by an amount corresponding to the occupied area of the through holes (land area), which contributes to size reduction of the semiconductor device.

Because the first electrode pads 1B can be put closer to the second electrode pads 1A by a distance corresponding to the occupied area of the through holes, it is possible to shorten the length of the conductors 1B, of the base substrate 1 that electrically connect the second electrode pads 1A and the first electrode pads 1B. This reduces the inductance, increasing the operation speed of the semiconductor device.

Further, because the rigid substrate has a higher Young's modulus and is harder than the flexible substrate of the conventional structure, the bonding force applied to the second electrode pads 1A is not absorbed by the base substrate 1 when electrically connecting the bonding pads 2A on the main surface of the semiconductor pellet 2 and the second electrode pads 1A on the back of the base substrate 1 by the bonding wires 6. As a result, the bonding force and the ultrasonic vibrations are effectively transferred to the second electrode pads 1A. This in turn increases the connection strength between the bonding wires 6 and the second electrode pads 1A, preventing possible connection failures of the bonding wires 6, enhancing the electric reliability of the semiconductor device.

Moreover, because the rigid substrate has a smaller thermal expansion coefficient in the planar direction and a higher Young's modulus than a flexible substrate, which means it is more resistant to bending, the base substrate 1 is free from deformations (warping and twisting) due to reflow heat when the semiconductor device is mounted on the mounting surface of the mounting board 15. As a result, a sufficient degree of flatness of the back of the base substrate 1 with respect to the mounting surface of the mounting board 15 can be secured, enhancing the mounting precision of the semiconductor device.

Further, because the rigid substrate has a smaller thermal expansion coefficient in the planar direction and a higher Young's modulus than the flexible substrate, which means it is more resistant to bending, the warning of the base substrate 1 can be limited to less than 100 μm even when the external size of the base substrate 1 increases with the increasing number of the first electrode pads 1B.

With the warping of the base substrate 1 limited to within 100 μm, it is possible to eliminate a reinforcement substrate intended to prevent warping of the base substrate 1. This reduces the manufacture cost of the semiconductor device compared with that of a semiconductor device having a reinforcement substrate.

Furthermore, because the base substrate 1 can be formed of a printed wiring board of a single layer structure having the second electrode pads 1A, first electrode pads 1B and conductors 1B1 arranged only on the back of a rigid substrate, the parts cost of the base substrate 1 can be reduced compared with that of a base substrate formed of a two-layer printed wiring board which has circuits formed on both the main and back surfaces of the rigid substrate. This means that the overall cost of semiconductor device manufacture can be lowered.

Another feature of this embodiment is that the slits 5 formed in the base substrate 1 extend in the directions of rows of bonding pads 2A arranged on the main surface of the semiconductor pellet 2 and are located at positions over the bonding pads 2A. With this construction, the slits 5 are arranged within the area occupied by the semiconductor pellet 2, so that the base substrate 1 requires no increase in size corresponding to the slits 5.

A further feature of this embodiment is that the second electrode pads 1A are arranged in two opposite areas of the back of the base substrate 1 divided by the slits 5. This construction allows an increase in the number of power supply paths for electrically connecting the bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1. This in turn makes it possible to reduce power supply noise generated at time of simultaneous switching of signals, thereby preventing malfunctions of the semiconductor device.

Further, even when the pitch of the second electrode pads 1A of the base substrate 1 is set larger than that of the bonding pads 2A of the semiconductor pellet 2, the length of the row of the second electrode pads 1A for each side of the semiconductor pellet 2 can be made almost equal to the length of the row of the bonding pads 2A for each side of the semiconductor pellet 2. This prevents an increase in the length of the bonding wires 6, which is dependent on the length of the row of the second electrode pads 1A. As a result, it is possible to prevent the bonding wires 6 from being deformed by the flow of resin when the bonding wire 6 are sealed by the resin sealing body 7 according to the transfer molding.

Further, because the second electrode pads 1A can be located at positions on the base substrate 1 facing the bonding pads 2A of the semiconductor pellet 2, the lengths of the bonding wires 6 can be made uniform, which in turn makes uniform the inductances of the signal paths between the bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1.

A further feature of this embodiment is the structure in which the back of the semiconductor pellet 2 opposing its main surface is exposed from the resin sealing body 7 that covers the peripheral area around the main surface of the base substrate 1. This structure allows the heat generated by die operation of the circuit system mounted on the semiconductor pellet 2 to be released from the back of the semiconductor pellet 2, thus enhancing the heat dissipation efficiency of the semiconductor device.

Further, because the mechanical strength of the base substrate 1 can be reinforced by the mechanical strength of the resin sealing body 7, deformations of the base substrate 1 (warping and twisting) due to reflow heat during mounting can be prevented.

A further feature of this embodiment is that the bonding wires 6 are sealed with the resin sealing body 7. This structure prevents the bonding wires 6 from being deformed due to external impacts and contacts, thus enhancing the electric reliability of the semiconductor device.

A still further feature of this embodiment is that the resin sealing body 7 is formed both on the main surface side and the back surface side of the base substrate 1. This structure prevents the resin sealing body 7 from becoming separated from the base substrate 1 due to the thermal stresses generated during a temperature cycle test or when the bump electrodes 4 are connected. This in turn enhances the reliability of the semiconductor device.

A method of manufacturing a semiconductor device, in which a semiconductor pellet 2 is mounted on a pellet mounting area of the main surface of a base substrate 1 and in which first electrode pads 1B arranged on the back of the base substrate 1 are electrically connected to bonding pads 2A arranged on the main surface of the semiconductor pellet 2, comprises a step of mounting the semiconductor pellet 2, with its main surface downward, on the pellet mounting area of the main surface of the base substrate 1 formed of a rigid substrate, and a step of electrically connecting the bonding pads 2A to the second electrode pads 1A, which are electrically connected to the first electrode pads 1B of the base substrate 1 and arranged on the back of the base substrate 1, through bonding wires 6 passing through slits 5 formed in the base substrate 1. The bonding pads 2A of the semiconductor pellet 2 and the first electrode pads 1B of the base substrate 1 therefore are electrically connected through the bonding wires 6 and the second electrode pads 1A, so that through holes 1C used for electrically connecting the second electrode pads 1A and the first electrode pads 1B can be eliminated, reducing the external size of the base substrate 1 by an amount corresponding to the occupied area of the through holes. As a result, the overall external size of the semiconductor device can be reduced.

Further, because the bonding pads 2A of the semiconductor pellet 2 and the first electrode pads 1B of the base substrate 1 are electrically connected through the bonding wires 6 and the second electrode pads 1A, there is no need for through holes 1C to electrically connect the second electrode pads 1A with the first electrode pads 1B. This makes it possible to use a base substrate 1 in which the conductors 1B1 electrically connecting the second electrode pads 1A and the first electrode pads 1B are shorter by a length corresponding to the occupied area of the through holes. As a result, it is possible to fabricate a semiconductor device with fast operating speeds.

Because the base substrate 1 used is formed of a rigid substrate having a higher Young's modulus—which means it is harder—than a flexible substrate, the bonding force applied to the bonding pads 2A when electrically connecting the bonding pads 2A arranged on the main surface of the semiconductor pellet 2 and the second electrode pads 1A arranged on the back of the base substrate 1 through the bonding wires 6 is not absorbed by the base substrate 1, effectively transmitting the bonding force and ultrasonic vibrations to the second electrode pads 1A. As a result, the connection strength between the bonding wires 6 and the second electrode pads 1A can be increased, which in turn allows the manufacture of a semiconductor device with high electric reliability.

Because the base substrate 1 is formed of a rigid substrate having a smaller thermal expansion coefficient in the planar direction and a higher Young's modulus—which means it is more resistant to bending—than a flexible substrate, the base substrate 1 is prevented from being deformed (warped or twisted) due to reflow heat during the process of mounting the semiconductor device on the mounting surface of the mounting board 15. This allows the back surface of the base substrate 1 to have a sufficient degree of flatness with respect to the mounting surface of the mounting board 15, thus enhancing the mounting precision of the semiconductor device.

Following the process of electrically connecting with the bonding wires 6, the method of manufacture includes a process of transfer molding of a resin sealing body 7 that covers the peripheral area of the main surface of the base substrate 1 and seals the bonding wires 6. Because the base substrate 1 uses a rigid substrate which has a smaller thermal expansion coefficient in the planar direction and a higher Young's modulus and is more resistant to bending than a flexible substrate, this method prevents the base substrate 1 from being deformed (warped or twisted) due to heating of the molding die 10.

Because the resin 7A supplied from the recess 11A into the recesses 12 through the slits 5 flows from one end side of the bonding wires 6 in their axial direction, i.e., in the vertical direction, the bonding wires 6 are not deformed by the flow of the resin 7A, whereas they can be deformed when the resin flows along the surface of the base substrate 1, i.e., in the lateral direction.

As shown in FIG. 11 (cross section), the resin sealing body 7 may be formed on the back surface of the base substrate 1 excluding the surfaces of the second electrode pads 1A and first electrode pads 1B. In this case, the base substrate 1 is held and clamped from both sides by the resin sealing body 7 and therefore prevented from being warped.

The base substrate 1 may, though not shown, be formed in a multilayer structure in which a plurality of rigid substrates are stacked together. This structure can reduce the manufacture cost as compared with a base substrate made up of a plurality of flexible substrates stacked together.

Embodiment 2

The outline configuration of a semiconductor device as the second embodiment of this invention that employs a BGA structure is shown in FIG. 12 (cross section) and FIG. 13 (enlarged plan view of an essential part of the back side showing the state of the back side removed of the resin sealing body).

As shown in FIG. 12 and 13, the semiconductor device has the semiconductor pellet 2 mounted facedown on the pellet mounting area of the main surface of the base substrate 1 with an insulating layer 3 in between. A plurality of bump electrodes 4 are arranged in grid on the back of the base substrate 1.

Arranged in the central area of the main surface of the semiconductor pellet 2 along the longer sides thereof is a row of bonding pads 2A, which are electrically connected to the second electrode pads 1A arranged on the back of the base substrate 1 through the bonding wires 6 passing through the slits 5 formed in the base substrate 1. The second electrode pads 1A are electrically connected to the corresponding first electrode pads 1B arranged on the back of the base substrate 1 through conductors 1B1. Bump electrodes 4 are electrically and mechanically connected to the surfaces of the first electrode pads 1B. That is, the bonding pads 2A of the semiconductor pellet 2 are electrically connected to the first electrode pads 1B through the bonding wires 6, second electrode pads 1A and conductors 1B1.

The slits 5 of the base substrate 1 are formed in the central area of the main surface of the semiconductor pellet 2 along the direction of the row of the bonding pads 2A arranged along the longer side of the semiconductor pellet 2. The slits 5 are tapered so that its opening on the back side of the base substrate 1 is greater than the opening on the main surface side.

As described above, this embodiment offers similar effects and advantages to those of the first embodiment. With the slits 5 tapered, it is possible to prevent contact between the base substrate 1 and a bonding tool when one end of the bonding wires 6 is bonded to the bonding pads 2A of the semiconductor pellet 2. This in turn raises the yield of semiconductor device assembly in the bonding process.

Embodiment 3

The outline configuration of a semiconductor device as the third embodiment of this invention that employs a BGA structure is shown in FIG. 14 (plan view of an essential part of the back side showing the state of the back side removed of the resin sealing body).

As shown in FIG. 14, the semiconductor device has a semiconductor pellet 2 mounted facedown on a pellet mounting area of the main surface of the base substrate 1, with an insulating layer 3 in between. Bump electrodes 4 are arranged in grid on the back of the base substrate 1.

At the outer periphery of the main surface of the semiconductor pellet 2, a plurality of bonding pads 2A are arranged along the sides of the pellet. At the central portion of the main surface of the semiconductor pellet 2, a plurality of bonding pads 2A are arranged along the longer or shorter side of the pellet. The bonding pads 2A are electrically connected to the second electrode pads 1A arranged on the back of the base substrate 1 by bonding wires 6 passing through slits 5 formed in the base substrate 1. The second electrode pads 1A are electrically connected to first electrode pads 1B arranged on the back of the base substrate 1 through conductors 1B1. Bump electrodes 4 are electrically and mechanically connected to the surfaces of the individual first electrode pads 1B. That is, the bonding pads 2A are electrically connected to the first electrode pads 1B through the bonding wires 6, second electrode pads 1A and conductors 1B1.

The slits 5 are arranged at each sides of the semiconductor pellet 2 and also at the central portion of the pellet. That is, the base substrate 1 of this embodiment has five slits 5, each of which is located above the bonding pads 2A of the semiconductor pellet 2.

As explained above, this embodiment offers the similar effects and advantages to those of the first embodiment. Because the slits 5 are arranged at the sides and the central portion of the semiconductor pellet 2, it is possible to increase the number of bonding pads 2A arranged on the main surface of the semiconductor pellet 2 and the number of second electrode pads 1A arranged on the back of the base substrate 1. This allows an increase in the number of power supply paths for electrically connecting the bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1. This is turn allows a further reduction in power supply noise generated when output signals are switched simultaneously. Furthermore, this construction makes it possible to increase the number of signal paths electrically connecting the bonding pads 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1 and therefore reduce the external size of the semiconductor pellet 2 dictated by the number of bonding pads 2A.

Although this embodiment has been shown to have only one slit 5 formed at the central portion of the semiconductor pellet 2, two or more slits 5 may be arranged parallelly or crosswise to each other at the central part of the semiconductor pellet 2. By increasing the number of slits 5 in this way, it is possible to further increase the number of the second electrode pads 1A of the base substrate 1 and the number of the bonding pads 2A of the semiconductor pellet 2.

Embodiment 4

The outline configuration of a semiconductor device as the fourth embodiment of this invention that employs a BGA structure is shown in FIG. 15 (plan view of an essential part of the back side showing the state of the back side removed of the resin sealing body).

As shown in FIG. 15, the semiconductor device has a semiconductor pellet 2 mounted facedown on a pellet mounting area of the main surface of the base substrate 1, with an insulating layer 3 in between. Bump electrodes 4 are arranged in grid on the back of the base substrate 1. The base substrate 1 is formed of a printed circuit board of, for example, 3-layer wiring structure.

At the outer periphery of the main surface of the semiconductor pellet 2, a plurality of bonding pads 2A are arranged along the sides of the pellet. The bonding pads 2A are electrically connected to the second electrode pads 1A arranged on the back of the base substrate 1 through bonding wires 6 passing through slits 5 formed in the base substrate 1.

Of the second electrode pads 1A, electrode pads 1A2 are formed integral with electrode plates 8A. The electrode plates 8A are electrically connected to other electrode plates 8A via through holes (not shown) and internal wiring (not shown) in the base substrate 1. The electrode plates 8A is connected to be at a reference voltage (0 V for example). Of the second electrode pads 1A, electrode pads 1A3 are formed integral with an electrode plate 8B. This electrode plate 8A is connected to be at an operating voltage (3.3 V for instance).

With this embodiment, because the through holes 1C that electrically connect the second electrode pads 1A on the main surface of the base substrate 1 and the first electrode pads 1B on the back are eliminated, the electrode plates 8A and the electrode plate 8B can be arranged on the back of the base substrate 1. This allows the bump electrodes 4 to be freely located and shortens the distance between the bonding pads 2A of the semiconductor pellet 2 and the pump electrodes 4. As a result, the inductance can be reduced, thereby increasing the operating speeds of the semiconductor device.

The invention has been described in detail in connection with representative embodiments of the invention. It is noted, however, that the invention is not limited to these embodiments but that many modifications may be made without departing from the spirit of the invention.

Representative advantages of this invention may be summarized as follows.

It is possible to reduce the size of a semiconductor device in which the semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate and in which the first electrode pads arranged on the back of the base substrate are electrically connected to the bonding pads arranged on the main surface of the semiconductor pellet.

It is possible to increase the operating speed of the semiconductor device.

It is also possible to enhance the electric reliability of the semiconductor device.

Further, it is possible to increase the mounting precision of the semiconductor device.

Claims (30)

1. A semiconductor device comprising:
(a) a rigid substrate having a first main surface and a second main surface opposite to the first main surface;
(b) a semiconductor pellet mounted on the first main surface of the rigid substrate, the semiconductor pellet having a plurality of semiconductor circuit elements and a plurality of bonding pads;
(c) a plurality of electrode pads formed on the second main surface of the rigid substrate; and
(d) a plurality of bonding wires for electrically connecting the bonding pads of the semiconductor pellet with the electrode pads;
wherein the semiconductor pellet is mounted facedown on the rigid substrate, the rigid substrate has slits that extend from the first main surface to the second main surface and expose the bonding pads of the semiconductor pellet, the bonding wires extend through the slits in the rigid substrate to connect the bonding pads and the electrode pads, and bump electrodes are formed on said electrode pads.
2. A semiconductor device according to claim 1, wherein the bonding pads are arranged at the periphery of the semiconductor pellet and the slits are formed along the directions of rows of the bonding pads.
3. A semiconductor device according to claim 2, wherein the electrode pads are located on both sides of the slits.
4. A semiconductor device according to claim 3, wherein the electrode pads located on one side of the slits and under the semiconductor pellet are power supply pads, and the electrode pads located on the other side of the slits and outside the semiconductor pellet are signal pads.
5. A semiconductor device according to claim 1, further comprising a first resin sealing body covering the semiconductor pellet.
6. A semiconductor device according to claim 5, further comprising a second resin sealing body formed in the slits and covering the bonding wires.
7. A semiconductor device according to claim 1, wherein said rigid substrate is formed by glass fibers impregnated with epoxy resin.
8. A method of manufacturing a semiconductor device in which a semiconductor pellet is mounted on a pellet mounting area of the main surface of a rigid base substrate and in which first electrode pads arranged on the back of the rigid base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet, said method comprising:
a step of mounting the semiconductor pellet, with its main surface downward, on the pellet mounting area of the main surface of the rigid base substrate
a step of electrically connecting the bonding pads of the semiconductor pellet and second electrode pads electrically connected to the first electrode pads of the rigid base substrate and arranged on the back of the rigid base substrate through bonding wires passing through slits formed on the rigid base substrate; and
a step of forming bump electrodes on the first electrode pads.
9. A method of manufacturing a semiconductor device according to claim 9, further comprising a step of forming by transfer molding a resin sealing body that covers the periphery of the main surface of the rigid base substrate and seals the bonding wires, after the step of electrically connecting the bonding wires.
10. A semiconductor device according to claim 10, wherein said rigid substrate is formed by glass fibers impregnated with polyimide resin.
11. A semiconductor device comprising:
(a) a rigid substrate having a first main surface and a second main surface opposite to the first main surface;
(b) a semiconductor pellet mounted on the first main surface of the rigid substrate, the semiconductor pellet having a plurality of semiconductor circuit elements and a plurality of bonding pads;
(c) a plurality of electrode pads formed on the second main surface of the rigid substrate; and
(d) a plurality of bonding wires for electrically connecting the bonding pads of the semiconductor pellet with the electrode pads;
wherein the semiconductor pellet is mounted facedown on the rigid substrate, the rigid substrate has slits that extend from the first main surface to the second main surface and expose the bonding pads of the semiconductor pellet, and the bonding wires extend through the slits in the rigid substrate to connect the bonding pads and the electrode pads;
wherein the bonding pads are arranged at the periphery of the semiconductor pellet and the slits are formed along the directions of rows of the bonding pads.
12. A semiconductor device according to claim 11, wherein the electrode pads are located on both sides of the slits.
13. A semiconductor device according to claim 12, wherein the electrode pads located on one side of the slits and under the semiconductor pellet are power supply pads, and the electrode pads located on the other side of the slits and outside the semiconductor pellet are signal pads.
14. A semiconductor device comprising:
a substrate of a quadrilateral shape having a first pair of opposed edges and a second pair of opposed edges, said substrate having a first main surface, a second main surface opposite to said first main surface and a first slit and a second slit each extending from said first main surface to said second main surface, said first slit extending along one of said first pair of opposed edges, said second slit extending along the other of said first pair of opposed edges, said substrate having first electrode pads on said second main surface in a first area between said first and second slits, second electrode pads on said second main surface in a second area between said first slit and said one of the first pair of opposed edges, and third electrode pads on said second main surface in a third area between said second slit and the other of the first pair of opposed edges;
a semiconductor pellet having a main surface with semiconductor elements and bonding pads, said semiconductor pellet being mounted on said first main surface of substrate such that said bonding pads are arranged to be in line with said first and second slits;
bonding wires extending through said first and second slits in said substrate and electrically connecting said bonding pads and said first to third electrode pads, respectively;
a resin member sealing said semiconductor pellet and said bonding wires; and
bump electrodes arranged on said second main surface of said substrate in said first to third areas in a direction of said first pair of opposed edges and being electrically connected with said first to third electrode pads,
wherein said bump electrodes in said second and third areas are arranged to form plural rows in a direction of at least one of said second pair of opposed edges, respectively.
15. A semiconductor device according to claim 14, wherein said semiconductor pellet has a quadrilateral shape and has a third pair of opposed edges and a fourth pair of opposed edges, wherein said bonding pads are arranged in a peripheral portion of said main surface and extend along said third pair of opposed edges.
16. A semiconductor device according to claim 15, wherein said semiconductor pellet is mounted on said first main surface opposite to said first area, wherein said substrate has a larger size than that of said semiconductor pellet, and wherein said bump electrodes in said second and third areas are located outside said third pair of opposed edges.
17. A semiconductor device according to claim 14, wherein the number of said bump electrodes in said second and third areas is larger than the number of said bump electrodes in said first area.
18. A semiconductor device according to claim 14, wherein said semiconductor pellet has a rear surface opposite to said main surface, and wherein said rear surface of said semiconductor pellet is exposed from said resin member.
19. A semiconductor device according to claim 14, wherein the number of said bump electrodes in said second area is larger than the number of said bump electrodes in said first area.
20. A semiconductor device according to claim 14, wherein said semiconductor pellet has a rear surface opposite to said main surface, and wherein said rear surface of said semiconductor pellet is exposed from said resin member.
21. A semiconductor device according to claim 14, wherein said first electrode pads extend along said first and second slits, respectively, said second electrode pads extend along said first slit, and said third electrode pads extend along said second slit, wherein said first to third electrode pads are arranged at a first pitch, respectively, wherein said bonding pads in said first and second slits are arranged at a second pitch which is smaller than said first pitch, respectively, wherein said bonding wires in said first slit alternately connect said bonding pads in said first slit with said first and second electrode pads, and wherein said bonding wires in said second slit alternately connect said bonding pads in said second slit with said first and third electrode pads.
22. A semiconductor device comprising:
a substrate of a quadrilateral shape having first to fourth edges, said substrate having a first main surface, a second main surface opposite to said first main surface and first to fourth slits extending from said first main surface to said second main surface, said first to fourth slits respectively extending along said first to fourth edges and defining a first area of said substrate surrounded by said first to fourth slits and a second area of said substrate extending outside said first to fourth slits, said substrate having first electrode pads on said second main surface in said first area and second electrode pads on said second main surface in said second area;
a semiconductor pellet having a main surface with semiconductor elements and bonding pads, said semiconductor pellet being mounted on said first main surface of substrate such that said bonding pads are arranged in line with said first to fourth slits;
bonding wires extending through said first to fourth slits in said substrate and electrically connecting said bonding pads and said first and second electrode pads, respectively;
a resin member sealing said semiconductor pellet and said bonding wires; and
bump electrodes arranged on said second main surface of said substrate in said first and second areas and being electrically connected with said first and second electrode pads,
wherein said bump electrodes in said second area are arranged to form a plurality of rows such that said plurality of rows are formed relative to one another to surround said first area of substrate.
23. A semiconductor device according to claim 22, wherein said semiconductor pellet has a quadrilateral shape and has first to fourth edges, wherein said bonding pads are arranged in a peripheral portion of said main surface and extend along said first to fourth edges of said semiconductor pellet.
24. A semiconductor device according to claim 23, wherein said semiconductor pellet is mounted on said first main surface opposite to said first area, wherein said substrate has a larger size than that of said semiconductor pellet, and wherein said bump electrodes in said second area are located outside said first to fourth edges of said semiconductor pellet.
25. A semiconductor device according to claim 22, wherein said first and second electrode pads extending along said first to fourth slits, respectively, and are arranged at a first pitch, wherein said bonding pads extend along said first and second electrode pads and are arranged at a second pitch which is smaller than said first pitch, and wherein said bonding wires alternately connect said bonding pads with said first and second electrode pads.
26. A semiconductor device comprising:
( 1 ) a semiconductor pellet of a quadrilateral shape having bonding pads formed in a main surface thereof, said semiconductor pellet having a first pair of opposed edges extending in a first direction and a second pair of opposed edges extending in a second direction which intersects said first direction;
( 2 ) a substrate having a first surface, a second surface opposite to said first surface, electrode pads formed on said second surface and a slit passing through said substrate from said first surface to said second surface and extending in said first direction, said semiconductor pellet being disposed on said first surface of said substrate such that said main surface of said semiconductor pellet is faced to said first surface of said substrate and said bonding pads are arranged in said slit in a plane view, said electrode pads including first electrode pads arranged at one side of said slit and second electrode pads arranged at the other side of said slit in said second direction;
( 3 ) bonding wires, each extending from one of said bonding pads of said semiconductor pellet to pass through said slit from said first surface of the substrate to the second surface of the substrate to electrically connect said electrode pads of said substrate with said bonding pads of said semiconductor pellet via said slit, said bonding wires including first bonding wires connected to said first electrode pads and second bonding wires connected to said second electrode pads;
( 4 ) bump electrodes being disposed on said second surface of said substrate and being electrically connected to said electrode pads of said substrate, said bump electrodes including first bump electrodes electrically connected to said first electrode pads and arranged at said one side of said slit and second bump electrodes electrically connected to said second electrode pads and arranged at the other side of said slit, said first bump electrodes being arranged in both said first and second directions to form, in said plane view, a first matrix, on said one side of said slit, formed of said first bump electrode arranged in said first and second directions, and, said second bump electrodes being arranged in both said first and second directions to form, in said plane view, a second matrix, on said other side of the slit, formed of said second bump electrodes arranged in said first and second directions, and
( 5 ) a resin sealing body sealing said bonding wires and said main surface of said semiconductor pellet exposed from said slit,
wherein said substrate has a periphery which protrudes outwardly from said first and second pairs of opposed edges of said semiconductor pellet, wherein said first surface of said periphery of said substrate and said semiconductor pellet are sealed with a resin sealing body, and wherein a rear surface of said semiconductor pellet opposite to said main surface is exposed from said resin sealing body.
27. The semiconductor device according to claim 26, wherein said bump electrodes are arranged on said second surface of said substrate that overlaps with said semiconductor pellet in said plane view and on said second surface of said substrate at said periphery.
28. A semiconductor device comprising:
( 1 ) a semiconductor pellet of a quadrilateral shape having bonding pads formed in a main surface thereof, said semiconductor pellet having a first pair of opposed edges extending in a first direction and a second pair of opposed edges extending in a second direction which intersects said first direction;
( 2 ) a substrate having a first surface, a second surface opposite to said first surface, electrode pads formed on said second surface and a slit passing through said substrate from said first surface to said second surface and extending in said first direction, said semiconductor pellet being disposed on said first surface of said substrate such that said main surface of said semiconductor pellet is faced to said first surface of said substrate and said bonding pads are arranged in said slit in a plane view, said electrode pads including first electrode pads arranged at one side of said slit and second electrode pads arranged at the other side of said slit in said second direction;
( 3 ) bonding wires, each extending from one of said bonding pads of said semiconductor pellet to pass through said slit from said first surface of the substrate to the second surface of the substrate to electrically connect said electrode pads of said substrate with said bonding pads of said semiconductor pellet via said slit, said bonding wires including first bonding wires connected to said first electrode pads and second bonding wires connected to said second electrode pads;
( 4 ) bump electrodes being disposed on said second surface of said substrate and being electrically connected to said electrode pads of said substrate, said bump electrodes including first bump electrodes electrically connected to said first electrode pads and arranged at said one side of said slit and second bump electrodes electrically connected to said second electrode pads and arranged at the other side of said slit, said first bump electrodes being arranged in both said first and second directions to form, in said plane view, a first matrix, on said one side of said slit, formed of said first bump electrode arranged in said first and second directions, and, said second bump electrodes being arranged in both said first and second directions to form, in said plane view, a second matrix, on said other side of the slit, formed of said second bump electrodes arranged in said first and second directions, and
( 5 ) a resin sealing body sealing said bonding wires and said main surface of said semiconductor pellet exposed from said slit,
wherein a height of said bump electrodes is greater than a thickness of said resin sealing body from said second surface of said substrate in a thickness direction of said semiconductor pellet.
29. The semiconductor device according to claim 28, wherein a peak of loop height of said bonding wires is less than said height of bump electrodes in said thickness direction of said semiconductor pellet.
30. The semiconductor device according to claim 29,
wherein said bump electrodes are formed to provide electrical connection to a printer circuit board.
US10105236 1994-12-20 2002-03-26 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof Expired - Lifetime USRE41722E1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP6-316444 1994-12-20
JP31644494 1994-12-20
JP7-126405 1995-05-25
JP12640595A JP3487524B2 (en) 1994-12-20 1995-05-25 Semiconductor device and manufacturing method thereof
US08570646 US5777391A (en) 1994-12-20 1995-12-11 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US09613541 USRE41721E1 (en) 1994-12-20 2000-07-07 Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes
US10105236 USRE41722E1 (en) 1994-12-20 2002-03-26 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof

Applications Claiming Priority (5)

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US10105236 USRE41722E1 (en) 1994-12-20 2002-03-26 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US11182040 USRE41478E1 (en) 1994-12-20 2005-07-15 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US11182039 USRE42972E1 (en) 1994-12-20 2005-07-15 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US11285730 USRE43444E1 (en) 1994-12-20 2005-11-23 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes
US12805447 USRE44148E1 (en) 1994-12-20 2010-07-30 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof

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US08570646 Reissue US5777391A (en) 1994-12-20 1995-12-11 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US09613541 Continuation USRE41721E1 (en) 1994-12-20 2000-07-07 Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes

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US11182039 Continuation USRE42972E1 (en) 1994-12-20 2005-07-15 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof

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US08570646 Expired - Lifetime US5777391A (en) 1994-12-20 1995-12-11 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US09613541 Expired - Lifetime USRE41721E1 (en) 1994-12-20 2000-07-07 Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes
US10105236 Expired - Lifetime USRE41722E1 (en) 1994-12-20 2002-03-26 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US11182040 Expired - Lifetime USRE41478E1 (en) 1994-12-20 2005-07-15 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US11182039 Expired - Lifetime USRE42972E1 (en) 1994-12-20 2005-07-15 Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE43444E1 (en) * 1994-12-20 2012-06-05 Renesas Electronics Corporation Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes
US20120153435A1 (en) * 2010-12-17 2012-06-21 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US8278764B1 (en) * 2011-10-03 2012-10-02 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8345441B1 (en) 2011-10-03 2013-01-01 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
USRE44148E1 (en) * 1994-12-20 2013-04-16 Renesas Electronics Corporation Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US8436477B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8670261B2 (en) 2011-10-03 2014-03-11 Invensas Corporation Stub minimization using duplicate sets of signal terminals
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8917532B2 (en) 2011-10-03 2014-12-23 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8981547B2 (en) 2011-10-03 2015-03-17 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US10032752B2 (en) 2016-11-10 2018-07-24 Invensas Corporation Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4528977B2 (en) * 1994-12-20 2010-08-25 ルネサスエレクトロニクス株式会社 A method of manufacturing a semiconductor device
US5891795A (en) * 1996-03-18 1999-04-06 Motorola, Inc. High density interconnect substrate
JP2891665B2 (en) 1996-03-22 1999-05-17 株式会社日立製作所 The semiconductor integrated circuit device and manufacturing method thereof
US20040061220A1 (en) * 1996-03-22 2004-04-01 Chuichi Miyazaki Semiconductor device and manufacturing method thereof
US6667560B2 (en) * 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6027791A (en) * 1996-09-30 2000-02-22 Kyocera Corporation Structure for mounting a wiring board
JPH10289932A (en) * 1997-02-17 1998-10-27 Seiko Epson Corp Carrier film and integrated circuit device using thereof
JP3328157B2 (en) * 1997-03-06 2002-09-24 シャープ株式会社 The liquid crystal display device
US5953623A (en) * 1997-04-10 1999-09-14 International Business Machines Corporation Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection
CA2273223C (en) * 1997-09-29 2003-11-11 Raytheon Company Chip-size package using a polyimide pcb interposer
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6221689B1 (en) * 1997-10-24 2001-04-24 Apack Technologies Inc. Method for improving the reliability of underfill process for a chip
US6768646B1 (en) * 1998-01-23 2004-07-27 Texas Instruments Incorporated High density internal ball grid array integrated circuit package
US6333565B1 (en) * 1998-03-23 2001-12-25 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JPH11284007A (en) * 1998-03-31 1999-10-15 Toshiba Corp Semiconductor device and manufacture thereof
US6404067B1 (en) * 1998-06-01 2002-06-11 Intel Corporation Plastic ball grid array package with improved moisture resistance
JP3825181B2 (en) * 1998-08-20 2006-09-20 沖電気工業株式会社 Method of manufacturing a semiconductor device
US6194250B1 (en) * 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
FR2788882A1 (en) * 1999-01-27 2000-07-28 Schlumberger Systems & Service Integrated circuit module for smart card
US6109369A (en) * 1999-01-29 2000-08-29 Delphi Technologies, Inc. Chip scale package
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
JP2000311921A (en) * 1999-04-27 2000-11-07 Sony Corp Semiconductor device and manufacture thereof
US6486538B1 (en) * 1999-05-27 2002-11-26 Infineon Technologies Ag Chip carrier having ventilation channels
US6628136B2 (en) * 1999-09-02 2003-09-30 Micron Technology, Inc. Method and apparatus for testing a semiconductor package
JP2001094045A (en) * 1999-09-22 2001-04-06 Seiko Epson Corp Semiconductor device
JP2003516560A (en) * 1999-12-10 2003-05-13 テレフオンアクチーボラゲツト エル エム エリクソン(パブル) Interposer device
US6414396B1 (en) * 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
US6531763B1 (en) * 2000-08-15 2003-03-11 Micron Technology, Inc. Interposers having encapsulant fill control features
US7273769B1 (en) 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
US7443041B2 (en) * 2001-01-15 2008-10-28 United Test & Assembly Center Limited Packaging of a microchip device
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6528408B2 (en) * 2001-05-21 2003-03-04 Micron Technology, Inc. Method for bumped die and wire bonded board-on-chip package
JP2003007917A (en) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd Method manufacturing circuit device
US6756251B2 (en) * 2001-08-21 2004-06-29 Micron Technology, Inc. Method of manufacturing microelectronic devices, including methods of underfilling microelectronic components through an underfill aperture
US7129584B2 (en) 2002-01-09 2006-10-31 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US8441113B2 (en) 2002-01-09 2013-05-14 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US7161237B2 (en) * 2002-03-04 2007-01-09 Micron Technology, Inc. Flip chip packaging using recessed interposer terminals
US7145225B2 (en) * 2002-03-04 2006-12-05 Micron Technology, Inc. Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US7915718B2 (en) * 2002-03-04 2011-03-29 Micron Technology, Inc. Apparatus for flip-chip packaging providing testing capability
US7348215B2 (en) * 2002-03-04 2008-03-25 Micron Technology, Inc. Methods for assembly and packaging of flip chip configured dice with interposer
US7112520B2 (en) * 2002-03-04 2006-09-26 Micron Technology, Inc. Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6975035B2 (en) * 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
US6946729B2 (en) * 2002-04-19 2005-09-20 Advanced Semiconductor Engineering, Inc. Wafer level package structure with a heat slug
US6857865B2 (en) * 2002-06-20 2005-02-22 Ultratera Corporation Mold structure for package fabrication
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US6911132B2 (en) * 2002-09-24 2005-06-28 Duke University Apparatus for manipulating droplets by electrowetting-based techniques
US8349276B2 (en) * 2002-09-24 2013-01-08 Duke University Apparatuses and methods for manipulating droplets on a printed circuit board
US7329545B2 (en) 2002-09-24 2008-02-12 Duke University Methods for sampling a liquid flow
DE10339609A1 (en) * 2003-08-28 2005-03-24 Forschungszentrum Karlsruhe Gmbh Oligonucleotide method and system for the detection of antibiotic resistance-mediating genes in microorganisms by means of the real-time PCR
FR2861895B1 (en) * 2003-11-03 2006-02-24 Commissariat Energie Atomique Method and chip terminal device
WO2005053100A3 (en) * 2003-11-24 2005-08-11 Safety Quicklight Ltd Swivellable electric socket-plug combination
DE10356885B4 (en) * 2003-12-03 2005-11-03 Schott Ag A method for housings of components and a housed element
JP4503611B2 (en) * 2004-09-17 2010-07-14 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US20060145362A1 (en) * 2005-01-06 2006-07-06 Chin-Huang Chang Semiconductor package and fabrication method of the same
KR100615606B1 (en) * 2005-03-15 2006-08-17 삼성전자주식회사 Memory module and signal line arrangement method of the same
US20060270109A1 (en) * 2005-05-31 2006-11-30 Stephan Blaszczak Manufacturing method for an electronic component assembly and corresponding electronic component assembly
US7863642B2 (en) * 2005-08-24 2011-01-04 Koninklijke Philips Electronics N.V. Light emitting diodes and lasers diodes with color converters
KR100713931B1 (en) * 2006-03-29 2007-04-25 주식회사 하이닉스반도체 Semiconductor package having high-speed and high-performance
US8446734B2 (en) * 2006-03-30 2013-05-21 Kyocera Corporation Circuit board and mounting structure
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
JP4942020B2 (en) 2006-05-12 2012-05-30 ルネサスエレクトロニクス株式会社 Semiconductor device
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
JP2008277325A (en) * 2007-04-25 2008-11-13 Canon Inc Semiconductor device, and manufacturing method of semiconductor device
WO2009021233A3 (en) * 2007-08-09 2009-04-23 Advanced Liquid Logic Inc Pcb droplet actuator fabrication
JP5199622B2 (en) * 2007-08-27 2013-05-15 パナソニック株式会社 Fire detector
JP2010272680A (en) * 2009-05-21 2010-12-02 Elpida Memory Inc Semiconductor device
JP2012033613A (en) * 2010-07-29 2012-02-16 Elpida Memory Inc Semiconductor device and manufacturing method of semiconductor device
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8338963B2 (en) * 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
JP6144285B2 (en) * 2012-03-01 2017-06-07 コーニンクレッカ フィリップス エヌ ヴェKoninklijke Philips N.V. Electronic circuit device and manufacturing method thereof
US8906749B2 (en) * 2012-03-28 2014-12-09 Infineon Technologies Ag Method for fabricating a semiconductor device
KR20140007992A (en) * 2012-07-09 2014-01-21 삼성전자주식회사 Semiconductor package and method of forming the same

Citations (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433419B1 (en)
US4688074A (en) * 1982-04-06 1987-08-18 Citizen Watch Co., Ltd. Connecting structure for a display device
JPS62272546A (en) * 1986-05-20 1987-11-26 Hitachi Cable Ltd Film carrier for semiconductor device
JPS63261736A (en) * 1987-04-20 1988-10-28 Matsushita Electric Ind Co Ltd Printed wiring board
JPS6481330A (en) 1987-09-24 1989-03-27 Nec Corp Film carrier semiconductor device
JPH01229257A (en) * 1988-03-09 1989-09-12 Fuji Photo Film Co Ltd Peeling device
JPH0291345A (en) 1988-09-27 1990-03-30 Washi Chuetsu Board Kk Restoring treatment method and device for asphalt roofing
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
WO1992005582A1 (en) 1990-09-24 1992-04-02 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5107328A (en) 1991-02-13 1992-04-21 Micron Technology, Inc. Packaging means for a semiconductor die having particular shelf structure
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
JPH0547829A (en) 1991-08-15 1993-02-26 Fujitsu Ltd Semiconductor device
US5258330A (en) 1990-09-24 1993-11-02 Tessera, Inc. Semiconductor chip assemblies with fan-in leads
FR2694139A1 (en) * 1992-07-21 1994-01-28 Aerospatiale Interconnection substrate for electronic components e.g. leadless chip carrier mounted integrated circuits - has double layer composite material core with printed circuit formed on each substrate exterior surface, with cores connected by electrically isolating fibres and has metallised through holes insulated from cores
US5293068A (en) * 1990-02-01 1994-03-08 Hitachi, Ltd. Semiconductor device
JPH06268101A (en) 1993-03-17 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate
JPH06314719A (en) 1993-04-30 1994-11-08 Fujitsu Ltd Semiconductor device
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5438478A (en) * 1992-10-20 1995-08-01 Ibiden Co., Ltd. Electronic component carriers and method of producing the same as well as electronic devices
US5442231A (en) 1991-10-01 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5519251A (en) 1992-10-20 1996-05-21 Fujitsu Limited Semiconductor device and method of producing the same
US5650593A (en) * 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
US5661086A (en) * 1995-03-28 1997-08-26 Mitsui High-Tec, Inc. Process for manufacturing a plurality of strip lead frame semiconductor devices
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5677566A (en) 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5684330A (en) 1995-08-22 1997-11-04 Samsung Electronics Co., Ltd. Chip-sized package having metal circuit substrate
US5729051A (en) * 1994-09-22 1998-03-17 Nec Corporation Tape automated bonding type semiconductor device
US5753974A (en) * 1994-09-12 1998-05-19 Nec Corporation Electronic device assembly
US5811879A (en) * 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US5843806A (en) * 1997-11-24 1998-12-01 Compeq Manufacturing Company Limited Methods for packaging tab-BGA integrated circuits
US5852326A (en) 1990-09-24 1998-12-22 Tessera, Inc. Face-up semiconductor chip assembly
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US6423622B1 (en) * 1999-12-29 2002-07-23 Advanced Semiconductor Engineering, Inc. Lead-bond type chip package and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583375A (en) * 1990-06-11 1996-12-10 Hitachi, Ltd. Semiconductor device with lead structure within the planar area of the device
JPH04291948A (en) * 1991-03-20 1992-10-16 Fujitsu Ltd Semiconductor device and its manufacture; radiating fin
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
JPH06291216A (en) * 1993-04-05 1994-10-18 E I Du Pont De Nemours & Co Substrate and ceramic package
JP3487524B2 (en) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US6861290B1 (en) * 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
JPH10229257A (en) * 1997-02-13 1998-08-25 Ibiden Co Ltd Glass resin board

Patent Citations (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433419B1 (en)
US4688074A (en) * 1982-04-06 1987-08-18 Citizen Watch Co., Ltd. Connecting structure for a display device
JPS62272546A (en) * 1986-05-20 1987-11-26 Hitachi Cable Ltd Film carrier for semiconductor device
JPS63261736A (en) * 1987-04-20 1988-10-28 Matsushita Electric Ind Co Ltd Printed wiring board
JPS6481330A (en) 1987-09-24 1989-03-27 Nec Corp Film carrier semiconductor device
JPH01229257A (en) * 1988-03-09 1989-09-12 Fuji Photo Film Co Ltd Peeling device
JPH0291345A (en) 1988-09-27 1990-03-30 Washi Chuetsu Board Kk Restoring treatment method and device for asphalt roofing
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5293068A (en) * 1990-02-01 1994-03-08 Hitachi, Ltd. Semiconductor device
US5258330A (en) 1990-09-24 1993-11-02 Tessera, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US6392306B1 (en) 1990-09-24 2002-05-21 Tessera, Inc. Semiconductor chip assembly with anisotropic conductive adhesive connections
US6433419B2 (en) 1990-09-24 2002-08-13 Tessera, Inc. Face-up semiconductor chip assemblies
US6372527B1 (en) 1990-09-24 2002-04-16 Tessera, Inc. Methods of making semiconductor chip assemblies
WO1992005582A1 (en) 1990-09-24 1992-04-02 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
JPH06504408A (en) 1990-09-24 1994-05-19
US5346861A (en) 1990-09-24 1994-09-13 Tessera, Inc. Semiconductor chip assemblies and methods of making same
US5347159A (en) 1990-09-24 1994-09-13 Tessera, Inc. Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate
US6133627A (en) 1990-09-24 2000-10-17 Tessera, Inc. Semiconductor chip package with center contacts
US5950304A (en) 1990-09-24 1999-09-14 Tessera, Inc. Methods of making semiconductor chip assemblies
US5852326A (en) 1990-09-24 1998-12-22 Tessera, Inc. Face-up semiconductor chip assembly
US5848467A (en) 1990-09-24 1998-12-15 Tessera, Inc. Methods of making semiconductor chip assemblies
US5685885A (en) 1990-09-24 1997-11-11 Tessera, Inc. Wafer-scale techniques for fabrication of semiconductor chip assemblies
US5682061A (en) 1990-09-24 1997-10-28 Tessera, Inc. Component for connecting a semiconductor chip to a substrate
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US6465893B1 (en) 1990-09-24 2002-10-15 Tessera, Inc. Stacked chip assembly
US5107328A (en) 1991-02-13 1992-04-21 Micron Technology, Inc. Packaging means for a semiconductor die having particular shelf structure
JPH0547829A (en) 1991-08-15 1993-02-26 Fujitsu Ltd Semiconductor device
US5442231A (en) 1991-10-01 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5502289A (en) * 1992-05-22 1996-03-26 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
FR2694139A1 (en) * 1992-07-21 1994-01-28 Aerospatiale Interconnection substrate for electronic components e.g. leadless chip carrier mounted integrated circuits - has double layer composite material core with printed circuit formed on each substrate exterior surface, with cores connected by electrically isolating fibres and has metallised through holes insulated from cores
US5519251A (en) 1992-10-20 1996-05-21 Fujitsu Limited Semiconductor device and method of producing the same
US5438478A (en) * 1992-10-20 1995-08-01 Ibiden Co., Ltd. Electronic component carriers and method of producing the same as well as electronic devices
JPH06268101A (en) 1993-03-17 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate
US5608265A (en) 1993-03-17 1997-03-04 Hitachi, Ltd. Encapsulated semiconductor device package having holes for electrically conductive material
JPH06314719A (en) 1993-04-30 1994-11-08 Fujitsu Ltd Semiconductor device
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards
US5650593A (en) * 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
US5753974A (en) * 1994-09-12 1998-05-19 Nec Corporation Electronic device assembly
US5729051A (en) * 1994-09-22 1998-03-17 Nec Corporation Tape automated bonding type semiconductor device
US5661086A (en) * 1995-03-28 1997-08-26 Mitsui High-Tec, Inc. Process for manufacturing a plurality of strip lead frame semiconductor devices
US5677566A (en) 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5684330A (en) 1995-08-22 1997-11-04 Samsung Electronics Co., Ltd. Chip-sized package having metal circuit substrate
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US5811879A (en) * 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US5843806A (en) * 1997-11-24 1998-12-01 Compeq Manufacturing Company Limited Methods for packaging tab-BGA integrated circuits
US6423622B1 (en) * 1999-12-29 2002-07-23 Advanced Semiconductor Engineering, Inc. Lead-bond type chip package and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Nikkei electronics Feb. 28, 1994 (No. 602), pp. 111-117. (with translation).

Cited By (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE43444E1 (en) * 1994-12-20 2012-06-05 Renesas Electronics Corporation Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes
USRE44148E1 (en) * 1994-12-20 2013-04-16 Renesas Electronics Corporation Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US8885356B2 (en) 2010-12-17 2014-11-11 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US8466564B2 (en) * 2010-12-17 2013-06-18 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US20120153435A1 (en) * 2010-12-17 2012-06-21 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8759982B2 (en) 2011-07-12 2014-06-24 Tessera, Inc. Deskewed multi-die packages
US9287216B2 (en) 2011-07-12 2016-03-15 Invensas Corporation Memory module in a package
US9508629B2 (en) 2011-07-12 2016-11-29 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US9373565B2 (en) 2011-10-03 2016-06-21 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
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US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
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US8653646B2 (en) 2011-10-03 2014-02-18 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
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US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
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US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
US9679876B2 (en) 2011-10-03 2017-06-13 Invensas Corporation Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other
US9530458B2 (en) 2011-10-03 2016-12-27 Invensas Corporation Stub minimization using duplicate sets of signal terminals
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
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US8981547B2 (en) 2011-10-03 2015-03-17 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US9515053B2 (en) 2011-10-03 2016-12-06 Invensas Corporation Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis
US8345441B1 (en) 2011-10-03 2013-01-01 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US9214455B2 (en) 2011-10-03 2015-12-15 Invensas Corporation Stub minimization with terminal grids offset from center of package
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USRE43444E1 (en) 2012-06-05 grant
US5777391A (en) 1998-07-07 grant
JPH08227908A (en) 1996-09-03 application
USRE41721E1 (en) 2010-09-21 grant
USRE42972E1 (en) 2011-11-29 grant
KR100365586B1 (en) 2003-03-15 grant
USRE41478E1 (en) 2010-08-10 grant
JP3487524B2 (en) 2004-01-19 grant

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