JPH0547829A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0547829A JPH0547829A JP3205315A JP20531591A JPH0547829A JP H0547829 A JPH0547829 A JP H0547829A JP 3205315 A JP3205315 A JP 3205315A JP 20531591 A JP20531591 A JP 20531591A JP H0547829 A JPH0547829 A JP H0547829A
- Authority
- JP
- Japan
- Prior art keywords
- input
- semiconductor chip
- semiconductor
- leads
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/732—Location after the connecting process
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、よ
り詳しくは、リードと半導体チップ上のバンプとをワイ
ヤーにより接続する構造の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure in which leads are connected to bumps on a semiconductor chip by wires.
【０００２】[0002]
【従来の技術】半導体集積回路はますます高集積化さ
れ、チップの大型化が進んでいる。これにともない、配
線長が増加し、アクセスの高速化が困難になっている。2. Description of the Related Art Semiconductor integrated circuits are becoming more highly integrated and chips are becoming larger. Along with this, the wiring length increases, making it difficult to speed up access.
【０００３】これは、集積回路の外部入出力パッドが回
路の周辺に位置し、パッドから回路までの距離が長いこ
と、信号の流れが良くないことに起因している。この対
策として、図６に示すように、半導体チップ６１の中央
部に入出力パッド６２を配置する構造のＬＯＣ（Lead O
n Chip）が提案され、高速化、高集積化を図っている。
図において、セラミック製のダイス６３の上には半導体
集積回路６４を形成した半導体チップ６１が取付けら
れ、また、ダイス６３の周縁に沿って取付けられる複数
のリード６５は、半導体チップ６１上面の中央に形成さ
れた入出力パッド６２にボンディングワイヤー６６を介
して接続されている。This is because the external input / output pads of the integrated circuit are located around the circuit, the distance from the pad to the circuit is long, and the signal flow is not good. As a countermeasure against this, as shown in FIG. 6, an LOC (Lead O of the structure where the input / output pad 62 is arranged in the central portion of the semiconductor chip 61).
n Chip) has been proposed for higher speed and higher integration.
In the figure, a semiconductor chip 61 on which a semiconductor integrated circuit 64 is formed is attached on a ceramic die 63, and a plurality of leads 65 attached along the peripheral edge of the die 63 are arranged at the center of the upper surface of the semiconductor chip 61. It is connected to the formed input / output pad 62 via a bonding wire 66.
【０００４】一方、プリント基板上における半導体装置
の実装密度を高くするために、図７に示すようなＺＩＰ
(Zig-Zag In-line package）と呼ばれるパッケージが利
用されている。このＺＩＰは、半導体チップ７１の一面
に形成された入出力パッド７２に接続されるリード７３
を一列に並べてこれらをジグザグに曲げる構造となって
いる。なお、符号７４は、半導体チップ７１を封止する
樹脂パッケージを示している。On the other hand, in order to increase the packaging density of semiconductor devices on a printed circuit board, a ZIP as shown in FIG.
A package called (Zig-Zag In-line package) is used. This ZIP has leads 73 connected to input / output pads 72 formed on one surface of the semiconductor chip 71.
Are arranged in a line and are bent in a zigzag. Reference numeral 74 indicates a resin package that seals the semiconductor chip 71.
【０００５】[0005]
【発明が解決しようとする課題】しかし、前者のＬＯＣ
構造の装置によれば、入出力パッド６２に接続されるボ
ンディングワイヤー６６が半導体集積回路６４上に配線
されているために、回路の誤動作等の初期不良を発見す
る表面からの試験の際にボンディングワイヤー６６が邪
魔になるといった不都合がある。しかも、リード６５を
入出力パッド６２に近づけることができないために、ボ
ンディングワイヤー６６が長くなって抵抗が増加すると
いった問題もある。[Problems to be Solved by the Invention] However, the former LOC
According to the device having the structure, since the bonding wire 66 connected to the input / output pad 62 is wired on the semiconductor integrated circuit 64, the bonding wire 66 is bonded at the time of a test from the surface for finding an initial defect such as malfunction of the circuit. There is an inconvenience that the wire 66 becomes an obstacle. Moreover, since the lead 65 cannot be brought close to the input / output pad 62, there is a problem that the bonding wire 66 becomes long and the resistance increases.
【０００６】また、後者のＺＩＰを用いた装置において
は、リード７３やボンディングワイヤー７５の間隔が厳
しくなり、高集積化に支障をきたすばかりでなく、その
幅の狭小化によって抵抗やインダクタンスが増加すると
いった問題がある。Further, in the latter device using the ZIP, the distance between the leads 73 and the bonding wires 75 becomes strict, which not only hinders high integration, but also the resistance and the inductance increase due to the narrowing of the width. There is such a problem.
【０００７】本発明はこのような問題に鑑みてなされた
ものであって、入出力パッドからの外部接続の自由度を
高めてＬＯＣ構造における回路評価試験に影響を与え
ず、同時に、ＺＩＰにおけるリードやボンディングワイ
ヤーの間隔を緩和するとともに、入出力パッドからリー
ドに到る経路の抵抗を低減できる半導体装置を提供する
ことを目的とする。The present invention has been made in view of the above problems, and increases the degree of freedom of external connection from the input / output pad to not affect the circuit evaluation test in the LOC structure, and at the same time, leads in the ZIP. It is an object of the present invention to provide a semiconductor device that can reduce the resistance of a path from an input / output pad to a lead, while reducing the distance between bonding wires and bonding wires.
【０００８】[0008]
【課題を解決するための手段】上記した課題は、図１〜
３に例示するように、半導体集積回路２、12を一面側に
形成した半導体チップ１、11と、前記半導体集積回路
２、12に繋がり、かつ前記半導体チップ１、11を厚み方
向に貫通して両面に表出される入出力パッド３，13と、
前記入出力パッド３，13の表出面の一方又は他方にワイ
ヤー７，17を介して接続される複数のリード６，16とを
有することを特徴とする半導体装置により達成する。[Means for Solving the Problems]
As illustrated in 3, the semiconductor chips 1 and 11 having the semiconductor integrated circuits 2 and 12 formed on one surface side are connected to the semiconductor integrated circuits 2 and 12 and penetrate the semiconductor chips 1 and 11 in the thickness direction. I / O pads 3 and 13 exposed on both sides,
This is achieved by a semiconductor device having a plurality of leads 6 and 16 connected to one or the other of the exposed surfaces of the input / output pads 3 and 13 via wires 7 and 17.
【０００９】または、図１に例示するように、前記入出
力パッド３が前記半導体チップ１の中央領域に形成さ
れ、かつ、前記半導体集積回路２と反対側の面に表出し
た前記入出力パッド３に前記リード６が接続されている
ことを特徴とする前記第１の半導体装置によって達成す
る。Alternatively, as illustrated in FIG. 1, the input / output pad 3 is formed in the central region of the semiconductor chip 1 and is exposed on the surface opposite to the semiconductor integrated circuit 2. This is achieved by the first semiconductor device characterized in that the lead 6 is connected to 3.
【００１０】または、図２、３に例示するように、前記
入出力パッド13が前記半導体チップ11の周縁近傍に形成
され、前記リード17が前記入出力パッド13の側方におい
て厚さ方向に相対向して２列に配置され、しかも、複数
の前記入出力パッド13は、一面側と他面側から交互に前
記ワイヤー17が接続されてそれぞれ一面側と他面側の前
記リード16に接続されていることを特徴とする前記第１
の半導体装置により達成する。Alternatively, as illustrated in FIGS. 2 and 3, the input / output pad 13 is formed in the vicinity of the peripheral edge of the semiconductor chip 11, and the leads 17 are arranged laterally of the input / output pad 13 in the thickness direction. The input / output pads 13 are arranged in two rows facing each other, and the wires 17 are alternately connected from one surface side and the other surface side to the lead wires 16 on the one surface side and the other surface side, respectively. Said first characterized in that
It is achieved by the semiconductor device of.
【００１１】[0011]
【作 用】本発明によれば、半導体集積回路２，12に接
続される入出力パッド３, 13を、半導体チップ１, 11に
貫通させてその両面に表出するようにしている。[Operation] According to the present invention, the input / output pads 3 and 13 connected to the semiconductor integrated circuits 2 and 12 are penetrated through the semiconductor chips 1 and 11 so as to be exposed on both surfaces thereof.
【００１２】このため、半導体集積回路２，12に対する
信号を半導体チップ１, 11の両面から出し入れすること
ができ、配線の自由度が高くなる。また、第２の発明に
よれば、そのような入出力パッド３を半導体チップ１の
中央領域に設けているが、リード６との接続は、半導体
集積回路２と反対側の面で行っている。Therefore, signals to / from the semiconductor integrated circuits 2 and 12 can be taken in and out from both sides of the semiconductor chips 1 and 11, and the degree of freedom of wiring is increased. Further, according to the second invention, such an input / output pad 3 is provided in the central region of the semiconductor chip 1, but the connection with the lead 6 is made on the surface opposite to the semiconductor integrated circuit 2. .
【００１３】したがって、半導体集積回路２に電子を照
射して行われるような試験の際に、ワイヤー７が邪魔に
なることはなく、しかも、リード６を入出力パッド３に
近づけてワイヤー７の長さを短くして抵抗やインダクタ
ンスを小さくできる。Therefore, the wire 7 does not interfere with a test which is performed by irradiating the semiconductor integrated circuit 2 with electrons, and the lead 6 is brought close to the input / output pad 3 so that the wire 7 is long. The length can be shortened to reduce the resistance and inductance.
【００１４】さらに、第３の発明によれば、上記したよ
うな入出力パッド13を半導体チップ11の周縁近傍に設け
るとともに、その側方に配置するリードを厚さ方向に対
向させて２列となし、しかも、複数の入出力パッド13を
一面と他面からに交互にワイヤー17により引出してその
方向のリード16に接続している。Further, according to the third invention, the input / output pads 13 as described above are provided in the vicinity of the peripheral edge of the semiconductor chip 11, and the leads arranged on the sides thereof are arranged in two rows so as to face each other in the thickness direction. None, moreover, a plurality of input / output pads 13 are alternately drawn out from one surface and the other surface by wires 17 and connected to the leads 16 in that direction.
【００１５】このため、リード16は２段に分割されるこ
とになり、その分だけリード16やワイヤー17の間隔を広
くすることができ、半導体集積回路の高集積化に対応で
きることになる。また、これによってリード16の幅を広
げる余裕もでき、これによりインダクタンスや抵抗が低
減する。Therefore, the lead 16 is divided into two stages, and the interval between the lead 16 and the wire 17 can be widened by that amount, and high integration of the semiconductor integrated circuit can be dealt with. Further, this also allows a margin to widen the width of the lead 16, which reduces inductance and resistance.
【００１６】[0016]
【実施例】そこで、以下に本発明の実施例を図面に基づ
いて説明する。 （ａ）本発明の第１実施例の説明 図１は、本発明の第１実施例を示す断面図及び平面図で
ある。Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment of the Present Invention FIG. 1 is a sectional view and a plan view showing a first embodiment of the present invention.
【００１７】図１において符号１は、上層部に半導体集
積回路２を形成した半導体チップで、その中央領域に
は、アルミニウム製の入出力パッド３が半導体チップ１
を貫通して形成され、また、入出力パッド３はその内部
で半導体集積回路２に繋がっている。In FIG. 1, reference numeral 1 is a semiconductor chip in which a semiconductor integrated circuit 2 is formed in an upper layer portion, and an input / output pad 3 made of aluminum is provided in the central region of the semiconductor chip 1.
And the input / output pad 3 is internally connected to the semiconductor integrated circuit 2.
【００１８】４は、半導体チップ１を搭載する絶縁性の
ダイスで、その中央領域には、入出力パッド３の下面を
露出する開口部５が形成され、また、ダイス４の下面に
はＬ字状に曲げられたリード６がその周縁に沿って複数
本取付けられており、リード６と入出力パッド３は開口
部５を通してアルミニウムのボンディングワイヤー７に
よって接続されている。Reference numeral 4 is an insulating die for mounting the semiconductor chip 1. An opening 5 for exposing the lower surface of the input / output pad 3 is formed in the central region of the die, and the lower surface of the die 4 is L-shaped. A plurality of bent leads 6 are attached along the periphery thereof, and the leads 6 and the input / output pad 3 are connected through an opening 5 by an aluminum bonding wire 7.
【００１９】次に、上記実施例の作用について説明す
る。上述した実施例において、半導体チップ１の上面側
で半導体集積回路２に接続される入出力パッド３は、半
導体チップ１を貫通してその反対側の面に表出し、しか
も、その反対側の面の入出力パッド３とリード６とをボ
ンディングワイヤー７を介して接続するようにしてい
る。Next, the operation of the above embodiment will be described. In the above-described embodiment, the input / output pad 3 connected to the semiconductor integrated circuit 2 on the upper surface side of the semiconductor chip 1 penetrates the semiconductor chip 1 and is exposed on the opposite surface, and the opposite surface. The input / output pad 3 and the lead 6 are connected via the bonding wire 7.
【００２０】このために、入出力パッド３を半導体チッ
プ１の中央寄りに集めたＬＯＣ構造の装置であっても、
ボンディングワイヤー７が半導体集積回路２の上を跨ぐ
ことはない。Therefore, even in the LOC structure device in which the input / output pads 3 are gathered near the center of the semiconductor chip 1,
The bonding wire 7 does not cross over the semiconductor integrated circuit 2.
【００２１】したがって、半導体集積回路２に電子ビー
ムを照射してその反射電子により回路評価を行うような
試験を行う場合に、リード６と半導体集積回路２を繋ぐ
ボンディングワイヤー７が試験の邪魔になることはな
い。しかも、リード６を中央まで引き延ばして、入出力
パッド３とを結ぶボンディングワイヤー７を短くでき、
インダクタンスや抵抗の低減が図れる。Therefore, when conducting a test in which the semiconductor integrated circuit 2 is irradiated with an electron beam and the reflected electrons are used to evaluate the circuit, the bonding wire 7 connecting the lead 6 and the semiconductor integrated circuit 2 interferes with the test. There is no such thing. Moreover, by extending the lead 6 to the center, the bonding wire 7 connecting to the input / output pad 3 can be shortened,
Inductance and resistance can be reduced.
【００２２】（ｂ）本発明の第２実施例の説明 図２、３は、本発明の第２実施例装置を示す平面図、部
分拡大平面図及び部分拡大側断面図である。(B) Description of the Second Embodiment of the Present Invention FIGS. 2 and 3 are a plan view, a partially enlarged plan view and a partially enlarged side sectional view showing a device of the second embodiment of the present invention.
【００２３】図２、３において符号１１は、上層部に半
導体集積回路１２を形成した半導体チップで、その上面
の両側寄りの領域には、半導体チップ１１を上下に貫通
するアルミニウム製の入出力パッド１３が複数形成され
ており、これらの入出力パッド１３は半導体チップ１１
内で半導体集積回路１２に接続されている。2 and 3, reference numeral 11 is a semiconductor chip having a semiconductor integrated circuit 12 formed in an upper layer portion, and aluminum input / output pads vertically penetrating the semiconductor chip 11 are provided in regions on both sides of the upper surface of the semiconductor chip. A plurality of 13 are formed, and these input / output pads 13 are the semiconductor chips 11.
It is connected to the semiconductor integrated circuit 12 inside.
【００２４】１４は、半導体チップ１１を搭載する絶縁
材よりなるダイスで、その両側寄りの２つの領域には、
半導体チップ１１の下面に出た入出力パッド１３を露出
する開口部１５が形成され、また半導体チップ１１の両
側方に広がるダイス１４の上面と下面には後述する複数
のリード１６ａ，１６ｂが取付けられている。Reference numeral 14 is a die made of an insulating material on which the semiconductor chip 11 is mounted. Two dies on both sides of the die are provided.
An opening 15 is formed to expose the input / output pad 13 exposed on the lower surface of the semiconductor chip 11, and a plurality of leads 16a and 16b, which will be described later, are attached to the upper surface and the lower surface of the die 14 that spreads to both sides of the semiconductor chip 11. ing.
【００２５】上記したリード１６ａ，１６ｂは、その一
端をボンディングワイヤー１７を介して入出力パッド１
３に接続するとともに、他端をダイス１４の外部に延出
させるもので、その一端は、２つの入出力パッド１３を
跨ぐ幅又はそれ以下の幅に形成されて、隣設する２つの
入出力パッド１３毎に側方に配置されている。One end of each of the leads 16a and 16b is connected to the input / output pad 1 via the bonding wire 17.
3 and the other end thereof is extended to the outside of the die 14, and one end thereof is formed to have a width that straddles the two input / output pads 13 or a width less than that, and two adjacent input / outputs. Each pad 13 is arranged laterally.
【００２６】また、上下のリード１６ａ，１６ｂの各々
の位置関係は、半導体チップ１１近傍の一端では上下に
重なり、また、ダイス１４から突出する部分では重なら
ずにダイス１４の一辺に沿ってジズザグに並ぶような構
成となっている。The positional relationship between the upper and lower leads 16a and 16b is such that they vertically overlap at one end in the vicinity of the semiconductor chip 11 and do not overlap at the portion projecting from the die 14 along the one side of the die 14. It is configured to line up with.
【００２７】そして、半導体チップ１１の上面に露出し
た入出力パッド１３は、図２(b),図３(a) に示すよう
に、一つおきにその上面側方のリード１６ａに接続さ
れ、残りの入出力パッド１３は、図２(c),図３(b) に示
すように、その下面から開口部１５を通して下側のリー
ド１６ｂにワイヤボンディングされている。The input / output pads 13 exposed on the upper surface of the semiconductor chip 11 are connected to the leads 16a on the side of the upper surface of the semiconductor chip 11, as shown in FIGS. 2 (b) and 3 (a). The remaining input / output pad 13 is wire-bonded from its lower surface to the lower lead 16b through the opening 15 as shown in FIGS. 2 (c) and 3 (b).
【００２８】なお、図中符号１８は、半導体チップ11、
ダイス１４、リード１６ａ，１６ｂの一端及びボンディ
ングワイヤー１７を覆う樹脂製パッケージを示してい
る。上記した実施例において、半導体チップ１１に複数
形成された入出力パッド１３は、図３に示すように半導
体チップ１１を貫通して形成されている。そして、隣設
する２つの入出力パッド１３の一方は上のリード１６ａ
に接続され、他方の入出力パッド１３は下のリード１６
ｂに接続されることになる。この場合、上のリード１６
ａは入出力パッド１３の上面にワイヤボンディングさ
れ、また下のリード１６ｂは入出力パッド１３の下面に
ワイヤボンディングされる。In the figure, reference numeral 18 is a semiconductor chip 11,
A resin package that covers the die 14, the ends of the leads 16a and 16b, and the bonding wire 17 is shown. In the above-described embodiment, the plurality of input / output pads 13 formed on the semiconductor chip 11 are formed so as to penetrate the semiconductor chip 11 as shown in FIG. One of the two adjacent input / output pads 13 has an upper lead 16a.
And the other input / output pad 13 is connected to the lower lead 16
will be connected to b. In this case, the upper lead 16
a is wire-bonded to the upper surface of the input / output pad 13, and the lower lead 16b is wire-bonded to the lower surface of the input / output pad 13.
【００２９】この結果、入出力パッド１３の間隔が狭く
なる場合でも、リード１６やボンディングワイヤー１７
の間隔を広くして短絡事故の防止や歩留りの向上が図れ
ることになる。As a result, even if the space between the input / output pads 13 becomes narrow, the leads 16 and the bonding wires 17 are formed.
It is possible to prevent short-circuit accidents and improve the yield by widening the interval between.
【００３０】しかも、リード１６の幅は、最大で入出力
パッド１３を２つを含める広さに形成できるので、リー
ド１６の幅が広がる分だけ抵抗やインダクタンスが小さ
くなって信号伝達の高速化に寄与できる。Moreover, since the width of the lead 16 can be formed to a width including the two input / output pads 13 at the maximum, the resistance and the inductance are reduced as the width of the lead 16 is increased, and the speed of signal transmission is increased. Can contribute.
【００３１】（ｃ）本発明の実施例における入出力パッ
ドの形成工程の説明 図４、５は、本発明の実施例装置における半導体チップ
の入出力パッドを形成する工程を示す断面図である。(C) Description of I / O Pad Forming Steps in the Embodiment of the Present Invention FIGS. 4 and 5 are sectional views showing the steps of forming the input / output pads of the semiconductor chip in the device of the embodiment of the present invention.
【００３２】図中符号３１は、上記した半導体チップ
１，１１を構成する厚さ約１ｍｍのシリコン基板で、こ
のシリコン基板３１のうち複数のパッド形成領域Ｘの上
には、上面側の半導体集積回路２，１２に繋がる導電膜
３２が形成されている。In the figure, reference numeral 31 is a silicon substrate having a thickness of about 1 mm which constitutes the above-mentioned semiconductor chips 1 and 11. Above the plurality of pad formation regions X of the silicon substrate 31, the semiconductor integrated on the upper surface side. A conductive film 32 connected to the circuits 2 and 12 is formed.
【００３３】この状態において、まず図４(a) に示すよ
うに、シリコン基板３１の上にフォトレジスト３３を塗
布し、これを露光、現像してパッド形成領域Ｘに窓３４
を開口する。In this state, first, as shown in FIG. 4A, a photoresist 33 is applied on the silicon substrate 31, and this is exposed and developed to form a window 34 in the pad formation region X.
To open.
【００３４】次に、同図(b) に示すように、反応性イオ
ンエッチング（ＲＩＥ）法によって窓３４の下の導電膜
３２及びシリコン基板３１を深さ５００μｍまでエッチ
ングしてパッド形成領域Ｘに凹部３５を形成する。Next, as shown in FIG. 3B, the conductive film 32 and the silicon substrate 31 under the window 34 are etched to a depth of 500 μm by the reactive ion etching (RIE) method to form a pad formation region X. The recess 35 is formed.
【００３５】この後に、フォトレジスト３３を溶剤によ
り除去してから、数千Åの厚さのSiO2膜３６をＣＶＤ法
によって形成し、このSiO2膜３６により凹部３５を埋め
込んで、さらに、ＲＩＥ法によりSiO2膜３６を異方性エ
ッチングし、凹部３５の側壁にのみこれを残す（図４
(c))。After that, the photoresist 33 is removed by a solvent, and then a SiO 2 film 36 having a thickness of several thousand Å is formed by the CVD method. The SiO 2 film 36 fills the concave portion 35, and the RIE is further performed. The SiO 2 film 36 is anisotropically etched by the method to leave it only on the side wall of the recess 35 (FIG. 4).
(c)).
【００３６】次に、図４(d) に示すように、スパッタ法
によりアルミニウム３７を積層して凹部３５を完全に埋
め込むと、アルミニウム３７の上部はほぼ平坦になる。
そして、全体をＲＩＥ法によりコントロールエッチング
して薄層化し、ついでフォトレジストを用いたエッチン
グ法によって凹部３５内のみにアルミニウム３７を残存
させる（図５(e))。凹部３５内のアルミニウム３７は、
上記した入出力パッド３、１３としてい用いられ、導電
膜３２を介して半導体集積回路２（１２）に接続され、
しかも、SiO2膜３６によりシリコン基板３１から絶縁さ
れた状態になる。Next, as shown in FIG. 4D, when aluminum 37 is laminated by the sputtering method to completely fill the recess 35, the upper part of the aluminum 37 becomes substantially flat.
Then, the whole is controlled by the RIE method to form a thin layer, and the aluminum 37 is left only in the recess 35 by the etching method using a photoresist (FIG. 5E). The aluminum 37 in the recess 35 is
It is used as the input / output pads 3 and 13 and is connected to the semiconductor integrated circuit 2 (12) through the conductive film 32.
Moreover, the SiO 2 film 36 insulates the silicon substrate 31.
【００３７】この後に、シリコン基板３１の下面を研磨
して凹部３５の底面を開放すれば、図５(f) に示すよう
にシリコン基板３１から入出力パッド３，１３が露出す
ることになる。研磨後のシリコン基板３の厚みは約５０
０μｍとなる。After that, if the lower surface of the silicon substrate 31 is polished to open the bottom surface of the recess 35, the input / output pads 3 and 13 are exposed from the silicon substrate 31 as shown in FIG. 5 (f). The thickness of the silicon substrate 3 after polishing is about 50.
It becomes 0 μm.
【００３８】なお、パッド形成領域Ｘは、ＺＩＰの場合
には半導体チップの両側に位置し、また、ＬＯＣ構造の
場合には半導体チップの中央に位置することになる。The pad formation regions X are located on both sides of the semiconductor chip in the case of ZIP and in the center of the semiconductor chip in the case of LOC structure.
【００３９】[0039]
【発明の効果】以上述べたように本発明によれば、半導
体集積回路に接続される入出力パッドを、半導体チップ
に貫通させてその両面に表出するようにしているので、
半導体集積回路に対する信号を半導体チップの両面から
出し入れすることができ、配線の自由度を高くすること
ができる。As described above, according to the present invention, the input / output pads connected to the semiconductor integrated circuit are made to penetrate through the semiconductor chip and exposed on both sides thereof.
Signals to and from the semiconductor integrated circuit can be taken in and out from both sides of the semiconductor chip, and the degree of freedom of wiring can be increased.
【００４０】第２の発明によれば、半導体チップを貫通
する入出力パッドを半導体チップの中央領域に設けると
ともに、リードとの接続を半導体集積回路と反対側の面
で行うようにしているので、半導体集積回路に電子を照
射して行われるような試験の際の障害を除去でき、しか
も、リードを入出力パッドに近づけてワイヤー長を短く
して抵抗やインダクタンスを低減することができる。According to the second invention, since the input / output pad penetrating the semiconductor chip is provided in the central region of the semiconductor chip, the connection with the lead is made on the surface opposite to the semiconductor integrated circuit. It is possible to eliminate obstacles in a test that is performed by irradiating a semiconductor integrated circuit with electrons, and further, to reduce the resistance and the inductance by bringing the lead close to the input / output pad to shorten the wire length.
【００４１】第３の発明によれば、半導体チップを貫通
する入出力パッドを半導体チップの周縁近傍に設けると
ともに、その側方に配置するリードを厚さ方向に対向さ
せて２列となし、さらに、複数の入出力パッドを一面と
他面からに交互にワイヤーにより引出してその方向のリ
ードに接続するようにしたので、リードは厚さ方向に２
段に分割されてリードやワイヤーの間隔を広くする溶融
ができ、半導体集積回路の高集積化に対応できる。ま
た、これによってリードの幅を広げることもできこれに
よりインダクタンスや抵抗を低減することができる。According to the third aspect of the invention, the input / output pads penetrating the semiconductor chip are provided in the vicinity of the periphery of the semiconductor chip, and the leads arranged on the sides are arranged in two rows so as to face each other in the thickness direction. , I / O pads are alternately pulled out from one side and the other side by wires and connected to the leads in that direction, so the leads are 2 in the thickness direction.
It is possible to melt by widening the intervals of leads and wires by dividing into stages, and it is possible to cope with high integration of semiconductor integrated circuits. Further, the width of the lead can be widened by this, and thereby the inductance and the resistance can be reduced.
【図１】本発明の第１実施例装置を示す側断面図及び平
面図である。FIG. 1 is a side sectional view and a plan view showing a device according to a first embodiment of the present invention.
【図２】本発明の第２実施例装置を示す平面図及び部分
拡大平面図である。FIG. 2 is a plan view and a partially enlarged plan view showing a second embodiment device of the present invention.
【図３】本発明の第２実施例装置を示す部分拡大側断面
図である。FIG. 3 is a partially enlarged side sectional view showing a second embodiment device of the present invention.
【図４】本発明の実施例装置における入出力パッドの形
成工程の一例を示す断面図（その１）である。FIG. 4 is a cross-sectional view (1) showing an example of the process of forming the input / output pad in the device of the embodiment of the present invention.
【図５】本発明の実施例装置における入出力パッドの形
成工程の一例を示す断面図（その２）である。FIG. 5 is a sectional view (No. 2) showing an example of the step of forming the input / output pad in the device of the embodiment of the present invention.
【図６】従来装置の第１の例を示す側断面図及び平面図
である。FIG. 6 is a side sectional view and a plan view showing a first example of a conventional device.
【図７】従来装置の第２の例を示す平面図及び部分拡大
平面図である。7A and 7B are a plan view and a partially enlarged plan view showing a second example of the conventional device.
１, 11 半導体チップ ２, 12 半導体集積回路 ３, 13 入出力パッド ４, 14 ダイス ５，15 開口部 ６，16 リード ７，17 ボンディングワイヤー 1, 11 Semiconductor chip 2, 12 Semiconductor integrated circuit 3, 13 Input / output pad 4, 14 Dice 5,15 Opening 6,16 Lead 7,17 Bonding wire
Claims (3)
した半導体チップ（１、11）と、 前記半導体集積回路（２、12）に繋がり、かつ前記半導
体チップ（１、11）を厚み方向に貫通して両面に表出さ
れる入出力パッド（３，13）と、 前記入出力パッド（３，13）の表出面の一方又は他方に
ワイヤー（７，17）を介して接続されるリード（６，1
6）とを有することを特徴とする半導体装置。1. A semiconductor chip (1, 11) having a semiconductor integrated circuit (2, 12) formed on one surface thereof, and a semiconductor chip (1, 11) connected to the semiconductor integrated circuit (2, 12). An input / output pad (3, 13) that penetrates in the thickness direction and is exposed on both sides, and is connected to one or the other of the exposed surfaces of the input / output pad (3, 13) via a wire (7, 17). Reed (6,1
6) A semiconductor device comprising:
プ（１）の中央領域に形成され、かつ、前記半導体集積
回路（２）と反対側の面に表出した前記入出力パッド
（３）に前記リード（６）が接続されていることを特徴
とする請求項１記載の半導体装置。2. The input / output pad (3) formed in the central region of the semiconductor chip (1) and exposed on the surface opposite to the semiconductor integrated circuit (2). 2. The semiconductor device according to claim 1, wherein the lead (6) is connected to (1).
プ（11）の周縁近傍に形成され、 前記リード（17）が前記入出力パッド（13）の側方にお
いて厚さ方向に相対向して２列に配置され、 しかも、複数の前記入出力パッド（13）は、一面側と他
面側から交互に前記ワイヤー（17）が接続されてそれぞ
れ一面側と他面側の前記リード（16）に接続されている
ことを特徴とする請求項１記載の半導体装置。3. The input / output pad (13) is formed in the vicinity of the peripheral edge of the semiconductor chip (11), and the leads (17) face each other in the thickness direction laterally of the input / output pad (13). The plurality of input / output pads (13) are alternately connected to the wires (17) from one surface side and the other surface side so that the leads (16) on the one surface side and the other surface side, respectively. ) Is connected to the semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3205315A JPH0547829A (en) | 1991-08-15 | 1991-08-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3205315A JPH0547829A (en) | 1991-08-15 | 1991-08-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547829A true JPH0547829A (en) | 1993-02-26 |
Family
ID=16504917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3205315A Withdrawn JPH0547829A (en) | 1991-08-15 | 1991-08-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547829A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE41478E1 (en) | 1994-12-20 | 2010-08-10 | Renesas Electronics Corporation | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
-
1991
- 1991-08-15 JP JP3205315A patent/JPH0547829A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE41478E1 (en) | 1994-12-20 | 2010-08-10 | Renesas Electronics Corporation | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
| USRE41721E1 (en) | 1994-12-20 | 2010-09-21 | Renesas Electronics Corporation | Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes |
| USRE41722E1 (en) | 1994-12-20 | 2010-09-21 | Renesas Electronics Corp. | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
| USRE42972E1 (en) | 1994-12-20 | 2011-11-29 | Renesas Electronics Corporation | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
| USRE43444E1 (en) | 1994-12-20 | 2012-06-05 | Renesas Electronics Corporation | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981112 |