US9362943B2 - Converter - Google Patents

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Publication number
US9362943B2
US9362943B2 US14/695,385 US201514695385A US9362943B2 US 9362943 B2 US9362943 B2 US 9362943B2 US 201514695385 A US201514695385 A US 201514695385A US 9362943 B2 US9362943 B2 US 9362943B2
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Prior art keywords
signal
input
clock signal
output
cycle
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Expired - Fee Related
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US14/695,385
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US20150236713A1 (en
Inventor
Akira Yasuda
Jun-ichi Okamura
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Trigence Semiconductor Inc
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Trigence Semiconductor Inc
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Assigned to TRIGENCE SEMICONDUCTOR, INC. reassignment TRIGENCE SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OKAMURA, JUN-ICHI, YASUDA, AKIRA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
    • H03M3/3283—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being in the time domain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation

Definitions

  • the present invention is related to a converter which converts an analog signal to a digital signal (an analog-digital converter), and a converter which converts a digital signal to an analog signal (a digital-analog converter).
  • an analog-digital converter and a digital-analog converter each of which uses a ⁇ modulator.
  • a method to use a ⁇ modulator as shown in FIG. 1 for example is used.
  • quantization of an input signal passed through a loop filter is once performed at a lower resolution than the precision finally required and the result is fed back to the input.
  • over-sampling is performed at a sampling frequency higher than the sampling frequency finally required.
  • Noise within the signal band can be reduced by increasing a ratio (an oversampling ratio) of the sampling frequency finally required and the sampling frequency by performing over-sampling.
  • the present invention aims to improve this problem by providing an analog-digital converter, a digital-analog converter, a digital direct drive system and a digital direct drive speaker, which significantly reduces unwanted radiation while maintaining conversion accuracy.
  • a data converter including a clock signal input part which inputs a clock signal, an input part which inputs an input signal, a sampling part which performs sampling of the input signal input to the input part in response to the clock signal input to the clock signal input part, and a signal processing part which performs signal processing in accordance with a sampling cycle and outputs an output signal, wherein when the cycle of the clock signal input to the clock signal input part becomes longer, the output signals output by the signal processing part are reduced is provided.
  • a data converter including a clock signal input part which inputs a clock signal having a cycle which dynamically changes, an input part which inputs an input signal, a cycle detection part which detects a cycle of a clock signal input to the clock signal input part, and a signal processing part which performs signal processing of an input signal input to the input part according to a cycle of a clock signal detected by the cycle detection part and outputs an output signal is provided.
  • a data converter including an input part which inputs an input signal, an integrator which integrates a signal output by the input part, a quantizer which quantizes a signal output by the integrator, and a sampler which samples an output of the quantizer in response to a clock signal having a variable cycle, wherein the input part includes a subtractor for performing a subtraction process of an output of the sampler from an input signal and outputs is provided.
  • a data converter including an input part which inputs an input signal, a loop filter input with a signal output by the input part, a quantizer which quantizes a signal output by the loop filter, and a sample which sampler an output of the quantizer according to a clock signal having a variable cycle, wherein the input part includes a subtractor for performing a subtraction process of an output of the sampler from the input signal and for performing outputting is provided.
  • a data converter including a clock signal input part which inputs a clock signal, an input part which inputs an input signal, a sampling part which samples an input signal input to the input part in response to a clock signal input to the clock signal input part, a signal processing part which performs signal processing according to a cycle of the sampling and outputs an output signal, and a driver which drives an actuator according to an output signal output by the signal processing part, wherein when a cycle of a clock signal input to the clock signal input part becomes longer, an output signal output by the signal processing part is reduced is provided.
  • FIG. 1 is a structural diagram of a digital-analog converter
  • FIG. 2 is a structural diagram of a digital-analog converter which uses a clock modulation
  • FIG. 3 is a structural diagram of a data converter related to a first embodiment of the present invention.
  • FIG. 4 is a structural diagram of a data converter related to a second embodiment of the present invention.
  • FIG. 5 is a structural diagram of a data converter related to a third embodiment of the present invention.
  • FIG. 6 is a structural diagram of a data converter related to a fourth embodiment of the present invention.
  • FIG. 7 is a structural diagram of a data converter related to a fifth embodiment of the present invention.
  • FIG. 8A is a structural diagram of a data converter related to a sixth embodiment of the present invention.
  • FIG. 8B (a) is a graph showing an output spectrum of a conventional data converter and (b) is a graph showing an output spectrum of a data converter in the sixth embodiment of the present invention
  • FIG. 8C (a) is a graph showing an output spectrum of a wide band of a conventional data converter and (b) is a graph showing an output spectrum of a wide band of the data converter in the sixth embodiment of the present invention
  • FIG. 9 is a structural diagram of a data converter related to a seventh embodiment of the present invention.
  • FIG. 10 is a structural diagram of a data converter related to an eighth embodiment of the present invention.
  • FIG. 11 is a structural diagram of a data converter related to a ninth embodiment of the present invention.
  • FIG. 12 is a structural diagram of a data converter related to a tenth embodiment of the present invention.
  • FIG. 13 is a diagram showing an example structure of a mismatching shaper used in a data converter related to a tenth embodiment of the present invention.
  • FIG. 14 is a structural diagram of a data converter related to an eleventh embodiment of the present invention.
  • FIG. 15 is a structural diagram of a data converter related to a twelfth embodiment of the present invention.
  • the first embodiment of the present invention is explained with reference to FIG. 3 .
  • Sampling using a sampling means within a sampling data converter ( 201 ) is performed by synchronizing an input signal that is input to an input means ( 101 ) with a clock signal input to a clock signal input means ( 301 ) and signal processing is performed by a signal processing means in accordance with a cycle of the sampling.
  • a digital signal is converted to analog
  • the cycle of the sampling changes, the timing of an output signal is changed by variation of a cycle of a clock frequency.
  • the pulse width of the output signal becomes wider, and it becomes equivalent to the output signal becoming large. In this way, it is possible to diffuse a spectrum of the output signal and to reduce a peak value of the spectrum at a particular frequency.
  • a data converter ( 201 ) in the present embodiment it is possible to configure, various converters such as an analog-digital converter, a digital-analog converter, an oversampling type analog-digital converter, an oversampling type oversampling type, a ⁇ modulator, a ⁇ type digital-analog converter, and a ⁇ analog-digital converter.
  • various converters such as an analog-digital converter, a digital-analog converter, an oversampling type analog-digital converter, an oversampling type oversampling type, a ⁇ modulator, a ⁇ type digital-analog converter, and a ⁇ analog-digital converter.
  • a clock signal generator ( 501 ) which has a cycle changed dynamically is connected to a clock input means ( 301 ) of a data converter ( 201 ), the clock signal generator ( 501 ) is connected to a cycle detection means ( 601 ) and the cycle detecting means ( 601 ) detects a cycle of an input clock signal.
  • the output of the cycle detecting means ( 601 ) is connected to the data converter ( 201 ) and a signal processing part of the data converter ( 201 ) performs signal processing according to the output of the cycle detection means ( 601 ).
  • a third embodiment of the present invention is explained with reference to FIG. 5 .
  • the present embodiment uses a clock generation circuit in which a cycle varies dynamically.
  • a clock generation part is formed by a clock signal generating means ( 502 ), a division means ( 503 ) and a division ratio generating means ( 504 ).
  • the division means ( 503 ) divides the clock signal generating means ( 502 ) in accordance with a signal of the division ratio generating means ( 504 ).
  • the division ratio generating means ( 504 ) can dynamically vary a division ratio.
  • a data converter ( 201 ) is formed from an integrating means ( 701 ), a subtracting means ( 601 ), a quantization means ( 703 ), and a sampling means ( 704 ).
  • the output of the sampling means ( 704 ) is subtracted by the subtraction means ( 601 ) from an input signal, and this signal is integrated by the integration means ( 701 ) and quantized by the quantization means ( 703 ).
  • the quantized signal is sampled by the sampling means ( 704 ).
  • the quantization and sampling can also be configured using the same means as a comparator circuit etc.
  • the sampling means ( 704 ) performs sampling in response to the clock signal of a variable cycle clock signal generator ( 501 ). Therefore, in the case where the cycle of the clock signal becomes longer, the time period for holding the output signal also becomes longer.
  • the signal obtained by subtracting the output of the sampling means ( 704 ) by the subtraction means ( 601 ) from the input signal is integrated by the integration means ( 701 ). Therefore, the output signal of the subtraction means ( 601 ) is time-integrated corresponding to the cycle of the variable cycle clock signal generator ( 501 ).
  • a fifth embodiment of the present invention is explained with reference to FIG. 7 .
  • the present embodiment is different in that the integrator in the fourth embodiment is replaced with a loop filter.
  • a ⁇ modulator by increasing the order of an integrator used in a loop, it is possible to reduce noise in the band, and improve conversion accuracy. Also in the present invention, it is possible to improve the conversion accuracy by increasing the order of a loop filter. In addition, by using a resonator as a loop filter, it is possible to reduce noise at a particular frequency and realize so-called band-pass conversion characteristics.
  • a sixth embodiment of the present invention is explained in more detail with reference to FIG. 8A .
  • An integrator is formed using a flip-flop ( 705 ) and an adding means ( 602 ) and the output of the integrator is multiplied with a coefficient by a coefficient means ( 603 ).
  • the output of the integrator at the last stage is quantized by a quantization means ( 703 ) and sampled by the flip-flop ( 705 ).
  • the clock of the flip-flop determines the sampling timing by a signal from a clock signal generator ( 501 ) which has a cycle dynamically changed.
  • a fixed cycle clock signal is supplied to the flip-flop ( 705 ), which forms the integrator.
  • FIG. 8B (a) shows an output spectrum in the case of use of the conventional art
  • FIG. 8B (b) shows an output spectrum of the present embodiment.
  • FIG. 8C shows output spectrums in a wide band.
  • FIG. 8C (a) shows an output spectrum in a wide band in a data converter in the conventional art
  • FIG. 8C (b) shows an output spectrum in a wide band of a data converter of the present embodiment. It can be seen that by using the present embodiment, it is possible to significantly reduce the peak level of the spectrum.
  • a seventh embodiment of the present invention is explained in detail with reference to FIG. 9 .
  • the present embodiment is different to the fifth embodiment shown in FIG. 7 in that a clock signal generating means ( 501 ) with a variable cycle is also connected to a loop filter means ( 702 ).
  • the loop filter means ( 702 ) the cycle of the clock signal generating means ( 501 ) with a variable cycle is detected based on two clock signals from the clock signal generating means ( 501 ) with a variable cycle and a fixed cycle clock signal generating means ( 502 ), and a coefficient of the loop filter is changed according to this cycle.
  • An integrator is formed from a flip-flop ( 705 ) and an adding means ( 602 ) and the output of the integrator is multiplied with a coefficient by a variable coefficient means ( 604 ).
  • the integrators are connected in series in two stages, it is possible to connect the integrators in three stages or more.
  • the output of the integrator at the last stage is quantized by a quantization means ( 703 ) and sampled by the flip-flop ( 705 ).
  • both the flip-flop which forms an integrator and the flip-flop arranged after the quantizer are connected to a divider ( 503 ).
  • the divider ( 503 ) divides a clock signal generation means ( 502 ) with a fixed cycle according to the division ratio of a division ratio generation means ( 504 ) and generates a variable cycle clock signal. Therefore, both of the flip-flops are driven by the variable cycle clock signals.
  • the coefficient of the variable coefficient means ( 604 ) is modified according to the division ratio generating means ( 504 ). In this way, it is possible to change the characteristics of a loop filter formed by the integrators in response to the variable cycle clock cycle from the divider ( 503 ) and to significantly reduce the deterioration of characteristics due to changes in a clock cycle.
  • a ninth embodiment of the present invention is explained with reference to FIG. 11 .
  • a driver means ( 801 ) is connected as a subsequent stage of a data converter of the first embodiment.
  • Driver means ( 801 ) has a characteristic of being able to drive an actuator or the like connected to the driver means ( 801 ).
  • a driver circuit with sufficiently low output impedance may be provided. In this way, it is possible to accurately convey a signal generated by the data converter means ( 201 ) to an actuator or the like and achieve high-precision conversion.
  • thermometer code it is possible to reduce the variation in characteristics of the driver circuit and actuator.
  • the driver means ( 801 ) it is also possible to convert an output an input signal to a 3 value code for driving each actuator driving in three states such as +1, 0, and ⁇ 1.
  • a 3 value code for driving each actuator driving in three states such as +1, 0, and ⁇ 1.
  • the driver means ( 801 ) is connected to the data converting means ( 201 ), it is possible to connect the output of any of the embodiments described above and to improve performance.
  • a tenth embodiment of the present invention is explained with reference to FIG. 12 .
  • a mismatch shaper means ( 901 ) is inserted between a data conversion means ( 201 ) of the ninth embodiment and a driver means ( 801 ).
  • a configuration example of the mismatch shaper means ( 901 ) is shown in detail in FIG. 13 .
  • the mismatch shaper means ( 901 ) is formed by a selection means ( 902 ) and a filter means ( 903 ) and selects the selection object such as an actuator according to the value specified by the input signal.
  • the driver means ( 801 ) uses a 3 value code
  • a signal of one of the three states +1, 0, ⁇ 1 to an actuator is output. This selection is carried out in accordance with the output of the filter means ( 903 ).
  • the filter means is formed from a filter connecting integrators in cascade in general.
  • the filter means is formed from a filter connecting integrators in cascade in general, it is possible to improve the properties by processing according to the cycle of the mismatch shaper means ( 901 ).
  • the filter means ( 903 ) By configuring the filter means ( 903 ) the same as a loop filter shown in the fifth to eighth embodiments, processing according to the output period becomes possible and mismatch shaping in consideration of the output time can be achieved.
  • a speaker is used as an actuator.
  • a twelfth embodiment of the present invention is explained with reference to FIG. 15 .
  • a digital-analog conversion means ( 1002 ) is used as an actuator.
  • a digital-analog conversion means 1002
  • the present invention it is possible to dynamically change a cycle of a clock signal used in a digital-analog converter, and to significantly reduce an internal signal of an analog-digital converter and a digital-analog converter, and an irradiated signal without degrading conversion accuracy while dispersing the spectrum. In this way, it is possible to use a clock signal with a higher frequency and achieve higher resolution with higher conversion accuracy.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
US14/695,385 2012-10-25 2015-04-24 Converter Expired - Fee Related US9362943B2 (en)

Applications Claiming Priority (3)

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JP2012235910 2012-10-25
JP2012-235910 2012-10-25
PCT/JP2013/078998 WO2014065408A1 (ja) 2012-10-25 2013-10-25 変換器

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PCT/JP2013/078998 Continuation WO2014065408A1 (ja) 2012-10-25 2013-10-25 変換器

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US9362943B2 true US9362943B2 (en) 2016-06-07

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EP (1) EP2913931A4 (ja)
JP (1) JP6316751B2 (ja)
KR (1) KR20150077420A (ja)
CN (1) CN104718704A (ja)
IN (1) IN2015DN03872A (ja)
WO (1) WO2014065408A1 (ja)

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CN104581589B (zh) * 2014-12-31 2018-01-02 苏州上声电子有限公司 基于三态编码的通道状态选取方法和装置
US9397677B1 (en) * 2015-11-02 2016-07-19 Keysight Technologies, Inc. Method and system for digital-to-analog converter performance measurement using equivalent-time sampler
CN105761691A (zh) * 2016-05-04 2016-07-13 深圳市华星光电技术有限公司 栅极扫描线驱动方法、驱动模块及tft-lcd显示面板

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US20110069211A1 (en) 2009-09-23 2011-03-24 Samsung Electronics Co., Ltd. Analog-to-digital converter for controlling gain by changing a system parameter, image sensor including the analog-to-digital converter and method of operating the analog-to-digital converter

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US5471209A (en) * 1994-03-03 1995-11-28 Echelon Corporation Sigma-delta converter having a digital logic gate core
JP2007243504A (ja) 2006-03-08 2007-09-20 Nec Corp 移動通信端末における信号処理システム及びその方法並びにそれを用いた移動通信端末
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EP2913931A1 (en) 2015-09-02
WO2014065408A1 (ja) 2014-05-01
KR20150077420A (ko) 2015-07-07
IN2015DN03872A (ja) 2015-10-02
US20150236713A1 (en) 2015-08-20
JPWO2014065408A1 (ja) 2016-09-08
EP2913931A4 (en) 2016-08-03
CN104718704A (zh) 2015-06-17
JP6316751B2 (ja) 2018-04-25

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