US9271388B2 - Interposer and package on package structure - Google Patents
Interposer and package on package structure Download PDFInfo
- Publication number
- US9271388B2 US9271388B2 US14/064,202 US201314064202A US9271388B2 US 9271388 B2 US9271388 B2 US 9271388B2 US 201314064202 A US201314064202 A US 201314064202A US 9271388 B2 US9271388 B2 US 9271388B2
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- US
- United States
- Prior art keywords
- interposer
- thermal conductive
- insulating base
- contact pads
- conductive pillars
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Definitions
- the present disclosure relates to packaging structures for semiconductor devices, particularly to an interposer and a package on package (POP) structure including the interposer.
- POP package on package
- the diameter of the solder ball may be in the range from 200 um to 300 um which is quite large. It is difficult to reduce the volume of the POP structure due to the large diameters of the solder ball and the large size of contact pad corresponding to the solder ball. The structural strength and integrity of the connection between the solder ball and the contact pad is not optimal due to the large diameter of the solder ball. So, the reliability of POP structure is not good.
- the bottom one of the two electric elements is usually provided between two circuit boards. Heat created by the bottom electric elements is hard to dissipate due to undesirable insulation given by the two circuit boards.
- FIG. 1 is a schematic, cross-sectional view of an interposer according to a first embodiment.
- FIG. 2 is a bottom view of the interposer of FIG. 1 .
- FIG. 3 is a schematic, cross-sectional view of an interposer according to a second embodiment.
- FIG. 4 is a schematic, cross-sectional view of an interposer according to a third embodiment.
- FIGS. 5-7 are schematic, cross-sectional views of a POP structure.
- FIGS. 1-2 show an interposer 100 according to a first embodiment.
- the interposer 100 includes an insulating base 110 , a plurality of electric conductive pillars 120 , and a thermal conductive frame 130 .
- the insulating base 110 includes a first surface 111 and a second surface 112 opposite to the first surface 111 .
- a plurality of through holes 113 is defined in the insulating base 110 .
- the through holes 113 are separated from each other.
- a groove 114 is defined in the first surface 112 to the inside of the insulating base 110 .
- the electric conductive pillars 120 are aligned with and arranged in the through holes 113 .
- An electric conductive pillar 120 includes a first end face 121 and a second end face 122 opposite to the first end face 121 .
- a height of each electric conductive pillar 120 is greater than the thickness of the insulating base 110 in this embodiment.
- the first end face 121 and the first surface 111 are coplanar.
- the second end face 122 protrudes from the second surface 112 .
- the height of the electric conductive pillar 120 relative to the second surface 112 is greater than the thickness of the insulating base 110 . Extension direction of the electric conductive pillar 120 is perpendicular to the second surface 112 .
- the thermal conductive frame 130 includes a top plate 131 and a plurality of thermal conductive pillars 132 perpendicularly interconnected with the top plate 131 .
- the top plate 131 is received in the groove 114 .
- the thermal conductive pillars 132 perpendicularly extend from the border of the top plate 131 .
- the material of the thermal conductive frame 130 is thermally conductive metal such as copper, aluminum, or silver.
- the material of the thermal conductive frame 130 is copper, is the same as that of the electric conductive pillar 120 .
- the height of the electric conductive pillar 120 relative to the insulating base 110 is equal to that of the thermal conductive pillar 132 relative to the insulating base 110 .
- the interposer 100 also includes a plurality of first contact pads 150 .
- the first contact pads 150 are formed on the first surface 111 .
- the first contact pads 150 are aligned with the electric conductive pillars 120 .
- the first contact pad 150 is electrically connected with the first end face 121 of an electric conductive pillar 120 .
- a solder mask layer 101 is formed on the first surface 111 .
- a plurality of openings 1011 are defined in the solder mask layer 101 .
- the first contact pads 150 are exposed through the openings 1011 .
- FIG. 3 shows an interposer 200 according to a second embodiment.
- the structure of the interposer 200 is similar to that of the interposer 100 of the first embodiment.
- the interposer 200 includes an insulating base 210 , a plurality of electric conductive pillars 220 , a thermal conductive connector 240 , a plurality of conductive vias 250 , and a thermal conductive frame 230 .
- the insulating base 210 includes a first surface 211 and a second surface 212 opposite to the first surface 211 .
- a plurality of through holes 213 is defined in the insulating base 210 .
- the diameter of the through hole 213 gradually reduces from the first surface 211 to the second surface 212 .
- the electric conductive pillars 220 are aligned with the conductive vias 250 . Extension direction of the electric conductive pillars 220 is perpendicular to the second surface 212 . A height of each electric conductive pillar 220 is greater than the thickness of the insulating base 210 .
- the thermal conductive frame 230 is formed on the second surface 212 .
- the thermal conductive frame 230 includes a top plate 231 and a plurality of thermal conductive pillars 232 .
- the top plate 231 includes a top surface 2311 facing away from the thermal conductive pillars 232 .
- the top surface 2311 is in contact with the second surface 212 .
- the top surface 2311 and the second surface 212 are coplanar.
- the thermal conductive pillars 232 perpendicularly extend from the border of the top plate 231 .
- the material of the thermal conductive frame 230 is thermally conductive metal such as copper, aluminum, or silver. In one embodiment, the material of the thermal conductive frame 230 is copper and is same as that of the electric conductive pillar 220 .
- the thermal conductive connector 240 is also formed on the second surface 212 .
- the thermal conductive connector 240 interconnects between the thermal conductive frame 230 and an electric conductive pillar 220 .
- the interposer 200 also includes a plurality of first contact pads 260 .
- the first contact pad 260 is defined on the first surface 211 .
- Each of the first contact pads 260 is electrically connected with a conductive via 250 .
- the first contact pad 260 and the conductive via 250 corresponding to the first contact pad 260 are integrated.
- FIG. 4 shows an interposer 300 according to a third embodiment.
- the structure of the interposer 300 is similar to that of the interposer 100 of the first embodiment.
- the interposer 300 includes an insulating base 310 , a plurality of electric conductive pillars 320 , and a thermal conductive frame 330 .
- the insulating base 310 includes a first surface 311 and a second surface 312 opposite to the first surface 311 .
- a plurality of through holes 313 is defined in the insulating base 310 .
- the through holes 313 are separated from each other.
- a receiving hole 314 is defined in the second surface 311 through to the first surface 312 .
- the receiving hole 314 is surrounded by the through holes 313 .
- the electric conductive pillars 320 are aligned with and received in the through holes 313 .
- the electric conductive pillar 320 includes a first end face 321 and a second end face 322 opposite to the first end face 321 .
- the height of each electric conductive pillar 320 is greater than the thickness of the insulating base 310 in this embodiment.
- the first end face 321 and the first surface 311 are coplanar.
- the second end face 322 protrudes from the second surface 312 .
- a height of the electric conductive pillar 320 relative to the second surface 312 is greater than the thickness of the insulating base 310 .
- the thermal conductive frame 330 is partially received in the receiving hole 314 .
- the thermal conductive frame 330 includes a top plate 331 and a plurality of thermal conductive pillars 332 perpendicularly interconnected with the top plate 331 .
- the top plate 331 includes a top surface 3311 facing away from the thermal conductive pillars 332 .
- the top surface 3311 and the first surface 311 are coplanar.
- the thermal conductive pillars 332 perpendicularly extend from the border of the top plate 331 . Extension direction of the thermal conductive pillar 332 is equal to that of the electric conductive pillar 320 .
- the material of the thermal conductive frame 330 is thermally conductive metal such as copper, aluminum, or silver. In one embodiment, the material of the thermal conductive frame 330 is copper, the same as that of the electric conductive pillar 320 .
- the interposer 300 also includes a plurality of first contact pads 350 .
- the first contact pad 350 is defined on the first surface 311 .
- Each of the first contact pads 350 is aligned with and electrically connected with an electric conductive pillar 320 .
- a solder mask layer is formed on the first surface of the second or the third embodiment.
- a plurality of openings is defined in the solder mask layer. The first contact pads are exposed through the corresponding openings.
- the interposer can also includes a thermal conductive connector of the first or the third embodiment.
- the thermal conductive frame and some of the electric conductive pillars are interconnected through the thermal conductive connectors.
- FIG. 5 shows a POP structure 10 according to a fourth embodiment.
- the POP structure 10 includes a first package substrate 20 , a first chip 30 , a second package substrate 40 , a second chip 50 , a first solder 60 , a second solder 70 , and an interposer of the first embodiment, the second embodiment, or the third embodiment.
- an interposer 100 is provided according to the first embodiment.
- the first package substrate 20 includes a first base layer 21 , a first circuit layer 22 , a second circuit layer 23 , a first solder mask layer 24 , a second solder mask layer 25 , and a plurality of solder balls 26 .
- the first circuit layer 22 and the second circuit layer 23 are formed on the opposite surface of the first base layer 21 .
- the first solder mask layer 24 is formed on the surface of the first circuit layer 22 .
- the second solder mask layer 25 is formed on the surface of the second circuit layer 23 .
- the first base layer 21 is a multilayer substrate.
- the first base layer 21 includes a plurality of resin layers alternating with a plurality of circuit layers.
- the first base layer 21 includes a third surface 2110 and a fourth surface 2120 opposite to the third surface 2110 .
- the first circuit layer 22 is formed on the third surface 2110 .
- the second circuit 23 is formed on the fourth surface 2120 .
- the first circuit layer 22 , the second circuit layer 23 , and the other circuit layer of the first base layer 21 are electrically connected through a plurality of conductive vias.
- Portions of the first circuit layer 22 are exposed through the first solder mask layer 24 .
- the exposed portions of the first circuit layer 22 are defined to be a plurality of third contact pads 2210 and a plurality of fourth contact pads 2220 .
- the third contact pads 2210 are arranged in an array.
- the third contact pads 2210 are surrounded by the fourth contact pads 2220 .
- Portions of the second circuit layer 23 are exposed through the second solder mask layer 25 .
- the exposed portions of the second circuit layer 23 are defined to be a plurality of fifth contact pads 2310 .
- the fifth contact pads 2310 are arranged in an array.
- the third contact pads 2210 , the fourth contact pads 2220 and the fifth contact pads 2310 are electrically connected through circuit layers and conductive holes.
- Each of the solder balls 26 is aligned with and is attached on a fifth contact pad 2310 .
- the first chip 30 is packed on the first solder mask layer 24 side of the first package substrate 20 by a flip-chip technology.
- the first chip 30 is adhered on the first solder mask layer 24 by a first packaging adhesive 32 .
- the first packaging adhesive 32 is made of high heat dissipation material such as thermally conductive adhesive.
- the first chip 30 includes a plurality of contact pads aligned with the third contact pads 2210 .
- the contact pads of the first chip 30 and the corresponding third contact pads 2210 are electrically interconnected by conductive holes 31 .
- the first chip 30 is received in the thermal conductive frame 130 .
- the first chip 30 and the top plate 131 are interconnected through a heat dissipation bonding sheet 33 for quickly dissipating to the top plate 131 heat created by the first chip 30 .
- the electric conductive pillars 120 are aligned with and electrically connected with the fourth contact pads 2220 through the first solder 60 .
- the second package substrate 40 includes two conductive layers.
- the second package substrate 40 is formed on the interposer 100 and opposite to the first package substrate 20 .
- the second package substrate 40 includes a second base layer 42 , a third circuit layer 43 , a fourth circuit layer 44 , a third solder mask layer 45 , and a fourth solder mask layer 46 .
- the third circuit layer 43 and the fourth circuit layer 44 are formed on the opposite surface of the second base layer 42 .
- the third solder mask layer 45 is formed on the surface of the third circuit layer 43 .
- the fourth solder mask layer 46 is formed on the surface of the fourth circuit layer 44 .
- the second base layer 42 includes a fifth surface 421 and a sixth surface 422 opposite to the fifth surface 421 .
- the third circuit layer 43 is formed on the fifth surface 421 .
- the fourth circuit 44 is formed on the sixth surface 422 .
- the third circuit layer 43 and the fourth circuit layer 44 are electrically connected through a plurality of conductive vias 47 .
- the second base layer 42 is an insulating material or an inner circuit board including circuit layers and insulating layers.
- Portions of the third circuit layer 43 are exposed through the third solder mask layer 45 .
- the exposed portions of the third circuit layer 43 are defined to be a plurality of sixth contact pads 431 .
- a chip fixing area is defined on the third solder mask layer 45 . The chip fixing area is surrounded by the sixth contact pads 431 .
- Portions of the fourth circuit layer 44 are exposed through the fourth solder mask layer 46 .
- the exposed portions of the fourth circuit layer 44 are defined to be a plurality of seventh contact pads 441 .
- the seventh contact pads 441 are aligned with the first contact pads 150 .
- the seventh contact pad 441 and the first contact pad 150 are electrically connected through the second solder 70 .
- the sixth contact pads 431 and the seventh contact pads 441 are electrically connected through the third circuit layer 43 , the fourth circuit layer 44 , and the conductive vias 47 .
- the second chip 50 is attached on the third solder mask layer 45 .
- the second chip 50 is a wire bonding chip.
- the second chip 50 is electrically interconnected with the sixth contact pads 431 .
- the second chip 50 includes a plurality of soldering contacts and a plurality of soldering wires 501 extended from the soldering contacts.
- the soldering wires 501 are aligned with and electrically connected with the sixth contact pads 431 .
- the second chip 50 and the third circuit layer 43 are electrically connected through the soldering wires 501 .
- the second chip 50 is adhered on the chip fixing area of the third solder mask layer 45 through a adhesive layer.
- the soldering wires 501 are soldered with the sixth contact pads 431 .
- the material of the soldering wires 501 is gold.
- the soldering wires 501 , the second chip 50 , the third solder mask layer 45 and the sixth contact pads 431 are all covered by a second packaging adhesive 502 .
- the second packaging adhesive 502 is black gum or other packaging adhesive.
- the interposer 100 and the second package substrate 40 are also covered by the second packaging adhesive 502 if the cross-section area of the first package substrate 20 is greater than that of the interposer 100 and the second package substrate 40 .
- the interposer 100 and the second package substrate 40 are also covered by the second packaging adhesive 502 in this embodiment.
- the first chip 30 is received in the thermal conductive frame 130 , thus heat created by the first chip 30 can be dissipated to the thermal conductive frame 130 and out of the POP structure 10 . Therefore, the disclosed POP structure 10 provides better heat dissipation.
- FIG. 6 shows a POP structure including an interposer of the second embodiment.
- the seventh contact pads 441 are electrically connected with the correspondingacco conductive vias or the first contact pads 250 through the second solder 70 .
- the thermal conductive connector 240 is interconnected between the thermal conductive frame 230 and an electric conductive pillar 220 . Therefore, the heat created by the first chip can be dissipated to the electric conductive pillar 220 , and thence to the first package substrate 20 and the second package substrate 40 through the thermal conductive frame 230 .
- the disclosed POP structure 10 provides improved heat dissipation.
- FIG. 7 shows a POP structure including an interposer according to the third embodiment.
- the top surface 3311 of the top plate 331 and the first surface 311 are coplanar. Therefore, the overall thickness of the POP structure is decreased.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW101139787A TWI531283B (zh) | 2012-10-26 | 2012-10-26 | 連接基板及層疊封裝結構 |
TW101139787 | 2012-10-26 | ||
TW101139787A | 2012-10-26 |
Publications (2)
Publication Number | Publication Date |
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US20140118951A1 US20140118951A1 (en) | 2014-05-01 |
US9271388B2 true US9271388B2 (en) | 2016-02-23 |
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US14/064,202 Active 2034-01-03 US9271388B2 (en) | 2012-10-26 | 2013-10-28 | Interposer and package on package structure |
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US (1) | US9271388B2 (zh) |
TW (1) | TWI531283B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10607971B2 (en) | 2017-10-17 | 2020-03-31 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11570898B2 (en) * | 2019-12-10 | 2023-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Multi-layer 3D foil package |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015211204A (ja) * | 2014-04-30 | 2015-11-24 | イビデン株式会社 | 回路基板及びその製造方法 |
KR101640341B1 (ko) * | 2015-02-04 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
CN107623994A (zh) * | 2016-07-14 | 2018-01-23 | 塞舌尔商元鼎音讯股份有限公司 | 电路板组件及芯片模块 |
CN107978584B (zh) * | 2016-10-21 | 2020-03-31 | 力成科技股份有限公司 | 芯片封装结构及其制造方法 |
US10606327B2 (en) * | 2017-06-16 | 2020-03-31 | Qualcomm Incorporated | Heat reduction using selective insulation and thermal spreading |
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US5495395A (en) * | 1991-09-30 | 1996-02-27 | Matsushita Electric Industrial Co., Ltd. | Face-mounting type module substrate attached to base substrate face to face |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US10607971B2 (en) | 2017-10-17 | 2020-03-31 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11171128B2 (en) | 2017-10-17 | 2021-11-09 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11570898B2 (en) * | 2019-12-10 | 2023-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Multi-layer 3D foil package |
Also Published As
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US20140118951A1 (en) | 2014-05-01 |
TWI531283B (zh) | 2016-04-21 |
TW201417642A (zh) | 2014-05-01 |
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