US9269418B2 - Apparatus and method for controlling refreshing of data in a DRAM - Google Patents

Apparatus and method for controlling refreshing of data in a DRAM Download PDF

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US9269418B2
US9269418B2 US13/366,660 US201213366660A US9269418B2 US 9269418 B2 US9269418 B2 US 9269418B2 US 201213366660 A US201213366660 A US 201213366660A US 9269418 B2 US9269418 B2 US 9269418B2
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refresh
dram
address sequence
addresses
refresh address
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US20130205080A1 (en
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Donald Felton
Emre Özer
Sachin Satish Idgunji
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ARM Ltd
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Priority to JP2013020291A priority patent/JP6184703B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

Definitions

  • the present invention relates to the field of dynamic random access memory (DRAM). More particularly, the invention relates to a technique for controlling refreshing of the data in the DRAM.
  • DRAM dynamic random access memory
  • DRAM Dynamic random access memory
  • a common form of DRAM stores data using capacitors.
  • the capacitor may be placed in either a discharged state or a charged state to represent bit values of zero or one. Since capacitors leak charge over time, the data stored using capacitors will fade unless the capacitor is refreshed periodically.
  • dynamic random access memory and “DRAM” are used to refer to any kind of memory which requires its data to be refreshed periodically to avoid loss of the data (whether the data is stored using capacitors or using another kind of storage element).
  • DRAM is increasingly being used for storage of secure data and secure program code. This is particularly the case in systems in which the DRAM is integrated into the same system-on-chip or package as the processing logic associated with the DRAM.
  • 3D-integrated DRAMs may be used in a system-on-chip having multiple stacked layers.
  • the present technique seeks to improve the security of secure data stored in a DRAM.
  • the present invention provides an apparatus comprising:
  • DRAM dynamic random-access memory
  • refresh control circuitry configured to control said DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of said DRAM
  • a refresh address sequence generator configured to generate a refresh address sequence of addresses identifying the order in which memory locations of said DRAM are refreshed during said refresh cycle
  • said refresh address sequence generator is configured to generate said refresh address sequence with the addresses of at least a portion of said memory locations in a random order which varies from refresh cycle to refresh cycle.
  • DPA differential power analysis
  • DPA is a powerful attack that uses observation of the power consumption of a circuit to at least partially deduce secret information.
  • DPA has been used to extract secret keys from crypto engines.
  • the attacker probes the power supply pin or ground supply pin of a circuit and observes the power consumption of the circuit over a period of time. Since the power consumption will vary slightly depending on the data values being processed, statistical methods can be used to crack the secret information without requiring any knowledge of the algorithm being performed by the circuit.
  • DPA may be used to deduce partial information (such as whether a value contains bit values which are mostly 0 or mostly 1), which allows some potential values of the secret information to be eliminated, increasing the likelihood of success of a brute force attack which attempts each possible value of the secret information to try to crack the actual value of the information. Therefore, DPA could be used to analyse the secure contents of the DRAM.
  • the present technique recognises that the refresh operation of a DRAM provides a security vulnerability which a differential power analysis attacker could exploit. Since the refresh operation is periodic, the DPA attacker can relatively easily work out which parts of the power consumption profile correspond to the refresh operation, by looking for a repeating pattern in the power consumption. Also, since the memory locations of a DRAM is typically refreshed in a predictable sequence, a DPA attacker can easily attribute the power consumed at different times during the refresh cycle to individual DRAM memory locations, to obtain information about the contents of the DRAM.
  • the present technique provides a refresh address sequence generator which generates a refresh address sequence in which the addresses of at least a portion of the memory locations of the DRAM are in a random order which varies from refresh cycle to refresh cycle. This ensures that the order in which the DRAM locations are refreshed is not predictable, and so it is difficult for a DPA attacker to map the power consumed at a particular instant during the refresh cycle to any individual memory location of the DRAM. This improves the security of the data stored within the DRAM.
  • the refresh address sequence generated by the refresh address sequence generator may comprise a sequence of addresses identifying individual memory locations within the DRAM.
  • the refresh address sequence may comprise a sequence of row addresses identifying the order in which the rows of memory locations are refreshed.
  • the memory locations may also be refreshed in units of groups (or clusters) of locations, with the refresh address sequence identifying the order in which the groups (or clusters) are refreshed.
  • the refresh address sequence it is not essential for the refresh address sequence to identify every memory location of the DRAM individually. Randomizing the order in which rows or groups of memory locations are refreshed, with each memory location within the same row or group being refreshed at the same time, is enough to make a DPA attack difficult.
  • the refresh address sequence generator may comprise a sequential address sequence generator which generates an address sequence in a sequential order.
  • the refresh address sequence generator may generate the refresh address sequence from the sequential address sequence by randomising the order of the addresses of at least a portion of the memory locations.
  • a sequential address sequence generator is often already provided in a typical DRAM refresh controller, and so can be reused as a starting point for generating the randomized refresh address sequence.
  • the apparatus may comprise a random number generator for generating at least one random number, and the refresh address sequence generator may randomise the order of the addresses of at least the portion of memory locations in dependence on the at least one random number.
  • the random number generator may be a pseudo random number generator for generating pseudo random numbers based on a seed value.
  • the random number generator While it would be possible to retain the same random number for several refresh cycles before moving to a different random number, it is preferable for the random number generator to change the at least one random number after each refresh cycle. This ensures that the order of the addresses within the refresh address sequence changes for each refresh cycle in an unpredictable manner, and so deters potential DPA attacks.
  • the refresh address sequence generator may also rearrange the bit positions of the addresses according to a second random number generated by the random number generator. This provides further entropy in the refresh address sequence and so makes it harder for an attacker to determine the order of the sequence. By rearranging the bit positions as well as changing the bit values within the addresses, this will disproportionately inconvenience a DPA attacker because it will strongly affect the row and column addressing occurring within the DRAM, causing the attacker to have to take into account a number of extra factors.
  • the bit positions of the addresses can be rearranged in various ways.
  • the addresses may be rotated by a number of bit positions specified by the second random number.
  • a shift register may for example be used to rotate the addresses.
  • a translation matrix may specify a mapping between original bit positions and rearranged bit positions for each possible value of the second random number. For a given value of the second random number, the appropriate entry in the translation matrix can be accessed and used to identify how to map the bits of the original addresses to bits of the refresh addresses.
  • bit position rearrangement may also be used in its own right to randomise the order of the refresh address sequence, without performing the XOR operation.
  • bit position rearrangement since bit position rearrangement has no effect on an address comprising all 0 bit values or all 1 bit values, and has little effect on an address with mostly 0 bit values or mostly 1 bit values, it is preferable to perform the XOR operation which can provide randomization for all addresses within the sequence.
  • the manufacturer of a DRAM typically provides information identifying a recommended refresh period, which represents the maximum recommended period between successive refresh cycles. If a data value is not refreshed within the recommended refresh period, then the data cannot be guaranteed to be accurate.
  • the DRAM would be controlled to perform a refresh cycle at intervals of the recommended refresh period.
  • the present technique recognises that if the ordering of the memory addresses within the refresh address sequence is randomised and refresh cycles are performed at intervals of the recommended refresh period, then it is possible that a particular memory location could be refreshed near the beginning of one refresh cycle and near the end of the next refresh cycle, so that the period between successive refreshes of the same location may be greater than the recommended refresh period. This could lead to data loss.
  • the refresh control circuitry may control the DRAM to periodically perform the refresh cycle at intervals of half the recommended refresh period. This ensures that any particular location is refreshed within the recommended refresh period, even when the order of the refresh sequence is randomised.
  • the apparatus may comprise processing circuitry for performing data processing.
  • the DRAM may be an off-chip memory located on a separate chip to the processing circuitry.
  • the present technique is particularly useful when the processing circuitry and DRAM are integrated on the same system-on-chip or in the same package, since this is when the DRAM is most likely to be used for storing secure data, because the interface between the DRAM and the processing circuitry is less accessible to a potential attacker.
  • the DRAM and processing circuitry may have separate power supply inputs or may share a common power supply input. If the DRAM and processing circuitry have separate power supply inputs then it is preferable that the refresh address sequence is always randomized, since in this case the DRAM's power consumption while performing refresh operations would be distinguishable from the power consumed by the processing circuitry and so a DPA attacker could probe the contents of the DRAM by monitoring the power drawn via the dedicated DRAM power supply input.
  • the processing circuitry and the DRAM share a common power supply input, then it is possible that sometimes the power drawn by the processing circuitry may obscure the power consumption profile of the DRAM. In this case, the refresh sequence need not always be randomized.
  • the refresh address sequence generator may be provided with a normal mode and a random mode.
  • the refresh address sequence may be generated with the addresses in a sequential order, while in the random mode the refresh address sequence may be generated with the addresses of at least a portion of the memory locations in a random order.
  • the refresh cycles may need to be performed more frequently than in the normal mode, for the reasons explained above. Therefore, more power is consumed, and there may be an impact on processing performance because more DRAM bandwidth is required for refresh operations which could delay DRAM accesses from the processor.
  • this allows the user to trade off increased security of the random mode against reduced power consumption and increased performance of the normal mode, depending on the particular requirements of the user.
  • the processing circuitry may have a normal mode and a power saving mode.
  • the power drawn by the processing circuitry may be enough to prevent the DRAM activity being identifiable by DPA.
  • the processing circuitry may consume very little power itself, and so at this time the power drawn via the shared power input is mainly caused by the refresh operation of the DRAM. This means that the DRAM is more vulnerable to DPA attacks while the processing circuitry is in the power saving mode than while the processing circuitry is in the normal mode. Therefore, the refresh address sequence generator may be configured to operate in the normal mode while the processing circuitry is operating in the normal mode, and operate in the random mode while the processing circuitry is operating in the power saving mode.
  • the refresh control circuitry may also detect DRAM accesses to the DRAM by the processing circuitry.
  • the volume of DRAM accesses is relatively high, then the power consumed by the processing circuitry and DRAM as a whole may be influenced by a number of factors other than the refresh operation, and so in this case it may not be necessary to use the random mode.
  • the refresh control circuitry may operate in the normal mode if a detected volume of DRAM accesses is greater than a predetermined threshold and operate in the random mode if the detected volume of DRAM accesses is less than the predetermined threshold.
  • the DRAM may be controlled to perform the refresh cycle twice as frequently when in the random mode as when in the normal mode. This ensures that during the random mode, each DRAM location is refreshed within the recommended refresh period, while during the normal mode power consumption can be reduced and processing performance improved by performing the refresh cycles less frequently.
  • the randomized refresh address sequence may be used for all memory locations of the DRAM. While it is unlikely that all memory locations of the DRAM would be storing secure data, the greater the number of addresses whose order is randomized, the greater the number of possible orderings of the addresses, and so the greater the amount of entropy which a DPA attacker would have to crack in order to identify the contents of the DRAM locations. Therefore, randomizing the order of addresses of locations storing non-secure data as well as locations storing secure data improves the security of the secure data of the DRAM.
  • the randomisation could be applied only to addresses corresponding to a secure portion of the DRAM for storing secure data, secret data, or confidential data.
  • This technique will typically work best if the secure portion comprises a block of 2 N memory locations or memory rows and is aligned to a natural memory address boundary.
  • the refresh control circuitry and refresh address sequence generator may be implemented in different ways.
  • the apparatus may comprise a memory controller for controlling said DRAM, with the memory controller comprising the refresh control circuitry and the refresh address sequence generator.
  • the memory controller controls when and how refreshing of the DRAM is performed.
  • the DRAM may comprise the refresh control circuitry and the refresh address sequence generator.
  • the DRAM since the DRAM controls its own refresh operations, the DRAM appears to other elements of the apparatus (such as a memory controller) as a static random access memory which does not require refreshing.
  • the present invention provides an apparatus comprising:
  • DRAM dynamic random-access memory
  • refresh control means for controlling said DRAM means to periodically perform a refresh cycle for refreshing the data stored in each memory location of said DRAM means
  • refresh address sequence generating means for generating a refresh address sequence of addresses identifying the order in which memory locations of said DRAM means are refreshed during said refresh cycle;
  • said refresh address sequence generating means generates said refresh address sequence with the addresses for at least a portion of said memory locations in a random order which varies from refresh cycle to refresh cycle.
  • the present invention provides a method comprising steps of:
  • DRAM dynamic random-access memory
  • said refresh address sequence is generated with the addresses for at least a portion of said memory locations in a random order which varies from refresh cycle to refresh cycle.
  • FIGS. 1A and 1B illustrate examples of a system-on-chip comprising a DRAM and a refresh controller for controlling refreshing of the DRAM;
  • FIG. 2 illustrates an example of randomising the order of a refresh address sequence
  • FIG. 3 illustrates another example of randomising the order of the refresh address sequence
  • FIG. 4 illustrates an example of a translation matrix for rearranging the bit positions of addresses
  • FIG. 5 illustrates an example showing why refresh cycles are performed at twice the recommended rate when the randomised refresh scheme is used
  • FIG. 6 illustrates an example of a DRAM address space having a non-secure region and a secure region
  • FIG. 7 illustrates examples of an integrated circuit package having DRAM and processing logic which share a power supply input or which have separate power supply inputs;
  • FIG. 8 illustrates a state diagram showing transitions between different modes for performing refreshing of the DRAM.
  • FIG. 9 illustrates a method of controlling refresh operations in a DRAM.
  • FIG. 1A shows an example of a system-on-chip 2 comprising a processor 4 , a dynamic random access memory (DRAM) 6 and a memory controller 8 .
  • the DRAM 6 may comprise any kind of memory which requires periodic refreshing, for example dynamic random access memory which stores data using capacitors.
  • the memory controller 8 is provided for controlling the operation of the DRAM 6 .
  • the memory controller 8 comprises a refresh controller 10 for controlling refreshing of the DRAM 6 , a refresh address sequence generator 12 for generating a refresh address sequence identifying the order in which memory locations of the DRAM are refreshed during a refresh cycle, and a random number generator 14 for generating random numbers.
  • the random number generator 14 may comprise a pseudo random number generator for generating a sequence of pseudo random numbers based on a seed value.
  • FIG. 1B shows an alternative example of a system-on-chip 2 in which the refresh controller 10 , the refresh address sequence address generator 12 and the random number generator 14 are provided within the DRAM package 6 .
  • the DRAM 6 of FIG. 1B acts as a static random access memory since the memory controller 8 does not need to consider the refreshing of the DRAM 6 .
  • FIGS. 1A and 1B show the DRAM 6 integrated into the same system-on-chip 2 as the processor 4 , in other embodiments the DRAM 6 may be an off-chip memory.
  • the refresh controller 10 controls the DRAM 6 to periodically perform a refresh cycle in which each memory location of the DRAM is refreshed.
  • the memory locations of the DRAM may be refreshed a row at a time by reading the values from a row of memory locations, rewriting the row of memory locations with the data which has been read, and then repeating this operation for each subsequent row.
  • the refresh operation may be performed in units of memory locations other than a row.
  • the refresh address sequence generator 12 generates a sequence of addresses identifying in the order in which the memory locations (or rows of memory locations) are refreshed. To deter differential power analysis attacks, the order of at least a portion of the memory addresses is randomised based on a random number generated by the random number generator 14 . This means that the temporal order in which the locations of the DRAM 6 are refreshed is randomised, although the physical location at which each item of data is stored remains the same.
  • FIG. 2 shows an example of how the address sequence can be randomised.
  • the refresh address sequence generator 12 includes a sequential address sequence generator 20 which generates a sequence of addresses in a sequential order.
  • the random number generator 14 generates a random number having the same number of bits as the addresses generated by the sequential address sequence generator 20 .
  • An XOR gate 22 is provided to XOR the addresses generated by the sequential address sequence generator 20 with the random number generated by the random number generator 14 , to generate the refresh address sequence.
  • the XOR operation has the property that when the same N-bit number is XORed with each value in a sequence of 2 N N-bit values comprising each possible permutation of 1s and 0s, the result is a sequence comprising all the original values but in a different order. This means that the XOR operation is useful for randomizing the order of the address sequence.
  • FIG. 2 shows an example using 4-bit addresses.
  • Each address in the sequence is combined with a 4-bit random number 1011 using the bitwise exclusive OR (XOR) operation.
  • XOR bitwise exclusive OR
  • each value within the sequential address sequence also appears in the randomized refresh address sequence, but in a different order dependent on the value of the random number.
  • the random number generator 14 can control the refresh address sequence generator 12 so that the next refresh cycle is performed with a different randomised sequence of addresses. While preferably the random number is changed after each refresh cycle to maximise security, it is possible for the random number to be changed less often, for example after two or more refresh cycles using the same random number.
  • the XOR operation does not change the frequency with which the bit value at each bit position of the address switches states during the refresh cycle. For example, as can be seen in FIG. 2 , the most significant bit still only changes twice per refresh cycle (once from 0 to 1 and once from 1 to 0). This may be able to provide the DPA attacker with additional information which can be used to improve the likelihood of success of a brute force attack. For example, the attacker may be able to determine whether an address is refreshed in the first half or the second half of the address sequence.
  • FIG. 3 shows a shift register 24 which rotates the bits of the addresses generated by XOR gate 22 by a number of bit positions specified by a second random number generated by the random number generator 14 .
  • the address bits which are shifted out of one side of the shift register 24 are inserted into the other side of the shift register 24 .
  • the second random number would preferably be changed after each refresh cycle.
  • the second random number has log 2 (N) bits.
  • the addresses are right rotated by 3 bit positions to generate the refresh address sequence used for the refresh cycle.
  • the frequency with which each bit position switches states is changed so that in this example it is the least significant bit that only changes twice per cycle, with the most significant bit changing state four times per cycle. This makes it harder for an attacker to derive information which could be used to identify the secure contents of the DRAM.
  • FIG. 3 shows the bit rotation being applied after the XOR operation, it will be appreciated that the rotation may also be applied before the XOR operation. Also, while FIG. 3 illustrates a right rotate, a left rotate may also be used.
  • FIG. 4 shows an alternative way of rearranging the positions of the bits within the addresses using a translation matrix 30 , which may be used in place of the shift register 24 shown in FIG. 3 .
  • the translation matrix 30 specifies mappings between bit positions of the input address A and bit positions of an output address M for each possible value of the random number generated by the random number generator 14 . Hence, for a given refresh cycle, the bit positions of each address in the refresh address sequence are rearranged according to the mapping specified by the current random number. A new random number is then selected for the next refresh cycle to provide a different mapping.
  • mappings For example, for a 4-bit address there are 24 different possible mappings, which can be mapped to 24 different values of the random number, for instance using the mapping shown in FIG. 4 .
  • a random number of 7 causes bits 3 , 2 , 1 and 0 of each input address A in the refresh sequence to be mapped to bits 2 , 3 , 0 and 1 of each output address M.
  • the bit position rearrangement using the matrix 30 of FIG. 4 may be performed either before or after applying an XOR operation to the addresses. Rearranging the bit positions of the addresses as shown in FIGS. 3 and 4 will vary the activity on a particular address line between cycles. For example, on a 64-bit address bus, the 63 rd bit line would normally change bit value twice per refresh cycle (once from 0 to 1 and once from 1 to 0), but by rearranging the bit positions of the addresses in a random way, the value of the 63 rd bit line may now toggle anywhere between once per refresh cycle and 2 63 times per cycle depending on the rearrangement applied during that refresh cycle). This will disproportionately inconvenience an attacker because it will strongly affect the row/column addressing occurring inside the DRAM and so cause a number of additional power factors to be taken into account when performing DPA.
  • bit rotation shown in FIG. 3 or the translation matrix shown in FIG. 4 could also be used on its own to perform randomisation of the refresh address sequence, without performing an XOR operation as well. However, this is less preferred, because unlike the XOR operation, the bit position rearrangement operations of FIGS. 3 and 4 can only rearrange the existing bit values of the addresses, and cannot change the actual bit values. This means that, for example, address values 0b0000 . . . or 0b1111 . . . , comprising all 0 or 1 bit values, could not be randomized using the bit position rearrangement alone, which could allow a DPA attacker to determine the contents of the locations having address 0b0000 . . . or 0b1111 . . . . Therefore, it is more secure to use the bit position rearrangement in combination with the XOR operation.
  • the DRAM manufacturer will indicate a recommended refresh period for a given DRAM device which represents the maximum time that a particular memory location should remain unrefreshed. If a memory location is not refreshed within the recommended refresh period, then the data cannot be guaranteed to be accurate and, in a worst case scenario, would be lost. Therefore, it is typical for DRAM refresh cycles to be performed at intervals of the recommended refresh period R, as shown in part A of FIG. 5 . However, if the randomised refresh scheme is used then it is possible that a memory location identified by a particular address X may be refreshed right at the beginning of one refresh cycle and refreshed right at the end of the following refresh cycle. As shown in part A of FIG. 5 , this means that the period between successive refreshes of the same location can be greater than the recommended refresh period R, which could lead to loss of data.
  • the refresh cycles may be performed at intervals of half the recommended refresh period R as shown in part B of FIG. 5 . This ensures that even if an address occurs at the beginning of the refresh sequence in one refresh cycle and at the end of the refresh sequence in the next refresh cycle, the memory location associated with that address is still refreshed within the recommended refresh period.
  • FIG. 6 shows a DRAM address space 50 comprising a non-secure region 54 and a secure region 56 .
  • the secure region 56 is provided specifically for storing secure programs and secure data.
  • the non-secure region 54 is provided for storing other data.
  • the address space 50 may contain multiple secure regions 56 or non-secure regions 54 .
  • the randomised refresh address sequence described above may be applied to either the entire DRAM address space 50 or only to portions of the address space.
  • the randomised scheme may be used just for the secure region 56 , and the addresses of the non-secure region 54 may be refreshed in sequence. By performing randomised refresh only for the secure region 56 , power consumption can be reduced.
  • the addresses of the non-secure region 54 as well as the addresses of the secure region, there are a greater number of possible permutations for ordering the addresses of the refresh address sequence, making it more difficult for the DPA attacker to determine the contents of the secure region 56 .
  • FIG. 7 shows two example implementations of the apparatus in a package rather than a system-on-chip as shown in FIG. 1 .
  • the separate processing logic 4 and DRAM 6 silicon wafers of the integrated circuit package share a common power supply input. This means that if a DPA attacker probes the power via the shared power supply input 70 , then observed power consumption profile will be influenced by contributions of both the logic 4 and the DRAM 6 . This may on some occasions be enough to obscure the profile caused by the DRAM refresh, and so it may not always be necessary to randomize the address sequence. Therefore, the random sequence generation may be used selectively.
  • FIG. 8 shows an example of a state machine having different refresh modes.
  • a normal mode 100 the memory locations are refreshed in a sequential order at the recommended refresh rate X.
  • a random mode 110 at least part of the refresh sequence is randomised using the techniques discussed above, and the refresh cycles are performed at twice the recommended refresh rate (2 ⁇ ).
  • the random mode 120 provides greater security than the normal mode 100 .
  • the normal mode 100 provides reduced power consumption and improved performance relative to the random mode 120 .
  • refresh cycles are performed twice as frequently as in the normal mode 100 , which means that there is less DRAM bandwidth available for the processing circuitry 4 to perform DRAM accesses. This may impact system performance.
  • An adaptive refresh mode 120 may also be provided in which the refresh controller 10 detects the volume of DRAM accesses to the DRAM 6 by the processing logic 4 and varies the refresh rate (i.e. varies whether the normal mode or the random refresh address generation scheme is used) depending on the volume of DRAM accesses.
  • the volume of DRAM accesses may be monitored for example by counting the number of DRAM accesses in a given period of time. If the volume of DRAM accesses is reasonably high (e.g. higher than a predetermined threshold), then the power signature of DRAM refresh scheme may be largely obscured by the DRAM accesses, and so the randomised refresh address sequence generation scheme may not be necessary. In this case, the sequential address sequence can be used as in the normal mode 100 .
  • the refresh controller 10 can switch to generating a randomised refresh address sequence as in the random mode 110 .
  • the adaptive mode 120 can provide a half-way house mode whose security, power consumption, and impact on system performance lies between that of the normal mode 100 and random mode 110 .
  • the state machine shown in FIG. 8 may allow a trade-off between increased security of the random mode 110 and reduced power consumption and improved performance of the adaptive or normal modes 100 , 120 .
  • the refresh controller 10 may switch to the random mode 110 .
  • the refresh controller may switch back to either the active mode 100 or the adaptive mode 120 to save power.
  • the user may select which mode to use depending on current security requirements.
  • the refresh controller 10 waits until the end of the current refresh cycle before switching modes (as switching modes mid-cycle could lead to some locations not being refreshed within the recommended refresh period).
  • Part (b) of FIG. 7 shows another example of an integrated circuit package, in which separate power supply inputs 80 , 82 are provided for the processing logic 4 and DRAM 6 respectively.
  • the power drawn by the DRAM during the refresh cycle is distinguishable from the power consumed by the processing logic 4 irrespective of whether the processing circuitry 4 is active or whether it is accessing the DRAM regularly. Therefore, in such an embodiment it would usually be preferable for the refresh controller 10 to permanently use the random mode (unless for some reason the increased security of the random mode is not considered necessary, in which case the normal mode could be used).
  • the state machine of FIG. 8 may be used with both the system-on-chip implementation of FIG. 1 and the integrated circuit package implementation of FIG. 7 .
  • FIG. 9 shows a method of controlling refresh cycles of a DRAM.
  • the refresh controller 10 may have a refresh timer which is used to identify the times at which refreshing is to be performed. After a refresh cycle is performed, the refresh timer is set to a value representing a given amount of time. The timer then counts down until the specified time has elapsed, at which point the next refresh cycle is performed.
  • the refresh controller 10 detects whether the refresh timer has expired. Once the refresh timer has expired then at step 210 the refresh controller 10 determines whether it is currently in the random mode or the normal mode. If the refresh controller 10 is in the adaptive mode 120 of FIG. 8 then the refresh controller 10 determines based on the observed volume of DRAM activity whether to use the random mode 110 or the normal mode 100 .
  • the refresh controller 10 controls the refresh address sequence generator 12 to generate the refresh address sequence in a sequential order. Hence, no randomisation is applied.
  • the refresh controller 10 controls the DRAM 6 to perform the refresh cycle in the order identified by the generated refresh address sequence.
  • the refresh controller 10 sets the refresh timer to a value X representing the recommended refresh period. Then at step 250 the refresh controller 10 counts down the timer and the method returns to step 200 until the refresh timer expires once more.
  • the refresh controller 10 controls the refresh address sequence generator 12 to generate a refresh address sequence with the order of at least a portion of the addresses of the DRAM randomised based on the random numbers generated by the random number generator 14 .
  • the refresh controller 10 controls DRAM 6 to perform the refresh cycle with the memory locations of the DRAM 6 refreshed in the order identified by the randomised refresh address sequence.
  • the random number generator 14 updates its random numbers so that the next time a randomised refresh address sequence is generated, the addresses will be in a different order.
  • the refresh timer is set to a value of X/2 representing half the recommended refresh period.
  • the method then returns to step 250 where the timer once more counts down until it expires at step 200 .
  • the next refresh will occur after half the recommended period to ensure that even if a particular address is refreshed at the beginning of one cycle and at the end of the next cycle, the address will still be refreshed within the recommended period.
  • the DRAM 6 shown in FIGS. 1A , 1 B and 7 may comprise a single memory unit or multiple physically distinct memory units. If there are multiple memory units, then the refreshing of the memory units may be controlled by a shared refresh controller 10 and refresh address sequence generator 12 , so that a refresh cycle is performed over the whole DRAM address space encompassing multiple memory units. This would tend to increase the amount of randomness in the ordering of the refresh address sequence.
  • each memory unit of the DRAM 6 with its own dedicated refresh controller 10 and refresh address sequence generator 12 , with the refresh cycle of one memory unit managed independently of the refresh cycle of another memory unit.

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