WO2008146393A1 - メモリを試験する方法及び装置並びにｄｒａｍ - Google Patents

メモリを試験する方法及び装置並びにｄｒａｍ Download PDF

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Publication number
WO2008146393A1
WO2008146393A1 PCT/JP2007/061115 JP2007061115W WO2008146393A1 WO 2008146393 A1 WO2008146393 A1 WO 2008146393A1 JP 2007061115 W JP2007061115 W JP 2007061115W WO 2008146393 A1 WO2008146393 A1 WO 2008146393A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory testing
dram
data
testing method
refresh operation
Prior art date
Application number
PCT/JP2007/061115
Other languages
English (en)
French (fr)
Inventor
Rikizo Nakano
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/061115 priority Critical patent/WO2008146393A1/ja
Publication of WO2008146393A1 publication Critical patent/WO2008146393A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

　最も電流を消費するリフレッシュ動作を有効に利用してノイズに弱くマージンの少ない回路やセルを検出可能とするメモリ試験方法。この方法は、一個又は複数個のＤＲＡＭ素子から構成されるメモリを試験するものであり、各ＤＲＡＭについて、ＤＲＡＭにデータ書込みを行うステップと、ＤＲＡＭからデータ読出しを行い、内容を確認するステップと、該データ書込みと該データ読出しとの間において、必要とされるリフレッシュ間隔よりも短い間隔でＤＲＡＭにリフレッシュを実行させるステップと、を含むことを特徴とする。
PCT/JP2007/061115 2007-05-31 2007-05-31 メモリを試験する方法及び装置並びにｄｒａｍ WO2008146393A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061115 WO2008146393A1 (ja) 2007-05-31 2007-05-31 メモリを試験する方法及び装置並びにｄｒａｍ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061115 WO2008146393A1 (ja) 2007-05-31 2007-05-31 メモリを試験する方法及び装置並びにｄｒａｍ

Publications (1)

Publication Number Publication Date
WO2008146393A1 true WO2008146393A1 (ja) 2008-12-04

Family

ID=40074675

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/061115 WO2008146393A1 (ja) 2007-05-31 2007-05-31 メモリを試験する方法及び装置並びにｄｒａｍ

Country Status (1)

Country Link
WO (1) WO2008146393A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013161482A (ja) * 2012-02-06 2013-08-19 Arm Ltd Ｄｒａｍ内のデータのリフレッシュを制御するための装置および方法
CN116259351A (zh) * 2023-05-12 2023-06-13 粤芯半导体技术股份有限公司 一种存储器的测试方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09312100A (ja) * 1996-05-22 1997-12-02 Nec Corp 半導体記憶装置
JPH11213659A (ja) * 1998-01-27 1999-08-06 Internatl Business Mach Corp <Ibm> リフレッシュ間隔制御装置及び方法、並びにコンピュータ
JP2003178598A (ja) * 2001-12-11 2003-06-27 Nec Electronics Corp 半導体記憶装置およびそのテスト方法並びにテスト回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09312100A (ja) * 1996-05-22 1997-12-02 Nec Corp 半導体記憶装置
JPH11213659A (ja) * 1998-01-27 1999-08-06 Internatl Business Mach Corp <Ibm> リフレッシュ間隔制御装置及び方法、並びにコンピュータ
JP2003178598A (ja) * 2001-12-11 2003-06-27 Nec Electronics Corp 半導体記憶装置およびそのテスト方法並びにテスト回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013161482A (ja) * 2012-02-06 2013-08-19 Arm Ltd Ｄｒａｍ内のデータのリフレッシュを制御するための装置および方法
CN116259351A (zh) * 2023-05-12 2023-06-13 粤芯半导体技术股份有限公司 一种存储器的测试方法
CN116259351B (zh) * 2023-05-12 2023-07-07 粤芯半导体技术股份有限公司 一种存储器的测试方法

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