US8799531B2 - Data transferring apparatus and control method thereof - Google Patents

Data transferring apparatus and control method thereof Download PDF

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US8799531B2
US8799531B2 US13/271,834 US201113271834A US8799531B2 US 8799531 B2 US8799531 B2 US 8799531B2 US 201113271834 A US201113271834 A US 201113271834A US 8799531 B2 US8799531 B2 US 8799531B2
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host
request
resume
configuration data
suspend
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US20120124252A1 (en
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Kazuya Kayama
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to data transferring apparatuses that control multiple endpoint devices, and to control methods for such apparatuses.
  • a data transferring system in which a host and multiple endpoint devices are connected via a switch, a hub, or the like, and which carries out the point-to-point transfer of image data, commands, and so on, is known.
  • PCI-Express which has in recent years been put into practical application as a high-speed serial transfer technique
  • a host and an endpoint device are connected point-to-point (that is, are connected one-to-one).
  • a switch that is compliant with PCI-Express is used when connecting multiple endpoint devices to the host in order to carry out point-to-point communication (see Japanese Patent Laid-Open No. 2005-148896).
  • the transition has followed the procedure described hereinafter in a data transferring system that is configured of a host, a switch, and endpoints, when transiting the link of an endpoint device to an L 2 state (an example of a suspend state as defined by PCI-Express; details will be given later).
  • the host sends a message to the switch for transiting the endpoint device and a corresponding port within the switch to the L 2 state.
  • the message sent in 1 is broadcasted by the switch, and is sent to all of the endpoint devices that are under that switch.
  • Each endpoint device that has received the stated message sends, to the switch, a message indicating acceptance of the suspension.
  • the switch Upon receiving a message indicating acceptance of the suspension from all of the endpoint devices, the switch sends a message indicating acceptance of the suspension to the host.
  • the host transits all of the links to the endpoint devices to the L 2 state.
  • a “state in which a link is established” refers to a state in which a connection that enables data communication is maintained.
  • USB 3.0 With USB 3.0, the host can transit a specific endpoint device connected to the hub from the U 0 state to the U 3 state through software control.
  • the link between the host and the endpoint device is restored from the initial state of the link in accordance with a power state diagram prepared for USB 3.0.
  • a data transferring apparatus that is capable of connecting to at least one device and that transfers a request from a host to the device, the apparatus comprising: a control unit that, in response to receiving a suspend request for suspending at least one of the devices from the host, obtains configuration data of the target device for suspension indicated by the suspend request from the device; and a holding unit that holds the configuration data obtained by the control unit.
  • a data transferring apparatus that is capable of connecting to at least one device and that transfers a request from a host to the device, the apparatus comprising: a control unit that, in response to receiving a suspend request for suspending at least one of the devices from the host, obtains configuration data used in data communication from a port to which the target device for suspension indicated by the suspend request is connected; and a holding unit that holds the configuration data obtained by the control unit.
  • a data transferring apparatus that is capable of connecting to at least one device and that transfers a request from a host to the device, the apparatus comprising: a receiving unit that receives, from the host, a suspend request specifying one of the devices as a target device for suspension or a resume request specifying one of the devices as a target device for resume; an obtainment unit that, in the case where the suspend request has been received by the receiving unit, obtains configuration data from the target device for suspension specified by the suspend request, and stores the configuration data in a holding unit; and a control unit that, in the case where the suspend request has been received by the receiving unit, transits the target device for suspension to the suspend state after the obtainment unit has stored the configuration data in the holding unit, and that, in the case where the resume request has been received by the receiving unit, resumes the target device for resume from the suspend state by reading the configuration data of the target device for resume stored in the holding unit and setting the configuration data in the target device for resume.
  • a control method for a data transferring apparatus that is capable of connecting to at least one device and that transfers a request from a host to the device, the method comprising: receiving, from the host, a suspend request specifying one of the devices as a target device for suspension or a resume request specifying one of the devices as a target device for resume; obtaining, in the case where the suspend request has been received in the receiving, configuration data from the target device for suspension specified by the suspend request, and storing the configuration data in a holding unit; and in the case where the suspend request has been received in the receiving, transiting the target device for suspension to the suspend state after the configuration data has been stored in the holding unit in the obtaining, and, in the case where the resume request has been received in the receiving, resuming the target device for resume from the suspend state by reading the configuration data of the target device for resume stored in the holding unit and setting the configuration data in the target device for resume.
  • FIG. 1 is a diagram illustrating a data transferring system according to a first embodiment.
  • FIG. 2 is a state transition diagram that follows an LTSSM.
  • FIG. 3 is a flowchart illustrating operations of a power control unit when a link is suspended according to the first embodiment.
  • FIG. 4 is a flowchart illustrating operations of a power control unit when resuming a link according to the first embodiment.
  • FIG. 5 is a diagram illustrating a data transferring system according to a second embodiment.
  • FIG. 7 is a flowchart illustrating operations of a power control unit when resuming a link according to the second embodiment.
  • FIG. 8 is a diagram illustrating a data transferring system according to a third embodiment.
  • FIG. 9 is a link state transition diagram for USB 3.0.
  • FIG. 10 is a diagram illustrating operations performed by a hub when a link is suspended according to the third embodiment.
  • FIG. 11 is a diagram illustrating operations performed by a hub when resuming a link according to the third embodiment.
  • FIG. 1 is a block diagram illustrating a data transferring system 24 according to a first embodiment.
  • a central processing unit 1 (called a “CPU 1 ” hereinafter; this may instead be an MPU), which serves as a host, carries out the overall control of a system that includes multiple devices.
  • a root complex 2 is located in the uppermost position in an IO layer, and connects the CPU 1 , a graphics board 3 , a memory 4 , sub-systems (not shown), and so on to the IO.
  • the root complex 2 includes a downstream port 18 , and the root complex 2 and a switch 5 are connected to each other via the downstream port 18 and an upstream port 19 .
  • the switch 5 is provided as a switching unit for connecting the host one-to-one to multiple devices.
  • the switch 5 is capable of connecting multiple endpoint devices (devices) and the host (via the root complex), and is used to extend the PCI-Express (denoted as “PCIe” hereinafter) ports.
  • PCIe PCI-Express
  • the data transferring system 24 may be implemented upon a single board. However, in the case where a printer, an image processing apparatus, or the like connected via PCIe are to be handled as endpoint devices, the data transferring system 24 is realized through multiple devices.
  • the switch 5 includes a power control unit 6 , and the power control unit 6 reduces the load on the CPU 1 when carrying out a resume process for multiple endpoint devices 9 , 10 , and 11 connected to the switch 5 . Furthermore, the control carried out by the power control unit 6 is simple, and thus the scale of the circuit can be reduced, which in turn reduces the power consumed by the power control unit 6 . Specific operations carried out by the power control unit 6 will be described later.
  • a power control register 7 is a register that is set by the CPU 1 ; a suspend instruction (a suspend request) and a resume instruction (a resume request) for the endpoint devices are written into this power control register 7 .
  • a status holding unit 8 includes a register or a memory, and is used to store the following:
  • configuration data (communication parameters) for downstream ports 15 , 16 , and 17 of the switch 5 ;
  • an address conversion table used by the switch 5 to convert requests issued by the host to devices in a first address space, into a second address space; and so on. It is sufficient for the status holding unit 8 to have a size of approximately 4 KByte.
  • Printers, cameras, and so on can be given as examples of the endpoint devices 9 , 10 , and 11 .
  • the configuration data (communication parameters, operation parameters, and so on, mentioned later), the stated address conversion table, and so on saved by the power control unit 6 are stored in an EEP ROM 40 (or the status holding unit 8 , if the unit has an uninterruptible power source) immediately after a reset.
  • the address conversion table handles the first address space as a PCI address space, and handles the second address space as a local address space.
  • the address conversion table is mapping information for mapping data (issued requests) written in the PCI address space to the local address space (a device address space).
  • the endpoint devices 9 , 10 , and 11 include upstream ports 12 , 13 , and 14 , respectively, for communicating with the respective downstream ports 15 , 16 , and 17 of the switch 5 .
  • Communication paths 21 , 22 , and 23 for connecting the downstream ports 15 , 16 , and 17 to the upstream ports 12 , 13 , and 14 , respectively, are PCIe connections based on PCI-Express.
  • FIG. 2 is a state diagram for the LTSSM (Link Training Status State Machines) of the PCI-Express connections 21 through 23 , respectively (referred to as “PCIe connections” hereinafter), according to the present embodiment (and more specifically, is a state diagram indicating the ports related to the connections).
  • LTSSM Link Training Status State Machines
  • PCIe connections PCIe connections
  • L 0 , L 0 s, L 1 , and L 2 link power states are provided, and based on the link state, a device transits to a power-saving state automatically without the involvement of software.
  • L 0 indicates a full-on communication state, but in the case where there are no packets that are to be sent over that link, the device transits to the L 0 s, L 1 , or L 2 state automatically.
  • FIG. 2 indicates content that is defined by PCI-Express (although some states are not shown in the drawing). Furthermore, in the present embodiment, the PCIe connections 21 through 23 can each take on a different state. The various states shown in FIG. 2 will be described hereinafter.
  • a link After a reset, a link starts from s 0 .
  • a remote-side receiver In the DETECT state in s 0 , a remote-side receiver is detected, and the state transits to the next state s 1 after the detection.
  • the POLLING state in s 1 bit synchronization and symbol synchronization are established, the lane polarity is detected, and the data rate is set. The state then transits to s 2 .
  • the CONFIGURATION state in s 2 a training sequence is sent/received, the lane configuration of the link is established, and lane-to-lane deskew and scramble settings are carried out.
  • the CONFIGURATION state Once the CONFIGURATION state has ended normally, the state transits to s 3 .
  • the L 0 state in s 3 is the normal state, and when this state is reached, the initialization of the physical layer ends.
  • the states s 4 (LOS), s 5 (L 1 ), and s 6 (L 2 ) transited to from s 3 are low-power-consumption states, in which data communication is not carried out.
  • the link is in an electrically idle state, but unlike s 3 , the clock supply to the port is stopped.
  • the power consumption is suppressed to be approximately 30 to 40% of s 3 , and thus it requires approximately 100 ns to several as to be restored to s 3 .
  • the link In the L 1 state in s 5 , the link is in an electrically idle state, but the clock supply to the port involved in the PCIe connection is stopped. In s 5 , the power consumption is suppressed to be approximately 10 to 20% of s 3 , and thus it requires approximately several ms to 10 ms to be restored to s 3 .
  • the L 2 state in s 6 transmitter and receiver functions, as well as the clock supply, are stopped, the main power is cut off, and only backup power is supplied. For this reason, although an extremely low amount of power is consumed compared to S 3 , it is necessary to establish a link from the initial state (S 0 ) when restoring from s 6 to s 3 , and thus the restoration takes a long time.
  • the link is restored from the states s 3 through s 5 .
  • a training sequence is executed using the link speed, link number, lane number, and so on of the already-established link, and bit synchronization, symbol synchronization, lane-to-lane deskew, and so on are executed.
  • the LOOPBACK state in s 8 testing, detection of problems, and so on are carried out.
  • the state transits to the HOT RESET state in s 9 in the case where a HOT RESET has been instructed from an upper layer, in the case where a HOT RESET has been instructed during link control in a training sequence, and so on.
  • the state transits to the DISABLED state in s 10 in the case where, when the link has been set to be unusable, and instruction to stop has been made from an upper layer, the link is set to be unusable in a training sequence, and so on.
  • the switch 5 includes the one upstream port 19 and the three downstream ports 15 , 16 , and 17 , and the CPU 1 is connected to the endpoint devices 9 , 10 , and 11 .
  • a switch is typically used as a PCI-PCI bridge by setting the header type of the upstream port of the switch to “1”.
  • the PCI address space is formed between the CPU 1 and the switch 5
  • the local address space is formed between the switch 5 and the endpoint devices 9 , 10 , and 11 , and thus the address spaces can be handled in an independent manner.
  • the space between the CPU 1 and the root complex 2 is a CPU address space and the space between the root complex 2 (the downstream port 18 ) and the switch 5 is a PCI address space, the CPU address space will not be discussed in the present embodiment.
  • the power control unit 6 of the switch 5 maps the data written by the CPU 1 into addresses in the PCI space (PCI-based addresses) to the local space using an address table held in the EEPROM 40 .
  • the PCI address space is given as an example of a predetermined bus address space formed between a host device (the CPU 1 or the like) and the switch 5 , it should be noted that the present embodiment can also be applied when using another address space.
  • Register data for suspending the endpoint device 9 that is the target for suspension (that is, a suspend instruction indicating the endpoint device 9 as the target for suspension) is written by the CPU 1 into a memory space in the PCI address space of the switch 5 , via the communication path 20 .
  • This register data is mapped from the memory space in the PCI address space to a memory space in the local address space by the power control unit 6 , and is stored in the power control register 7 in the local space. In this manner, the switch 5 transfers the request from the CPU 1 to the device.
  • the communication parameters of the downstream ports 15 , 16 , and 17 , the operation parameters of the endpoint devices 9 , 10 , and 11 , and so on are stored in the EEPROM 40 .
  • the power control unit 6 can transfer data between the PCI address space and the local address space by setting communication parameters in the downstream ports 15 , 16 , and 17 . Through this, data can be transferred between the CPU 1 and the endpoint devices 9 , 10 , and 11 . Note that the loading of data by the power control unit 6 from the EEPROM 40 to the ports used in the PCIe connections 21 through 23 and to the endpoint devices is carried out immediately after a reset; the details of this will be given later.
  • the power control unit 6 Upon reading the register data instructing the endpoint device 9 to be put into suspend from the power control register 7 (the suspend instruction indicating the endpoint device 9 as the target for suspension) (step S 301 ), the power control unit 6 commences operations for suspending the endpoint device 9 . First, the power control unit 6 reads and obtains the operation parameters of the endpoint device 9 , and stores those parameters in the status holding unit 8 (step S 302 ). These operation parameters refer to values that specify the various operations of the endpoint device 9 , and are stored in a control register or the like within the endpoint device 9 . The details of the operation parameters differ depending on the type of endpoint device 9 .
  • device-unique information such as whether or not a dual-sided printing unit is provided, the printing speed (ppm), and so on, information indicating the operational mode of the printer when transiting to the suspend state (2-in-1 printing, password-locked, or the like by default), or the like is held as the operation parameters.
  • the power control unit 6 also stores communication parameters indicating the configuration of the PCIe connection 21 in the status holding unit 8 .
  • Information indicating settings determined in S 0 to S 2 in FIG. 2 when establishing the PCIe connection 21 is included in the communication parameters.
  • the power control unit 6 may obtain the communication parameters from the downstream port 15 .
  • the operation parameters of the endpoint device 9 may be obtained any time before the endpoint device 9 is suspended.
  • the communication parameters of the downstream port 15 may be obtained any time before the PCIe connection 21 is cut off.
  • a message prompting the device to be suspended (PME_Turn_Off: TLP) is sent to the endpoint device 9 via the communication path 21 (step S 303 ).
  • the power control unit 6 receives, from the endpoint device 9 , a message (PME_TO_Ack: TLP) accepting the suspension (step S 304 ).
  • the power control unit 6 receives, from the endpoint device 9 , a message (PM_Enter_L 23 ) indicating that preparations to enter suspension have been completed (step S 305 ).
  • the power control unit 6 sends, to the CPU 1 , a signal requesting the supply of a reference clock and the power to the endpoint device 9 to be cut off (step S 306 ).
  • an interrupt signal is preferable for this type of request signal.
  • the interrupt signal generated by the power control unit 6 is transferred from the local address space, through the PCI address space, and to the CPU 1 .
  • the CPU 1 stops the supply of the reference clock and the power to the endpoint device 9 . Through this, the link of the endpoint device 9 is transited to the L 2 state.
  • the power control unit 6 issues a request to the CPU 1 to start the supply of the reference clock and the power to the endpoint device 9 , which is the target for resume (step S 402 ). It is preferable to use, for example, an interrupt signal for this request.
  • the power control unit 6 carries out the resume process for the link between the CPU 1 and endpoint device 9 , and waits for the link to be restored to the normal state (L 0 ) (step S 403 ).
  • the link used in PCIe data transfer can be resumed by the power control unit 6 setting the communication parameters in the downstream port 15 and upstream port 12 .
  • the processes indicated in S 0 to S 2 of FIG. 2 may be carried out as the link resume process.
  • the power control unit 6 reads the operation parameters of the endpoint device 9 that are stored in the status holding unit 8 (or the EEPROM 40 ) (step S 404 ). Then, the power control unit 6 sends the operation parameters read in step S 404 to the endpoint device 9 (step S 405 ).
  • the configuration data the operation parameters and communication parameters
  • the settings of the endpoint device 9 can be restored to the same state those settings were in before the device was suspended; thus the endpoint device 9 is resumed from the L 2 suspend state.
  • the present embodiment describes the endpoint device 9 as the device that is to be suspended and resumed, it goes without saying that the power control unit 6 can carry out the same control, and that the same effects can be achieved, when the target is the endpoint device 10 or 11 .
  • the resume process for the PCIe connection 20 link may be simplified by the power control unit 6 saving the communication parameters of the PCIe connection 20 in the status holding unit 8 (or the EEPROM 40 ).
  • a process for re-creating the address conversion table can be eliminated by the power control unit 6 loading, into the switch 5 , the address conversion table saved in the status holding unit 8 (or the EEPROM 40 ).
  • the status holding unit 8 of the power control unit 6 in the switch 5 may be configured by the EEPROM 40 , or, if power from a backup power source is supplied in a stable manner to the power control unit 6 , the EEPROM 40 need not be provided.
  • the configuration data may be saved in a predetermined storage device that is accessible by the power control unit 6 and that is not volatile.
  • FIG. 5 is a block diagram illustrating a data transferring system according to a second embodiment.
  • blocks that have the same functions as those in FIG. 1 are given the same reference numerals. Furthermore, descriptions will be omitted for blocks that carry out the same operations as those described in the first embodiment.
  • the switch 5 forms a virtual bus bridge, and operates so as to be treated as a bus bridge by a host device.
  • the upstream port 19 of the switch 5 connects to the downstream ports 15 through 17 via a virtual PCI-PCI bridge.
  • the header type of the upstream port 19 of the switch 5 is set to “1”, and the switch 5 is used as a bus bridge (a PCI-PCI bridge).
  • the CPU 1 communicates with the endpoint devices 9 , 10 , and 11 without traversing address spaces from the PCI address space to the local address space as in the first embodiment.
  • the CPU 1 can carry out the configuration settings for the downstream port of the switch 5 and the endpoint devices. Accordingly, the EEPROM 40 , which is necessary in the first embodiment, can be omitted from the present embodiment.
  • a circuit for mapping the PCI address space to the local address space is necessary within the switch 5 , but such is not necessary with the switch 5 according to the second embodiment.
  • the configuration of the second embodiment is more advantageous than the data transferring system according to the first embodiment in terms of reduced power consumption and reduced costs.
  • the switch 5 according to the second embodiment includes the power control unit 6 , the power control register 7 , and the status holding unit 8 .
  • the circuit that corresponds to the power control unit 6 has a simpler configuration than in the first embodiment.
  • operations performed by the power control unit 6 according to the second embodiment will be described using the endpoint device 9 as an example of a target for suspension and a target for resume.
  • operations performed by the power control unit 6 when a command for transiting the endpoint device 9 from the normal state to the suspend state has come from the system will be described.
  • FIG. 6 illustrates a flow of operations performed by the power control unit 6 when transiting the endpoint device 9 , which is the target for suspension, from the normal state to the suspend state.
  • the operations will be described in detail using FIGS. 5 and 6 .
  • data instructing the endpoint device 9 to be suspended are written by the CPU 1 into the power control register 7 of the switch 5 .
  • the power control unit 6 reads the power control register 7 (step S 601 ), and when there is a suspend instruction specifying the endpoint device 9 as the target for suspension, the suspension process from step S 602 is commenced.
  • the power control unit 6 reads and obtains the operation parameters of the endpoint device 9 , and stores those parameters in the status holding unit 8 (step S 602 ).
  • the power control unit 6 then sends, to the endpoint device 9 that is the target for suspension, a message (PME_Turn_Off: TLP) prompting the suspension, from the downstream port 15 and through the communication path 21 (step S 603 ).
  • a message PME_Turn_Off: TLP
  • the power control unit 6 receives that message (step S 604 ). Furthermore, when the endpoint device 9 has completed preparations to enter suspension, a message (PM_Enter_L23:DLLP) communicating that the preparations to enter suspension have been completed is sent from the endpoint device 9 to the downstream port 15 . The power control unit 6 then receives the message (PM_Enter_L23:DLLP) indicating the completion of preparations for suspension from the endpoint device 9 (step S 605 ).
  • the power control unit 6 sends, to the CPU 1 , a signal (for example, an interrupt signal) requesting the supply of a reference clock and the power to the endpoint device 9 to be cut off (step S 606 ). Having received the interrupt signal, the CPU 1 stops the supply of power and the reference clock to the endpoint device 9 . As a result, the link state between the endpoint device 9 , to which the supply of power and the reference clock has been cut off, and the switch 5 , is transited to the L 2 state (suspend).
  • a signal for example, an interrupt signal
  • FIG. 7 illustrates a flow of operations performed by the power control unit 6 when resuming an endpoint device that is in the suspend state.
  • register data instructing the endpoint device 9 to be resumed is written by the CPU 1 into the power control register 7 of the switch 5 .
  • the power control unit 6 reads the register data from the power control register 7 (step S 701 ), and when a resume instruction specifying the endpoint device 9 as the target for resume has been made, the resume process for the link with the endpoint device 9 , which is the target for resume, is commenced.
  • the power control unit 6 makes a request to the CPU 1 to start the supply of the reference clock and the power to the endpoint device 9 , which is the target for resume (step S 702 ). It is preferable to use, for example, an interrupt signal for this request.
  • FIG. 8 is a block diagram illustrating a data transferring system according to a third embodiment.
  • a host 25 provides processing capabilities, services, and so on to devices 26 , 27 , and 28 (these correspond to endpoint devices) that are present within a data transferring system 39 according to the third embodiment.
  • the devices 26 , 27 , and 28 are devices, computers, or the like to which the processing capabilities, services, and so on are provided by the host 25 .
  • a hub 41 serves to extend ports, and connects the host 25 to the devices 26 , 27 , and 28 .
  • the hub 41 according to the third embodiment includes the power control unit 6 , which further carries out a process for resuming power to the devices 26 , 27 , and 28 , and the status holding unit 8 .
  • the numbers 35 , 36 , 37 , and 38 shown in FIG. 8 indicate communication paths based on the USB 3.0 standard.
  • FIG. 9 is a state diagram illustrating link transitions occurring during USB 3.0 power management.
  • link power states U 0 , U 1 , U 2 , and U 3 are provided. Each of these power states will be described briefly hereinafter.
  • the U 0 state is a state in which a link is active.
  • the U 1 state is a state in which a link is idle and transmission and reception circuits are stopped. Restoration from the U 1 state to the U 0 state takes an amount of time on the order of ⁇ s.
  • the U 2 state is a state in which a clock generator such as a PLL is stopped, on top of the link idle state in the U 1 state.
  • the U 3 state is a suspend state, in which some of the power to the device is turned off. Resume from the U 3 state to the U 0 state takes an amount of time on the order of ms.
  • the hub 41 according to the third embodiment includes a single upstream port that is connected to the host 25 and three downstream ports 29 , 30 , and 31 that are connected to the devices 26 , 27 , and 28 , and thus connects the host 25 to the three devices 26 , 27 , and 28 .
  • the host 25 and the hub 41 are connected by a communication path 38 provided between the root port of the host 25 and the upstream port of the hub 41 .
  • upstream ports 32 , 33 , and 34 of the devices 26 , 27 , and 28 are connected to the downstream ports 29 , 30 , and 31 of the hub 41 by the communication paths 35 , 36 , and 37 , respectively.
  • the power control unit 6 and the status holding unit 8 are provided in the hub 41 , and the power control unit 6 is caused to carry out configuration settings when restoring the power of the devices 26 , 27 , and 28 .
  • the hub 41 transfers, to the device 26 , a request to transit the device 26 to the U 3 state (that is, a U3entryREQUEST) that has been sent from the host 25 (step S 1001 ).
  • This is a suspend instruction indicating the device 26 as the target for suspension.
  • the power control unit 6 of the hub 41 accesses the device 26 , reads and obtains the configuration data of the device 26 (that is, the operation parameters and communication parameters), and stores that data in the status holding unit 8 (step S 1002 ).
  • the configuration data of the device 26 that is the target of suspension may be stored in the status holding unit 8 at any time as long as it is before the device 26 is suspended.
  • the hub 41 transfers, to the device 26 , an LGO_U 3 Link command (indicating a request to transit the link from the U 0 state to the U 3 state) sent from the host 25 (step S 1003 ). Then, the hub 41 transfers, to the host 25 , a LAU link command (indicating acceptance of the request to transit the link state) sent from the device 26 that is the target of suspension (step S 1004 ). After this, the link of the device 26 is transmitted to the U 3 state (suspend).
  • FIG. 11 illustrates a flow of operations in a resume process performed by the hub 41 .
  • the restoration from the U 3 state to the U 0 state is also controlled by system software.
  • the resume process is carried out by setting PORT_LINK_STATE in the root port of the host 25 .
  • the processes described hereinafter are executed when the PORT_LINK_STATE is set in the root port.
  • the hub 41 Upon receiving a U 3 state end request (called a “resume command” hereinafter) for the device 26 that has been sent from the host 25 (step S 1101 ), the hub 41 executes the resume process described hereinafter.
  • This resume command is a resume instruction indicating the device 26 as the target for resume.
  • the hub 41 remotely turns on the power of the device 26 , which is the target for resume, using a network configuration (not shown) (step S 1102 ). After the power of the device 26 has been turned on, the link between the device 26 and the host 25 is restored to the normal state according to the states illustrated in FIG. 9 .
  • the power control unit 6 reads the configuration data (that is, the operation parameters and communication parameters) stored in the status holding unit 8 (step S 1104 ), and sends that data to the device 26 (step S 1105 ).
  • the settings of the device 26 can be returned to the same state as before the device 26 was suspended by setting the configuration data (the operation parameters and communication parameters) in the device 26 .
  • the communication parameters may be obtained from the downstream port 29 , as in the first embodiment.
  • the setting is carried out in the same manner as in the first embodiment.
  • the state transitions are carried out more smoothly if the communication parameters are saved after first saving the operation parameters when the device is transited to the suspend state and the operation parameters are set after first setting the communication parameters and restoring the link when resuming the device.
  • the present invention can also be applied in a system that includes switches, hubs, or the like in multiple across a layered structure. In such a case, the present invention may be applied in the switch (hub) that is uppermost among the switches (hubs) involved in the transfer of data to the device whose configuration data is to be saved.
  • a switch (or a hub) that connects a single host to multiple devices executes suspension processes or resume processes for the devices more on the device side than past hosts. Accordingly, it is possible to increase the speed of the suspension processes and resume processes, and it is also possible to reduce the load on the host.
  • aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiments, and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiments.
  • the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (e.g., computer-readable storage medium).

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8700819B2 (en) * 2011-03-09 2014-04-15 Apple Inc. Host device suspending communication link to client device based on client device notification
JP5936498B2 (ja) * 2012-01-16 2016-06-22 ルネサスエレクトロニクス株式会社 Ｕｓｂ３．０デバイス及び制御方法
JP6007642B2 (ja) * 2012-01-26 2016-10-12 株式会社リコー 情報処理装置、省電力制御方法、省電力制御プログラム
US9280507B2 (en) 2012-10-22 2016-03-08 Intel Corporation High performance interconnect physical layer
KR101691756B1 (ko) * 2012-10-22 2016-12-30 인텔 코포레이션 코히어런스 프로토콜 테이블
US10209911B2 (en) 2013-09-27 2019-02-19 Intel Corporation Techniques enabling low power states for a communications port
JP6286551B2 (ja) * 2014-01-16 2018-02-28 インテル・コーポレーション 処理要素構成のための装置、デバイス構成のための装置および方法、高速デバイス構成のための装置、プログラム、並びに、非一時的コンピュータ可読ストレージ媒体
US9830289B2 (en) 2014-09-16 2017-11-28 Apple Inc. Methods and apparatus for aggregating packet transfer over a virtual bus interface
US10078361B2 (en) 2014-10-08 2018-09-18 Apple Inc. Methods and apparatus for running and booting an inter-processor communication link between independently operable processors
US10042794B2 (en) 2015-06-12 2018-08-07 Apple Inc. Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link
US10085214B2 (en) 2016-01-27 2018-09-25 Apple Inc. Apparatus and methods for wake-limiting with an inter-device communication link
US10572390B2 (en) 2016-02-29 2020-02-25 Apple Inc. Methods and apparatus for loading firmware on demand
JP6843508B2 (ja) * 2016-03-01 2021-03-17 キヤノン株式会社 情報処理装置及び情報処理装置の制御方法
JP6252614B2 (ja) * 2016-03-18 2017-12-27 株式会社リコー 情報処理装置、情報処理システム、情報処理方法、プログラム及び記憶媒体
US10191859B2 (en) 2016-03-31 2019-01-29 Apple Inc. Memory access protection apparatus and methods for memory mapped access between independently operable processors
US10775871B2 (en) 2016-11-10 2020-09-15 Apple Inc. Methods and apparatus for providing individualized power control for peripheral sub-systems
US10551902B2 (en) 2016-11-10 2020-02-04 Apple Inc. Methods and apparatus for providing access to peripheral sub-system registers
US10346226B2 (en) 2017-08-07 2019-07-09 Time Warner Cable Enterprises Llc Methods and apparatus for transmitting time sensitive data over a tunneled bus interface
US10331612B1 (en) 2018-01-09 2019-06-25 Apple Inc. Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors
US11792307B2 (en) 2018-03-28 2023-10-17 Apple Inc. Methods and apparatus for single entity buffer pool management
US20190317893A1 (en) * 2018-04-13 2019-10-17 Hewlett Packard Enterprise Development Lp Addressable control space for integrated circuit hardware blocks
US11381514B2 (en) 2018-05-07 2022-07-05 Apple Inc. Methods and apparatus for early delivery of data link layer packets
US10430352B1 (en) 2018-05-18 2019-10-01 Apple Inc. Methods and apparatus for reduced overhead data transfer with a shared ring buffer
US10585699B2 (en) 2018-07-30 2020-03-10 Apple Inc. Methods and apparatus for verifying completion of groups of data transactions between processors
US10719376B2 (en) 2018-08-24 2020-07-21 Apple Inc. Methods and apparatus for multiplexing data flows via a single data structure
US10846224B2 (en) 2018-08-24 2020-11-24 Apple Inc. Methods and apparatus for control of a jointly shared memory-mapped region
US10838450B2 (en) 2018-09-28 2020-11-17 Apple Inc. Methods and apparatus for synchronization of time between independently operable processors
US10789110B2 (en) 2018-09-28 2020-09-29 Apple Inc. Methods and apparatus for correcting out-of-order data transactions between processors
US11216061B2 (en) * 2019-07-25 2022-01-04 Arm Limited Methods and apparatus for interfacing between power domains
US11558348B2 (en) 2019-09-26 2023-01-17 Apple Inc. Methods and apparatus for emerging use case support in user space networking
US11829303B2 (en) 2019-09-26 2023-11-28 Apple Inc. Methods and apparatus for device driver operation in non-kernel space
CN112189191A (zh) * 2019-09-27 2021-01-05 深圳市大疆创新科技有限公司 基于PCIe总线的数据处理方法及装置、可移动平台
US11558296B2 (en) * 2020-09-18 2023-01-17 Serialtek, Llc Transaction analyzer for peripheral bus traffic
US11606302B2 (en) 2020-06-12 2023-03-14 Apple Inc. Methods and apparatus for flow-based batching and processing
US11775359B2 (en) 2020-09-11 2023-10-03 Apple Inc. Methods and apparatuses for cross-layer processing
US11954540B2 (en) 2020-09-14 2024-04-09 Apple Inc. Methods and apparatus for thread-level execution in non-kernel space
US11799986B2 (en) 2020-09-22 2023-10-24 Apple Inc. Methods and apparatus for thread level execution in non-kernel space
US11876719B2 (en) 2021-07-26 2024-01-16 Apple Inc. Systems and methods for managing transmission control protocol (TCP) acknowledgements
US11882051B2 (en) 2021-07-26 2024-01-23 Apple Inc. Systems and methods for managing transmission control protocol (TCP) acknowledgements

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11305880A (ja) 1998-04-23 1999-11-05 Sony Corp Ｕｓｂ機器およびｕｓｂハブ装置
US20040015732A1 (en) 2002-07-18 2004-01-22 Agere Systems, Inc. Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data
JP2005148896A (ja) 2003-11-12 2005-06-09 Ricoh Co Ltd 画像機器システム
US6954879B1 (en) 1998-12-10 2005-10-11 Advanced Micro Devices, Inc. Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path
US20060161727A1 (en) * 2005-01-20 2006-07-20 Stefano Surico Method and system for managing a suspend request in a flash memory
US20060248174A1 (en) * 2005-04-29 2006-11-02 Sigmatel, Inc. System and method for accessing universal serial bus networks
US20090222690A1 (en) * 2008-02-28 2009-09-03 Secure Computing Corporation Automated computing appliance disaster recovery

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5309932B2 (ja) * 2008-12-02 2013-10-09 日本電気株式会社 ホットプラグ形式のデバイス機器を接続するための中継機器
JP5230006B2 (ja) * 2008-12-24 2013-07-10 京セラ株式会社 情報処理システム、周辺装置、情報処理装置、省電力制御方法、およびプログラム
JP2010211351A (ja) * 2009-03-09 2010-09-24 Ricoh Co Ltd 半導体集積回路、省電力制御方法、省電力制御プログラム及び記録媒体
JP2012059178A (ja) * 2010-09-13 2012-03-22 Ricoh Co Ltd Ｕｓｂハブ装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11305880A (ja) 1998-04-23 1999-11-05 Sony Corp Ｕｓｂ機器およびｕｓｂハブ装置
US6363491B1 (en) 1998-04-23 2002-03-26 Sony Corporation USB apparatus and USB hub apparatus
US6954879B1 (en) 1998-12-10 2005-10-11 Advanced Micro Devices, Inc. Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path
US20040015732A1 (en) 2002-07-18 2004-01-22 Agere Systems, Inc. Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data
JP2005148896A (ja) 2003-11-12 2005-06-09 Ricoh Co Ltd 画像機器システム
US20060161727A1 (en) * 2005-01-20 2006-07-20 Stefano Surico Method and system for managing a suspend request in a flash memory
US20060248174A1 (en) * 2005-04-29 2006-11-02 Sigmatel, Inc. System and method for accessing universal serial bus networks
GB2425861A (en) 2005-04-29 2006-11-08 Sigmatel Inc Changing the power configuration of a USB device
US20090222690A1 (en) * 2008-02-28 2009-09-03 Secure Computing Corporation Automated computing appliance disaster recovery

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
European Patent Office, European Search Report dated Aug. 20, 2012, in connection with European Application No. 11008028.0 (5 pages).

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