US8610132B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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US8610132B2
US8610132B2 US13/613,801 US201213613801A US8610132B2 US 8610132 B2 US8610132 B2 US 8610132B2 US 201213613801 A US201213613801 A US 201213613801A US 8610132 B2 US8610132 B2 US 8610132B2
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interconnection
region
trench
potential fixing
semiconductor device
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US20130075758A1 (en
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Takeyoshi Masuda
Keiji Wada
Toru Hiyoshi
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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Definitions

  • the present invention relates to a semiconductor device and a semiconductor device manufacturing method, and more particularly to a semiconductor device capable of fixing a potential at a surface portion of a semiconductor layer located outside an active region and a semiconductor device manufacturing method capable of manufacturing the semiconductor device.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a trench (groove) type element structure instead of a planar (plane) type element structure has increasingly been adopted.
  • the trench type element structure refers to an element structure characterized by formation of a channel region along a wall surface of the trench formed in a surface of an element.
  • a MOSFET serving as a power switching device is used for conversion, control, or the like of a high voltage, it is required to achieve high efficiency and low loss as well as a high breakdown voltage.
  • a trench type element structure With a trench type element structure, lower loss of an element owing to lowering in ON resistance is achieved, while a breakdown voltage of an element may lower due to a defective shape of a formed trench or the like. Specifically, local electric field concentration occurs in a portion where a defective shape of a trench is present, and resulting high electric field is likely to break a gate insulating film formed on a wall surface of the trench.
  • the present invention was made in view of the problems above, and an object thereof is to provide a semiconductor device capable of achieving improved breakdown voltage characteristics by fixing a potential of a semiconductor layer located outside an active region and a semiconductor device manufacturing method capable of manufacturing the semiconductor device.
  • a semiconductor device includes a semiconductor substrate having a trench formed in one main surface, a first insulating film arranged on and in contact with a wall surface of the trench, a gate electrode arranged on and in contact with the first insulating film, and a first interconnection arranged on one main surface.
  • the semiconductor substrate includes a drift layer having a first conductivity type and a body layer having a second conductivity type, which is arranged on a side of one main surface when viewed from the drift layer.
  • the trench is formed to penetrate the body layer and to reach the drift layer.
  • the trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally.
  • a potential fixing region where the body layer is exposed is formed in one main surface opposite to the active region when viewed from the outer peripheral trench.
  • the first interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the first interconnection.
  • an active region and a potential fixing region located outside the active region are formed. Then, the potential fixing region is electrically connected to the first interconnection arranged to lie over the active region. Therefore, in the semiconductor device according to the present invention, a potential of a semiconductor region located outside the active region can be fixed to a potential as high as the potential of the first interconnection. Consequently, according to the semiconductor device of the present invention, a semiconductor device excellent in breakdown voltage characteristics can be provided.
  • an electric field relaxing region having a second conductivity type may be formed.
  • the electric field relaxing region may be connected to the potential fixing region.
  • a pn junction is formed at an interface between the electric field relaxing region and the region of the drift layer other than the electric field relaxing region, and a depletion layer extending from the pn junction is formed in the drift layer. Consequently, owing to an electric field relaxing effect of the depletion layer extending from the pn junction, electric field applied to the first insulating film arranged on a wall surface of the outer peripheral trench can be relaxed.
  • the electric field relaxing region is connected to the potential fixing region fixed to a potential as high as a potential of the first interconnection, a potential thereof is fixed.
  • the semiconductor device above may further include a second insulating film arranged above the potential fixing region and a second interconnection arranged above the second insulating film.
  • the potential fixing region may include a potential fixing region extension portion extending to a portion below the first interconnection.
  • the gate electrode may include a gate electrode extension portion extending to a portion below the second interconnection.
  • the potential fixing region may electrically be connected to the first interconnection in the potential fixing region extension portion.
  • the gate electrode may electrically be connected to the second interconnection in the gate electrode extension portion.
  • the semiconductor device above may further include a second insulating film arranged above the potential fixing region and a second interconnection arranged above the second insulating film.
  • the first interconnection may include a first interconnection extension portion extending beyond the outer peripheral trench to the potential fixing region.
  • the second interconnection may include a second interconnection extension portion extending beyond the outer peripheral trench to the gate electrode.
  • the first interconnection may electrically be connected to the potential fixing region in the first interconnection extension portion.
  • the second interconnection may electrically be connected to the gate electrode in the second interconnection extension portion.
  • an angle formed between a sidewall surface of the trench and one main surface may be from 100° to 160°. By thus gently forming a sidewall surface of the trench, electric field concentration around a trench bottom can be suppressed. It is noted that an angle formed between a sidewall surface of the trench and one main surface means an angle formed between a sidewall surface of the trench and one main surface in the semiconductor substrate.
  • the semiconductor substrate may be composed of silicon carbide.
  • the semiconductor device according to the present invention can suitably be employed in a silicon carbide semiconductor device having the semiconductor substrate composed of silicon carbide.
  • a method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a drift layer having a first conductivity type and a body layer having a second conductivity type, which is formed on the drift layer to include one main surface, forming a trench to open on a side of one main surface and to penetrate the body layer and reach the drift layer, forming a first insulating film to include a wall surface of the trench, forming a gate electrode to be in contact with the first insulating film, and forming a first interconnection on one main surface.
  • an outer peripheral trench arranged to surround an active region when viewed two-dimensionally is formed.
  • the first interconnection is formed to lie over the active region when viewed two-dimensionally and to electrically be connected to a potential fixing region which is the body layer exposed at one main surface opposite to the active region when viewed from the outer peripheral trench.
  • the semiconductor device according to the present invention in which a potential at a surface portion of a semiconductor layer located outside an active region is fixed, can be manufactured.
  • the outer peripheral trench may be formed simultaneously with the trench other than the outer peripheral trench.
  • the method of manufacturing a semiconductor device above may further include the step of forming an electric field relaxing region having the second conductivity type, which extends to be in contact with the outer peripheral trench in the drift layer and to reach the potential fixing region.
  • the electric field relaxing region may be formed through ion implantation.
  • a semiconductor device capable of relaxing electric field applied to the first insulating film arranged on a wall surface of the outer peripheral trench can readily be manufactured.
  • a semiconductor substrate composed of silicon carbide may be prepared in the step of preparing a semiconductor substrate.
  • the method of manufacturing a semiconductor device according to the present invention can suitably be employed in a method of manufacturing a silicon carbide semiconductor device including a semiconductor substrate composed of silicon carbide.
  • breakdown voltage characteristics can be improved by fixing a potential at a surface portion of a semiconductor layer located outside an active region.
  • the semiconductor device according to the present invention above can be manufactured.
  • FIG. 1 is a schematic diagram showing a cross-sectional structure of a MOSFET along the line A-A in FIG. 4 .
  • FIG. 2 is a schematic diagram showing a cross-sectional structure of the MOSFET along the line B-B in FIG. 4 .
  • FIG. 3 is a schematic top view partially showing a structure of the MOSFET.
  • FIG. 4 is a schematic top view partially showing a structure of the MOSFET.
  • FIG. 5 is a flowchart schematically showing a method of manufacturing a MOSFET.
  • FIG. 6 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 7 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 8 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 9 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 10 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 11 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 12 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 13 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 14 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 15 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET.
  • FIG. 16 is a schematic diagram showing a cross-sectional structure of a MOSFET along the line C-C in FIG. 19 .
  • FIG. 17 is a schematic diagram showing a cross-sectional structure of the MOSFET along the line D-D in FIG. 19 .
  • FIG. 18 is a schematic top view partially showing a structure of a MOSFET according to a second embodiment.
  • FIG. 19 is a schematic top view partially showing a structure of the MOSFET according to the second embodiment.
  • FIG. 20 is a schematic cross-sectional view for illustrating a method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 21 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 22 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 23 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 24 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 25 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 26 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 27 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 28 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 29 is a schematic cross-sectional view for illustrating the method of manufacturing a MOSFET according to the second embodiment.
  • FIG. 3 is a top view of a semiconductor substrate 10 included in MOSFET 1 .
  • FIG. 4 is a top view partially showing a structure of MOSFET 1 .
  • MOSFET 1 includes semiconductor substrate 10 having a main surface 10 A, a gate oxide film 30 serving as a first insulating film, a protection oxide film 31 serving as a second insulating film, a gate electrode 40 , an interlayer insulating film 32 , a source electrode 50 , a drain electrode 51 , a source interconnection 60 serving as a first interconnection, a gate interconnection 70 serving as a second interconnection, and a drain pad electrode 80 .
  • Semiconductor substrate 10 includes a base substrate 11 , a drift layer 12 , a body layer 13 , contact regions 14 , 15 , and a source region 16 .
  • semiconductor substrate 10 may be composed of silicon carbide.
  • Trench 20 opening on a side of main surface 10 A is formed in semiconductor substrate 10 .
  • Trench 20 is formed to extend across body layer 13 and drift layer 12 , specifically to penetrate body layer 13 and to reach drift layer 12 .
  • An angle formed between a sidewall surface of trench 20 and main surface 10 A may be from 100° to 160°. By thus gently forming a sidewall surface of trench 20 , electric field concentration around a bottom of trench 20 can be suppressed. More specifically, in FIGS. 1 and 2 , an example where an angle formed between the sidewall surface of trench 20 and main surface 10 A is 90° is shown, however, by setting this angle to 100° to 160°, an angle formed between the sidewall surface of trench 20 and a bottom surface formed in parallel to main surface 10 A is also from 100° to 160°. By thus setting an angle formed between the sidewall surface of trench 20 and the bottom surface to an obtuse angle, electric field concentration around the bottom of trench 20 can be suppressed. It is noted that an angle formed between the sidewall surface of trench 20 and main surface 10 A means an angle formed between the sidewall surface of trench 20 and main surface 10 A in semiconductor substrate 10 .
  • Drift layer 12 is formed on one main surface of base substrate 11 .
  • Base substrate 11 and drift layer 12 contain such an n-type impurity as P (phosphorus), and a concentration value thereof is higher in base substrate 11 than in drift layer 12 .
  • Body layer 13 is formed to include the sidewall surface of trench 20 and to extend in contact with drift layer 12 .
  • a p-type impurity contained in body layer 13 is, for example, Al (aluminum), B (boron), or the like.
  • Source region 16 is formed to include main surface 10 A on a side opposite to drift layer 12 when viewed from body layer 13 .
  • Source region 16 is formed to include the sidewall surface of trench 20 and to be in contact with body layer 13 .
  • An n-type impurity contained in source region 16 is, for example, P (phosphorus) or the like, and a concentration value thereof is higher than that in drift layer 12 .
  • Contact regions 14 , 15 are formed to include main surface 10 A, while they are in contact with body layer 13 .
  • contact region 14 is formed adjacent to source region 16 .
  • a p-type impurity contained in contact regions 14 , 15 is, for example, Al, B, or the like, and a concentration value thereof is higher than that in body layer 13 .
  • trench 20 when viewed two-dimensionally from above main surface 10 A of semiconductor substrate 10 , trench 20 includes an outer peripheral trench 22 arranged to surround an active region 10 B and an inner trench 21 defined as trench 20 other than outer peripheral trench 22 .
  • Active region 10 B is a region where contact region 14 and source region 16 are formed in a region including main surface 10 A. This active region 10 B operates as a device.
  • main surface 10 A located opposite to active region 10 B when viewed from outer peripheral trench 22 that is, outside of active region 10 B, a potential fixing region 10 C where body layer 13 is exposed is formed. In a region of potential fixing region 10 C including main surface 10 A, contact region 15 is formed.
  • potential fixing region 10 C is formed to include a potential fixing region extension portion 10 D extending toward active region 10 B when viewed two-dimensionally.
  • outer peripheral trench 22 is formed to include an outer peripheral trench extension portion 22 A extending toward potential fixing region 10 C along potential fixing region extension portion 10 D in such a manner that outer peripheral trench extension portion 22 A and potential fixing region extension portion 10 D are staggered.
  • gate oxide film 30 is arranged on and in contact with the wall surface of trench 20 .
  • Protection oxide film 31 is arranged above potential fixing region 10 C, in contact with main surface 10 A.
  • Gate oxide film 30 and protection oxide film 31 are composed, for example, of silicon dioxide (SiO 2 ).
  • Gate electrode 40 is arranged on and in contact with gate oxide film 30 . More specifically, gate electrode 40 is formed to bury trench 20 on which gate oxide film 30 is formed. In addition, gate electrode 40 includes a gate electrode extension portion 40 A formed to bury outer peripheral trench extension portion 22 A. Gate electrode 40 is composed, for example, of such a conductor as Al or polysilicon to which an impurity has been added.
  • Source electrode 50 is arranged on main surface 10 A, to be in contact with contact region 14 or contact region 15 and source region 16 .
  • Source electrode 50 is made of a material capable of establishing ohmic contact with source region 16 , such as Ni x Si y (nickel silicide), Ti x Si y (titanium silicide), Al x Si y (aluminum silicide), and Ti x Al y Si z (titanium aluminum silicide), and electrically connected to source region 16 .
  • Drain electrode 51 is arranged in contact with a main surface opposite to drift layer 12 when viewed from base substrate 11 .
  • Drain electrode 51 is made of a material capable of establishing ohmic contact with base substrate 11 , such as a material similar to that for source electrode 50 , and electrically connected to base substrate 11 .
  • Interlayer insulating film 32 is arranged on and in contact with gate electrode 40 and protection oxide film 31 , and it electrically isolates gate electrode 40 from source electrode 50 .
  • Interlayer insulating film 32 is composed, for example, of silicon dioxide (SiO 2 ).
  • source interconnection 60 is arranged to lie over active region 10 B when viewed two-dimensionally.
  • source interconnection 60 is made, for example, of such a conductor as Al, and it is electrically connected to source region 16 through source electrode 50 .
  • potential fixing region 10 C includes potential fixing region extension portion 10 D extending to a portion below source interconnection 60 , and it is electrically connected to source interconnection 60 in potential fixing region extension portion 10 D.
  • potential fixing region 10 C is electrically connected to source interconnection 60 through source electrode 50 in contact region 15 formed in potential fixing region extension portion 10 D.
  • a potential of potential fixing region 10 C is fixed to a potential as high as that of source interconnection 60 .
  • gate interconnection 70 is arranged at a distance from source interconnection 60 , to lie over potential fixing region 10 C when viewed two-dimensionally.
  • gate electrode 40 includes gate electrode extension portion 40 A extending to a portion below gate interconnection 70 , and it is electrically connected to gate interconnection 70 in gate electrode extension portion 40 A.
  • Gate interconnection 70 is made, for example, of a material similar to that for source interconnection 60 .
  • gate electrode extension portion 40 A and potential fixing region extension portion 10 D are formed alternately in a direction along an outer periphery of source interconnection 60 (a direction vertical to a sheet surface in FIGS. 1 and 2 ).
  • drain pad electrode 80 is arranged to cover drain electrode 51 .
  • Drain pad electrode 80 is made, for example, of a material similar to that for source interconnection 60 and gate interconnection 70 , and it is electrically connected to base substrate 11 through drain electrode 51 .
  • MOSFET 1 as the semiconductor device according to the present embodiment includes semiconductor substrate 10 having trench 20 formed in main surface 10 A, gate oxide film 30 arranged on and in contact with the wall surface of trench 20 , gate electrode 40 arranged on and in contact with gate oxide film 30 , and source interconnection 60 arranged on main surface 10 A.
  • Semiconductor substrate 10 includes drift layer 12 having a p conductivity type and body layer 13 having an n conductivity type, which is arranged on the main surface 10 A side when viewed from drift layer 12 .
  • Trench 20 is formed to penetrate body layer 13 and to reach drift layer 12 .
  • Trench 20 includes outer peripheral trench 22 arranged to surround active region 10 B when viewed two-dimensionally.
  • MOSFET 1 is a semiconductor device having improved breakdown voltage characteristics, as a potential of potential fixing region 10 C which is a semiconductor region located outside active region 10 B is fixed to a potential as high as a potential of source interconnection 60 .
  • p-type electric field relaxing region 17 is formed in a region of drift layer 12 in contact with outer peripheral trench 22 .
  • electric field relaxing region 17 is connected to potential fixing region 10 C.
  • electric field relaxing region 17 is not an essential feature in the semiconductor device according to the present invention, by including electric field relaxing region 17 , a pn junction is formed at an interface between electric field relaxing region 17 and a region of drift layer 12 other than electric field relaxing region 17 , and in drift layer 12 , a depletion layer extending from the pn junction is formed. Consequently, owing to an electric field relaxing effect of the depletion layer extending from the pn junction, electric field applied to gate oxide film 30 arranged on the wall surface of outer peripheral trench 22 can be relaxed. In addition, a potential of electric field relaxing region 17 is fixed by being connected to potential fixing region 10 C fixed to a potential as high as a potential of source interconnection 60 .
  • FIGS. 6 , 8 , 10 , 12 , and 14 partially show a cross-sectional structure of MOSFET 1 along the line A-A in FIG. 4
  • FIGS. 7 , 9 , 11 , 13 , and 15 partially show a cross-sectional structure of MOSFET 1 along the line B-B in FIG. 4
  • MOSFET 1 as the semiconductor device according to the present embodiment above is manufactured.
  • a semiconductor substrate preparation step is performed as a step (S 10 ).
  • step (S 10 ) referring to FIGS. 6 and 7 , initially, base substrate 11 is prepared. Then, for example, through epitaxial growth, a semiconductor layer 18 having the n conductivity type is formed on one main surface of base substrate 11 . Then, for example, Al ions are implanted into a region of semiconductor layer 18 including a surface portion, to thereby form body layer 13 . Then, a region of semiconductor layer 18 where body layer 13 was not formed serves as drift layer 12 .
  • semiconductor substrate 10 composed, for example, of silicon carbide is prepared.
  • a trench formation step is performed as a step (S 20 ).
  • this step (S 20 ) referring to FIGS. 8 and 9 , trench 20 opening on the main surface 10 A side is formed in semiconductor substrate 10 .
  • an etching method such as RIE (Reactive Ion Etching) or thermal etching or combination thereof, trench 20 is formed to penetrate body layer 13 and to reach drift layer 12 .
  • RIE Reactive Ion Etching
  • outer peripheral trench 22 arranged to surround a region where active region 10 B should be formed in a subsequent step (S 30 ) and inner trench 21 which is trench 20 other than outer peripheral trench 22 , arranged in the region above where active region 10 B should be formed, are formed.
  • Outer peripheral trench 22 is formed to have an outer peripheral trench extension portion 22 A protruding toward a region where potential fixing region 10 C should be formed in the subsequent step (S 30 ) when viewed two-dimensionally.
  • outer peripheral trench 22 may be formed simultaneously with inner trench 21 .
  • the step above can more efficiently be performed.
  • an ion implantation step is performed as the step (S 30 ).
  • an electric field relaxing region formation step as a step (S 31 )
  • a contact region formation step as a step (S 32 ) are performed.
  • step (S 31 ) Al ions are implanted into a region including main surface 10 A of semiconductor substrate 10 and a wall surface of outer peripheral trench extension portion 22 A.
  • a region 13 A higher in p-type impurity concentration than body layer 13 is formed in a region including main surface 10 A, and electric field relaxing region 17 having the p conductivity type and extending to be in contact with outer peripheral trench 22 is formed in drift layer 12 .
  • step (S 32 ) initially, for example, P ions are implanted into a region including main surface 10 A to thereby form source region 16 . Then, for example, Al ions are further implanted into a region including main surface 10 A to thereby form contact regions 14 , 15 .
  • active region 10 B including contact region 14 and source region 16 and potential fixing region 10 C including contact region 15 , where body layer 13 is exposed are formed (see FIG. 3 ).
  • potential fixing region 10 C is formed to include potential fixing region extension portion 10 D extending toward active region 10 B.
  • an activation annealing step is performed as a step (S 40 ).
  • this step (S 40 ) by heating semiconductor substrate 10 , an impurity introduced in the step (S 30 ) above is activated. Thus, desired carriers are generated in the region where the impurity has been introduced.
  • an oxide film formation step is performed as a step (S 50 ).
  • this step (S 50 ) referring to FIGS. 12 and 13 , as semiconductor substrate 10 is heated in an atmosphere containing, for example, oxygen, gate oxide film 30 and protection oxide film 31 composed of silicon dioxide (SiO 2 ) are formed across a region including the wall surface of trench 20 and main surface 10 A.
  • a gate electrode formation step is performed as a step (S 60 ).
  • this step (S 60 ) referring to FIGS. 14 and 15 , for example, with LPCVD (Low Pressure Chemical Vapor Deposition), a polysilicon film is formed to bury trench 20 .
  • gate electrode 40 in contact with gate oxide film 30 is formed.
  • gate electrode 40 is formed to bury outer peripheral trench extension portion 22 A in this step (S 60 ), it is formed to include gate electrode extension portion 40 A extending toward potential fixing region 10 C.
  • An interlayer insulating film formation step is performed as a step (S 70 ).
  • step (S 70 ) for example, with P (Plasma)-CVD, interlayer insulating film 32 composed of silicon dioxide (SiO 2 ) which is an insulator is formed on and in contact with gate electrode 40 and protection oxide film 31 .
  • an ohmic electrode formation step is performed as a step (S 80 ).
  • this step (S 80 ) initially, for example, with such an etching method as RIE, interlayer insulating film 32 and protection oxide film 31 are partially removed, to thereby form a contact hole where contact regions 14 , 15 and source region 16 are exposed.
  • a film composed of Ni is formed in the contact hole above.
  • a film composed of Ni is similarly formed on the main surface of base substrate 11 opposite to the side where drift layer 12 is formed.
  • alloying heating treatment is performed, so that at least a part of the film composed of Ni above is converted to silicide to thereby form source electrode 50 and drain electrode 51 .
  • a source interconnection formation step is performed as a step (S 90 ).
  • step (S 90 ) referring to FIGS. 1 , 2 , and 4 , for example, with the vapor deposition method, source interconnection 60 composed of Al which is a conductor is formed to lie over active region 10 B and potential fixing region extension portion 10 D.
  • a gate interconnection formation step is performed as a step (S 100 ).
  • this step (S 100 ) for example, with the vapor deposition method, gate interconnection 70 composed of Al is formed to lie over potential fixing region 10 C and gate electrode extension portion 40 A.
  • a drain pad electrode formation step is performed as a step (S 110 ).
  • this step (S 110 ) for example, with the vapor deposition method, drain pad electrode 80 composed of Al is formed to cover drain electrode 51 .
  • MOSFET 1 is manufactured and the semiconductor device manufacturing method according to the present embodiment is completed.
  • MOSFET 1 as the semiconductor device according to the present embodiment above capable of fixing a potential at the surface portion of the semiconductor layer located outside the active region can be manufactured.
  • FIG. 18 is a plan view showing a top surface of semiconductor substrate 10 provided in MOSFET 2 .
  • FIG. 19 is a plan view showing a top surface of MOSFET 2 .
  • MOSFET 2 is basically the same in structure and effect as MOSFET 1 as the semiconductor device according to the first embodiment above.
  • MOSFET 2 is different from MOSFET 1 in connection between the potential fixing region and the source interconnection and connection between the gate electrode and the gate interconnection.
  • source interconnection 60 is arranged to lie over active region 10 B when viewed two-dimensionally and is electrically connected to source region 16 through source electrode 50 , as in the first embodiment.
  • source interconnection 60 includes a source interconnection extension portion 60 A serving as a first interconnection extension portion extending beyond outer peripheral trench 22 to potential fixing region 10 C and it is electrically connected to potential fixing region 10 C in source interconnection extension portion 60 A.
  • Gate interconnection 70 is arranged to lie over potential fixing region 10 C when viewed two-dimensionally, as in the first embodiment.
  • gate interconnection 70 includes a gate interconnection extension portion 70 A serving as a second interconnection extension portion extending beyond outer peripheral trench 22 to gate electrode 40 and it is electrically connected to gate electrode 40 in gate interconnection extension portion 70 A.
  • FIGS. 20 , 22 , 24 , 26 , and 28 partially show a cross-sectional structure of MOSFET 2 along the line C-C in FIG. 19
  • FIGS. 21 , 23 , 25 , 27 , and 29 partially show a cross-sectional structure of MOSFET 2 along the line D-D in FIG. 19 .
  • the semiconductor device manufacturing method according to the present embodiment is basically performed in the steps the same as those in the semiconductor device manufacturing method according to the first embodiment, and achieves the same effect.
  • MOSFET 2 as the semiconductor device according to the present embodiment above is manufactured.
  • the semiconductor substrate preparation step is performed as the step (S 10 ).
  • semiconductor substrate 10 including base substrate 11 , drift layer 12 , and body layer 13 is prepared.
  • the trench formation step is performed as the step (S 20 ).
  • trench 20 opening on the main surface 10 A side and penetrating body layer 13 to reach drift layer 12 is formed in semiconductor substrate 10 .
  • outer peripheral trench 22 surrounding an outer periphery of a region where active region 10 B should be formed in the subsequent step (S 30 ) and inner trench 21 which is trench 20 other than outer peripheral trench 22 , arranged in the region above where active region 10 B should be formed, are formed.
  • outer peripheral trench 22 is formed without extending toward the region where potential fixing region 10 C should be formed in the subsequent step (S 30 ).
  • the ion implantation step is performed as the step (S 30 ).
  • the electric field relaxing region formation step as the step (S 31 ) and the contact region formation step as the step (S 32 ) are performed.
  • step (S 31 ) electric field relaxing region 17 extending to be in contact with outer peripheral trench 22 is formed in drift layer 12 .
  • step (S 32 ) contact regions 14 , 15 and source region 16 are formed in the region including main surface 10 A.
  • potential fixing region 10 C is formed without extending toward active region 10 B.
  • the activation annealing step is performed as the step (S 40 ).
  • semiconductor substrate 10 is heated.
  • the oxide film formation step is performed as the step (S 50 ). Referring to FIGS. 26 and 27 , in this step (S 50 ), as in the first embodiment, gate oxide film 30 and protection oxide film 31 are formed across the region including the wall surface of trench 20 and main surface 10 A.
  • the gate electrode formation step is performed as the step (S 60 ).
  • the gate electrode 40 in contact with gate oxide film 30 is foamed.
  • outer peripheral trench 22 is formed without extending toward potential fixing region 10 C
  • gate electrode 40 is formed without extending toward potential fixing region 10 C.
  • interlayer insulating film formation step is performed as the step (S 70 ).
  • interlayer insulating film 32 is formed to be in contact with gate electrode 40 and protection oxide film 31 .
  • the ohmic electrode formation step is performed as the step (S 80 ).
  • the ohmic electrode formation step is performed as the step (S 80 ). Referring to FIGS. 16 and 17 , in this step (S 80 ), as in the first embodiment, source electrode 50 and drain electrode 51 are formed.
  • the source interconnection formation step is performed as the step (S 90 ).
  • step (S 90 ) referring to FIGS. 16 to 19 , for example, with the vapor deposition method, source interconnection 60 composed of Al which is a conductor is formed to lie over active region 10 B. Then, in the present embodiment, source interconnection 60 is formed to include source interconnection extension portion 60 A extending beyond outer peripheral trench 22 to potential fixing region 10 C.
  • the gate interconnection formation step is performed as the step (S 100 ).
  • step (S 100 ) for example, with the vapor deposition method, gate interconnection 70 composed of Al which is a conductor is formed to lie over potential fixing region 10 C. Then, in the present embodiment, gate interconnection 70 is formed to include gate interconnection extension portion 70 A extending beyond outer peripheral trench 22 to gate electrode 40 .
  • drain pad electrode formation step is performed as the step (S 110 ).
  • drain pad electrode 80 is formed to cover drain electrode 51 .
  • MOSFETs 1 , 2 as the semiconductor devices according to the embodiments of the present invention above, active region 10 B and potential fixing region 10 C which is a semiconductor layer located outside active region 10 B are formed. Then, potential fixing region 10 C is electrically connected to source interconnection 60 arranged to lie over active region 10 B. Therefore, in MOSFETs 1 , 2 as the semiconductor devices according to the embodiments of the present invention above, a potential at the surface portion of the semiconductor layer located outside active region 10 B can be fixed to a potential as high as a potential of source interconnection 60 . Consequently, with MOSFETs 1 , 2 as the semiconductor devices according to the embodiments of the present invention above, the semiconductor device excellent in breakdown voltage characteristics can be provided.
  • MOSFETs 1 , 2 as the semiconductor devices according to the embodiments of the present invention above, electrical connection between gate interconnection 70 arranged on potential fixing region 10 C and gate electrode 40 can readily be achieved while a potential of potential fixing region 10 C is fixed to a potential of source interconnection 60 . Then, MOSFETs 1 , 2 are different from each other in connection between potential fixing region 10 C and source interconnection 60 and connection between gate interconnection 70 and gate electrode 40 , as set forth below.
  • source interconnection 60 is electrically connected to potential fixing region 10 C without extending to potential fixing region 10 C.
  • gate interconnection 70 is electrically connected to gate electrode 40 without extending to gate electrode 40 . Therefore, in MOSFET 1 , source interconnection 60 and gate interconnection 70 are readily arranged while a distance therebetween is maintained when viewed two-dimensionally. Consequently, according to MOSFET 1 , contact between source interconnection 60 and gate interconnection 70 can readily be avoided and short-circuiting between source interconnection 60 and gate interconnection 70 can be suppressed.
  • potential fixing region 10 C is electrically connected to source interconnection 60 without extending to a portion below source interconnection 60 . Therefore, in electrical connection between potential fixing region 10 C and source interconnection 60 , potential fixing region 10 C can be formed more readily than in a case where potential fixing region 10 C is caused to extend to the portion below source interconnection 60 .
  • gate electrode 40 is electrically connected to gate interconnection 70 without extending to a portion below gate interconnection 70 . Therefore, in electrical connection between gate electrode 40 and gate interconnection 70 , gate electrode 40 can be formed more readily than in a case where gate electrode 40 is caused to extend to the portion below gate interconnection 70 . Consequently, according to MOSFET 2 , a structure in semiconductor substrate 10 can be easier to form.
  • the semiconductor device and the semiconductor device manufacturing method according to the present invention can particularly advantageously be applied to a semiconductor device required to have a fixed potential at a surface portion of a semiconductor layer located outside an active region and a method of manufacturing the semiconductor device.

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