US8575901B2 - Auto-selecting holding current circuit - Google Patents

Auto-selecting holding current circuit Download PDF

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US8575901B2
US8575901B2 US13/410,034 US201213410034A US8575901B2 US 8575901 B2 US8575901 B2 US 8575901B2 US 201213410034 A US201213410034 A US 201213410034A US 8575901 B2 US8575901 B2 US 8575901B2
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current
signal
gate
flip
output end
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US20130009616A1 (en
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Lon-Kou Chang
Hsing-Fu Liu
Chang-Yu Wu
Li-Wei Yen
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Macroblock Inc
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Macroblock Inc
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B39/00—Circuit arrangements or apparatus for operating incandescent light sources
    • H05B39/04—Controlling
    • H05B39/041—Controlling the light-intensity of the source
    • H05B39/044—Controlling the light-intensity of the source continuously
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/31—Phase-control circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/357—Driver circuits specially adapted for retrofit LED light sources
    • H05B45/3574—Emulating the electrical or functional characteristics of incandescent lamps
    • H05B45/3575—Emulating the electrical or functional characteristics of incandescent lamps by means of dummy loads or bleeder circuits, e.g. for dimmers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the disclosure relates to an auto-selecting holding current circuit, and more particularly to an auto-selecting holding current circuit capable of being coupled to different Triodes for Alternating Current (TRIACs).
  • TRIACs Alternating Current
  • illuminators power consumption of illuminators is usually too high. When strong illumination is not needed, energy can be saved effectively if the illumination of the illuminator can be lowered.
  • Common dimmers include TRIAC dimmers, electronic dimmers, and remote control dimmers (such as infrared or radio frequency remote control dimmers).
  • the TRIAC dimmer mainly includes a TRIAC for changing the input power of a light, and one of the TRIAC features is the holding-current value.
  • the TRIAC When the TRIAC is triggered, the TRIAC maintains a conducting state. When the current flowing through the TRIAC drops below the holding-current value, the TRIAC is closed (or cut off).
  • both the input voltage and the input current of the illuminator are decreased, which causes the TRIAC to be closed earlier than expected since the current flowing through the TRIAC is smaller than the holding-current value, and further causes the TRIAC misfire and illuminator to flicker.
  • a conventional method for adding a bleeder circuit (or dummy load) in the TRIAC dimmable LED driver is adopted, so that the current flowing through the TRIAC is higher than the holding-current value even when the TRIAC current is decreased, therefore maintaining normal functions of the TRIAC.
  • a common bleeder circuit transmits an extra current extracted from an input voltage to the TRIAC by connecting a constant resistor to the input voltage in parallel, so that the current flowing through the TRIAC is greater than the holding-current value, therefore maintaining the TRIAC turned-on.
  • the above method fails to achieve an effect of dynamically compensating for the exact amount of current that the TRIAC lacks.
  • a conventional adaptive bleeder circuit is provided to dynamically satisfy the current needed by the TRIAC.
  • the adaptive bleeder circuit is merely applicable to the TRIAC having a specific holding-current value.
  • the same adaptive bleeder circuit is not applicable to another TRIAC having a different holding-current value. Therefore, the conventional adaptive bleeder circuit is inconvenient in use.
  • the disclosure is an auto-selecting holding current circuit, so as to solve a problem that the conventional adaptive bleeder circuit is not applicable to TRIACs having different holding-current values.
  • An auto-selecting holding current circuit is applicable to a converter.
  • an input voltage which is input into the primary side of the converter is adjusted by a TRIAC.
  • the primary side is connected with the TRIAC having a holding-current value.
  • a bleeder circuit is mounted at the primary side, and makes an input current flowing through the TRIAC be greater than or equal to the holding current value according to an input current detector signal and a reference current signal.
  • the bleeder circuit will output a current to maintain the TRIAC turned-on.
  • the different TRIACs have different holding current value.
  • the auto-selecting holding current circuit is used to detect the TRIAC holding-current value and modify the bleeder reference voltage level.
  • the auto-selecting holding current circuit comprises a first sensor module, a second sensor module and a reference voltage selecting circuit.
  • the first sensor module senses a current drop time of the current detector signal or voltage drop time of the input voltage, so as to detect when the TRIAC is turned off and, therefore, outputs a sense signal.
  • the second sensor module receives the current detector signal and outputs a critical current signal used to detect a current value range when the TRIAC is turned off.
  • the current range stands for the TRIAC holding-current value.
  • the reference voltage selecting circuit outputs the reference current signal to the bleeder circuit according to the sense signal and the critical current signal. Therefore, based on the reference current signal, the bleeder circuit maintains the input current of the converter be greater than or equal to the holding-current value.
  • the reference voltage selecting circuit obtains a holding-current-value range of the TRIAC to output the corresponding reference current signal to the bleeder circuit, so that the bleeder circuit dynamically adjusts a pulse modulation signal to make the TRIAC operate normally.
  • FIG. 1 is a circuit block diagram of a bleeder circuit applied in a converter according to an embodiment of the disclosure
  • FIG. 2 is a circuit block diagram of an auto-selecting holding current circuit according to FIG. 1 ;
  • FIG. 3 is a schematic time-sequence oscillogram of a current detector signal of FIG. 1 ;
  • FIG. 4 is a circuit block diagram of a bleeder circuit applied in a converter according to another embodiment of the disclosure.
  • FIG. 5 is a schematic structural view of a circuit of a bleeder circuit according to a first embodiment of the disclosure
  • FIG. 6A is a schematic structural view of a circuit of a first sensor module according to another embodiment
  • FIG. 6B is a schematic time-sequence oscillogram of a reference voltage and a current detector signal according to FIG. 6A ;
  • FIG. 7A to FIG. 7D are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is greater than a preset current signal according to FIG. 5 ;
  • FIG. 8A to FIG. 8D are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is smaller than a preset current signal according to FIG. 5 ;
  • FIG. 9 is a schematic structural view of a circuit of a bleeder circuit according to a second embodiment of the disclosure.
  • FIG. 10A to FIG. 10F are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is greater than a third preset current signal according to FIG. 9 ;
  • FIG. 11A to FIG. 11F are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is between a second preset current signal and a third preset current signal according to FIG. 9 ;
  • FIG. 12A to FIG. 12F are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is between a first preset current signal and a second preset current signal according to FIG. 9 ;
  • FIG. 13A to FIG. 13F are respectively time-sequence oscillograms of a current detector signal, a sense signal, a critical current signal and a reference current signal when a holding-current value of a TRIAC is smaller than a first preset current signal according to FIG. 9 ;
  • FIG. 14 is a schematic structural view of a circuit of an auto-selecting holding current circuit according to a third embodiment of the disclosure.
  • FIG. 15A is a schematic structural view of a circuit of a comparator and a counter of a auto-selecting holding current circuit according to a fourth embodiment of the disclosure.
  • FIG. 15B is a schematic structural view of a circuit of a decoder and a preset threshold voltage selecting circuit of a auto-selecting holding current circuit according to a fourth embodiment of the disclosure.
  • FIG. 1 is a circuit block diagram in which a bleeder circuit is applied in a converter according to an embodiment of the disclosure.
  • a bleeder circuit 28 may be applied to a converter 50 .
  • the converter 50 may be, but is not limited to, an Isolated Converter. That is to say, the converter 50 may also be a Buck Converter, Boost Converter, Buck-boost Converter, Forward Converter, a Half-bridge Converter, a Full-bridge Converter, a Push-Pull Converter or a Flyback Converter.
  • the converter 50 has a primary side 51 and a secondary side 52 .
  • the primary side 51 has an alternating current (AC) signal source 20 , a TRIAC 22 , a bridge rectifier 23 , a current sensor 24 , a low pass filter 26 and the bleeder circuit 28 .
  • the secondary side 52 has a load 30 , and the load 30 may be, but is not limited to, Light-Emitting Diodes (LEDs).
  • the primary side 51 is supplied with a voltage V IN — 2 which is output by the low pass filter 26 with an input of an input voltage V IN .
  • the input voltage V IN is the output of the AC signal source 20 passing through the TRIAC 22 and rectified by the bridge rectifier 23 .
  • FIG. 2 is a circuit block diagram of an auto-selecting holding current circuit according to FIG. 1 .
  • an auto-selecting holding current circuit 100 which is connected to the primary side 51 comprises a first sensor module 200 , a second sensor module 300 and a reference voltage selecting circuit 400 .
  • the first sensor module 200 is connected to the current sensor 24 .
  • the first sensor module 200 senses a current drop time (i.e. a current drop when the TRIAC 22 is cut off, for example, the point P in FIG. 3 ) of a current detector signal V CS output by the current sensor 24 (referring to FIG. 3 , which is a schematic time-sequence oscillogram of a current detector signal of FIG.
  • the second sensor module 300 receives the current detector signal V CS and outputs a critical current signal V th , in which the critical current signal V th is used to detect the holding-current value I H of the TRIAC 22 .
  • the reference voltage selecting circuit 400 outputs a reference current signal V Iref to the bleeder circuit 28 according to the sense signal V cd and the critical current signal V th .
  • the reference current signal V Iref corresponds to the holding-current value I H of the TRIAC 22 .
  • the bleeder circuit 28 maintains the input current I IN of the converter, which flows through the TRIAC 22 , to be greater than or equal to the holding-current value I H , so as to make the TRIAC 22 operates normally.
  • the first sensor module 200 may also be used to sense a voltage drop time of the input voltage V IN (i.e. a voltage drop when the TRIAC 22 is turned off), and then output the sense signal V cd (referring to FIG. 4 , which is a circuit block diagram in which a bleeder circuit is applied in a converter according to another embodiment of the disclosure). It is taken as examples in the following embodiments that the first sensor module 200 senses the current drop of the current detector signal V CS , but these examples are not intended to limit the scope of the disclosure.
  • FIG. 5 is a schematic structural view of a circuit of an auto-selecting holding current circuit according to a first embodiment of the disclosure.
  • a first sensor module 200 comprises a differentiator 202 which senses a current drop time for outputting a sense signal V cd to a reference voltage selecting circuit 400 .
  • FIG. 6A is a schematic structural view of a circuit of a first sensor module according to another embodiment of the disclosure and
  • FIG. 6B is a schematic time-sequence oscillogram of a reference voltage and a current detector signal according to FIG. 6A .
  • the first sensor module 200 may also comprise a comparator 40 .
  • the comparator 40 receives a current detector signal V CS and compares the current detector signal V CS to a reference voltage V REF , and thereby, output the sense signal V cd .
  • the reference voltage V REF is smaller than a feedback signal value of a holding-current value I H of the TRIAC 22 , wherein the feedback signal value of the holding-current value I H is the current detector signal V CS output by a current sensor 24 while a current equal to the holding-current value I H flows through the current sensor 24 .
  • a second sensor module 300 comprises a comparator 302 and a first NOT gate 304 .
  • the comparator 302 receives the current detector signal V CS and outputs a comparison signal V C after comparing the current detector signal V CS with a preset current signal V p .
  • the first NOT gate 304 receives the comparison signal V C and outputs a critical current signal V th to a reference voltage selecting circuit 400 .
  • the reference voltage selecting circuit 400 comprises a second AND gate 402 , a first reset-set (RS) flip-flop 404 , a second RS flip-flop 406 , a switch element 408 , a switch element 410 and a voltage divider 412 .
  • An input end 41 of the second AND gate 402 is coupled to the first sensor module 200
  • an input end 42 of the second AND gate 402 is coupled to the second sensor module 300 .
  • An output end 43 of the second AND gate 402 is coupled to a set end S of the first RS flip-flop 404
  • an output end Q of the first RS flip-flop 404 is coupled to a reset end R′ of the second RS flip-flop 406 .
  • a reset end R of the first RS flip-flop 404 is grounded, and an output end Q o of the first RS flip-flop 404 is coupled to a set end S′ of the second RS flip-flop 406 .
  • An output end Q′ of the second RS flip-flop 406 and the output end Q of the first RS flip-flop 406 respectively control the switch elements 408 and 410 , so that the voltage divider 412 outputs a reference current signal V Iref .
  • the first RS flip-flop 404 and the second RS flip-flop 406 may be, but are not limited to, NAND gate RS flip-flops. However, the embodiment is not intended to limit the disclosure.
  • the first RS flip-flop 404 and the second RS flip-flop 406 may be NOR gate RS flip-flops.
  • FIG. 7A to FIG. 7D are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signal V th and the reference current signal V Iref in the case of the holding-current value of a TRIAC being greater than a preset current signal value.
  • the differentiator 202 When sensing a current drop (namely the point Y in FIG. 7A ), the differentiator 202 outputs the sense signal V cd (namely a pulse signal in FIG. 7B ) to the input end 41 of the second AND gate 402 .
  • the differentiator 202 is used to detect a sudden drop time of the current detector signal V CS .
  • the comparator 302 receives the current detector signal V CS and outputs the comparison signal V C after comparing the current detector signal V CS with the preset current signal V p which corresponds to the preset current signal value.
  • the first NOT gate 304 receives the comparison signal V C and outputs the critical current signal V th to the input end 42 of the second AND gate 402 . When the current detector signal V CS is greater than the preset current signal V p , the critical current signal V th is at a high level.
  • the output end 43 of the second AND gate 402 outputs the high level to the set end S of the first RS flip-flop 404 , so that the output end Q of the first RS flip-flop 404 outputs the high level, and the output end Q′ of the second RS flip-flop 406 outputs a low level.
  • the switch element 410 is actuated, and therefore the voltage divider 412 outputs a corresponding reference current signal V Iref 2 .
  • FIG. 8A to FIG. 8D are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signal V th and the reference current signal V I — ref in a case of the holding-current value of a TRIAC being smaller than the preset current signal value.
  • the differentiator 202 When sensing a current drop (namely the point Y′ in FIG. 8A ), the differentiator 202 outputs the sense signal V cd (namely a pulse signal in FIG. 8B ) to the input end 41 of the second AND gate 402 .
  • the differentiator 202 is used to detect a sudden drop time of the current detector signal V CS .
  • the comparator 302 receives the current detector signal V CS and outputs the comparison signal V C after comparing the current detector signal V CS with the preset current signal V p .
  • the first NOT gate 304 receives the comparison signal V C and outputs the critical current signal V th to the input end 42 of the second AND gate 402 .
  • the critical current signal V th is at the low level.
  • the output end 43 of the second AND gate 402 outputs the low level to the set end S of the first RS flip-flop 404 , so that the output end Q of the first RS flip-flop 404 outputs the low level, and the output end Q′ of the second RS flip-flop 406 outputs the high level.
  • the switch element 408 is actuated, and therefore the voltage divider 412 outputs a corresponding reference current signal V Iref — 1 .
  • the sudden drop time of the current detector signal V CS is the moment when the input current I IN is smaller than the holding-current value I H which causes the TRIAC turned off. Accordingly, by setting the reference current signal V Iref (namely, V Iref — 1 or V Iref — 2 ) output by the reference voltage selecting circuit 400 to a value corresponding to the holding-current value I H of the TRIAC 22 , the bleeder circuit 28 may control the input current I IN flowing through the TRIAC 22 to be greater than or equal to the holding-current value I H according to the reference current signal V Iref and the current detector signal V CS to make the TRIAC 22 operate normally.
  • V Iref namely, V Iref — 1 or V Iref — 2
  • the second sensor module 300 only can provide one single preset current signal, so the auto-selecting holding current circuit 100 is capable of providing two types of reference current signals V Iref .
  • the auto-selecting holding current circuit 100 can provide more than two types of reference current signals V Iref , the auto-selecting holding current circuit 100 is capable of providing more than two types of reference current signals V Iref .
  • the auto-selecting holding current circuit 100 provides four types of reference current signals V Iref .
  • the second embodiment is not intended to limit the disclosure.
  • the auto-selecting holding current circuit 100 can provide three types or more than four types of reference current signals V Iref .
  • FIG. 9 is a schematic structural view of a circuit of an auto-selecting holding current circuit according to a second embodiment of the disclosure.
  • a second sensor module 300 comprises a comparator 330 , a comparator 331 , a comparator 332 , a first NOT gate 333 , a first NOT gate 334 , a first NOT gate 335 , a first AND gate 336 and a first AND gate 337 .
  • the comparator 330 , the comparator 331 and the comparator 332 respectively receive a current detector signal V CS output by a current sensor 24 .
  • An input end of the first NOT gate 333 is coupled to an output end of the comparator 330 .
  • An output end of the first NOT gate 333 is coupled to an input end of the first AND gate 336 .
  • Another input end of the first AND gate 336 is coupled to an output end of the comparator 331 .
  • An input end of the first NOT gate 334 is coupled to the output end of the comparator 331 .
  • An output end of the first NOT gate 334 is coupled to an input end of the first AND gate 337 .
  • Another input end of the first AND gate 337 is coupled to an output end of the comparator 332 .
  • An input end of the first NOT gate 335 is coupled to the output end of the comparator 332 , and an output end of the first NOT gate 335 is coupled to the reference voltage selecting circuit 400 .
  • the output end of the first NOT gate 335 , the output end of the first AND gate 336 and the output end of the first AND gate 337 respectively output a critical current signal V t4 , a critical current signal V t3 and a critical current signal V t2 to the reference voltage selecting circuit 400 .
  • the reference voltage selecting circuit 400 may comprise a second AND gate 420 , a second AND gate 421 , a second AND gate 422 , an RS flip-flop 423 , an RS flip-flop 424 , an RS flip-flop 425 , an RS flip-flop 426 , a first OR gate 427 , a first OR gate 428 , a switch element 429 , a switch element 430 , a switch element 431 , a switch element 432 and a voltage divider 433 .
  • An input end of the second AND gate 420 is coupled to an output end of the first AND gate 336 ; another input end of the second AND gate 420 is coupled to a first sensor module 200 ; and further another input end of the second AND gate 420 is coupled to an output end Q 03 of the RS flip-flop 425 .
  • An output end of the second AND gate 420 is coupled to a set end S 2 of the RS flip-flop 424 .
  • An input end of the second AND gate 421 is coupled to an output end of the first AND gate 337 ; another input end of the second AND gate 421 is coupled to the first sensor module 200 ; and further another input end of the second AND gate 421 is coupled to an output end Q 04 of the RS flip-flop 426 .
  • An output end of the second AND gate 421 is coupled to a set end S 3 of the RS flip-flop 425 .
  • An input end of the second AND gate 422 is coupled to the output end of the first NOT gate 335 ; another input end of the second AND gate 422 is coupled to the first sensor module 200 .
  • An output end of the second AND gate 422 is coupled to a set end S 4 of the RS flip-flop 426 .
  • An input end of the first OR gate 427 is coupled to an output end Q 2 of the RS flip-flop 424 ; another input end of the first OR gate 427 is coupled to an output end Q 3 of the RS flip-flop 425 ; and further another input end of the first OR gate 427 is coupled to an output end Q 4 of the RS flip-flop 426 .
  • An output end of the first OR gate 427 is coupled to a reset end R 1 of the RS flip-flop 427 .
  • An input end of the first OR gate 428 is coupled to the output end Q 3 of the RS flip-flop 425 ; another input end of the first OR gate 428 is coupled to the output end Q 4 of the RS flip-flop 426 .
  • An output end of the first OR gate 428 is coupled to a reset end R 2 of the RS flip-flop 424 .
  • an output end Q 02 of the RS flip-flop 424 is coupled to a set end S 1 of the RS flip-flop 423 .
  • the output end Q 4 of the RS flip-flop 426 is coupled to a reset end R 3 of the RS flip-flop 425 .
  • the reset end R 4 of the RS flip-flop 426 is grounded.
  • An output end Q 1 of the RS flip-flop 423 controls the switch element 429 ; the output end Q 2 of the RS flip-flop 424 controls the switch element 430 ; the output end Q 3 of the RS flip-flop 425 controls the switch element 431 ; and the output end Q 4 of the RS flip-flop 426 controls the switch element 432 , so that the voltage divider 433 outputs a corresponding reference current signal V Iref — 1 , a reference current signal V Iref — 2 , a reference current signal V Iref — 3 or a reference current signal V Iref — 4 .
  • FIG. 10A to FIG. 10F are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signals V t1 ⁇ V t4 and the reference current signal V Iref in a case of the holding-current value of the TRIAC is greater than a third preset current signal value.
  • a current drop namely the point H in FIG. 10A
  • the first sensor module 200 outputs a sense signal V cd (namely a pulse signal in FIG.
  • the first sensor module 200 is used to detect a sudden drop time of the current detector signal V CS .
  • the comparator 330 receives the current detector signal V CS and outputs a comparison signal V C1 after comparing the current detector signal V CS with a first preset current signal V p1 .
  • the first NOT gate 333 receives the comparison signal V C1 and outputs a reversed phase of the comparison signal V C1 to the first AND gate 336 .
  • the comparator 331 receives the current detector signal V CS and outputs a comparison signal V C2 to the first AND gate 336 and the first NOT gate 334 after comparing the current detector signal V CS with a second preset current signal V p2 .
  • the first NOT gate 334 receives the comparison signal V C2 and outputs a reversed phase of the comparison signal V C2 to the first AND gate 337 .
  • the comparator 332 receives the current detector signal V CS and outputs a comparison signal V V3 to the first AND gate 337 and the first NOT gate 335 after comparing the current detector signal V CS with a third preset current signal V p3 .
  • the first NOT gate 335 receives the comparison signal V C3 and outputs a critical current signal V t4 to the second AND gate 422 .
  • the first AND gate 336 outputs a critical current signal V t2 to the second AND gate 420 according to the reversed phase of the comparison signal V C1 and the comparison signal V C2 .
  • the first AND gate 337 outputs a critical current signal V t3 to the second AND gate 421 according to the reversed phase of the comparison signal V C2 and the comparison signal V C3 .
  • the third preset current signal V p3 is greater than the second preset current signal V p2
  • the second preset current signal V p2 is greater than the first present current signal V p1 .
  • the critical current signal V t4 When the current detector signal V CS is greater than the third preset current signal V p3 , the critical current signal V t4 is at a high level.
  • the second AND gate 422 When the critical current signal V t4 is at the high level and the first sensor module 200 outputs the sense signal V cd , the second AND gate 422 outputs the high level to the set end S 4 of the RS flip-flop 426 , so that the output end Q 4 of the RS flip-flop 426 outputs the high level, the output end Q 3 of the RS flip-flop 425 outputs a low level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the low level.
  • the switch element 432 Since the output end Q 4 of the RS flip-flop 426 outputs the high level, the output end Q 3 of the RS flip-flop 425 outputs the low level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the low level, the switch element 432 is actuated, and therefore the voltage divider 433 outputs the corresponding reference current signal V Iref — 4 .
  • FIG. 11A to FIG. 11F are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signals V t1 ⁇ V t4 and the reference current signal V Iref in a case of the holding-current value of the TRIAC being between a second preset current signal and a third preset current signal.
  • the current detector signal V CS is greater than the second preset current signal V p2 and smaller than the third preset current signal V p3 , the critical current signal V t4 is at the low level and the critical current signal V t3 is at the high level.
  • the second AND gate 422 When the critical current signal V t3 is at the high level and the first sensor module 200 outputs the sense signal V cd , the second AND gate 422 outputs the low level to the set end S 4 of the RS flip-flop 426 , so that the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the high level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the low level.
  • the switch element 431 Since the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the high level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the low level, the switch element 431 is actuated, and therefore the voltage divider 433 outputs the corresponding reference current signal V Iref — 3 .
  • FIG. 12A to FIG. 12F are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signals V t1 ⁇ V t4 and the reference current signal V Iref in a case of the holding-current value of a TRIAC being between a first preset current signal and a second preset current signal.
  • the critical current signal V t4 is at the low level
  • the critical current signal V t3 is at the low level
  • the critical current signal V t2 is at the high level.
  • the second AND gate 422 When the critical current signal V t2 is at the high level and the first sensor module 200 outputs the sense signal V cd , the second AND gate 422 outputs the low level to the set end S 4 of the RS flip-flop 426 , so that the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the low level, the output end Q 2 of the RS flip-flop 424 outputs the high level, and the output end Q 1 of the RS flip-flop 423 outputs the low level.
  • the switch element 430 Since the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the low level, the output end Q 2 of the RS flip-flop 424 outputs the high level, and the output end Q 1 of the RS flip-flop 423 outputs the low level, the switch element 430 is actuated, and therefore the voltage divider 433 outputs the corresponding reference current signal V Iref — 2 .
  • FIG. 13A to FIG. 13F are respectively time-sequence oscillograms of the current detector signal V CS , the sense signal V cd , the critical current signals V t1 -V t4 and the reference current signal V Iref in a case of the holding-current value of the TRIAC being smaller than a first preset current signal.
  • the current detector signal V CS is smaller than the first preset current signal V p1
  • the critical current signal V t4 is at the low level
  • the critical current signal V t3 is at the low level
  • the critical current signal V t2 is at the low level.
  • the second AND gate 422 When the critical current signal V t2 is at the low level and the first sensor module 200 outputs the sense signal V cd , the second AND gate 422 outputs the low level to the set end S 4 of the RS flip-flop 426 , so that the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the low level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the high level.
  • the switch element 429 Since the output end Q 4 of the RS flip-flop 426 outputs the low level, the output end Q 3 of the RS flip-flop 425 outputs the low level, the output end Q 2 of the RS flip-flop 424 outputs the low level, and the output end Q 1 of the RS flip-flop 423 outputs the high level, the switch element 429 is actuated, and therefore the voltage divider 433 outputs the corresponding reference current signal V Iref — 1 .
  • the design of the counter, decoder and preset threshold voltage selecting circuit may be used to achieve the same effect.
  • references may be made to the following description of the third embodiment and the fourth embodiment.
  • FIG. 14 is a schematic structural view of a circuit of a auto-selecting holding current circuit according to a third embodiment of the disclosure.
  • the first sensor module 200 and the reference voltage selecting circuit 400 are the same as those in the first embodiment, and a second sensor module 300 comprises a comparator 350 , a counter 360 , a decoder 370 and a preset threshold voltage selecting circuit 380 .
  • the comparator 350 receives a current detector signal V CS , and outputs a comparison signal V C after comparing the current detector signal V CS with a critical current signal V th (namely a critical current signal V t1 or a critical current signal V t2 , in which the critical current signal V t2 is greater than the critical current signal V t1 ).
  • the counter 360 performs cycle count and receives the comparison signal V C to output a count value in real time.
  • the decoder 370 continuously receives the count value from the counter 360 and outputs a state signal (in this embodiment, the state signal is an output of an output end Q nb of the second NOT gate 372 ).
  • the preset threshold voltage selecting circuit 380 continuously receives the state signals output by the decoder 370 and outputs the critical current signal V th .
  • the counter 360 may also comprise a T flip-flop 362 .
  • the embodiment is not intended to limit the disclosure; that is to say, the counter 360 may also comprise a D flip-flop.
  • a clock end CLK of the T flip-flop 362 is coupled to an output end of the comparator 350 .
  • An input end T n of the T flip-flop 362 is coupled to a voltage V G which is at a high level.
  • the decoder 370 comprises a second NOT gate 372 .
  • the preset threshold voltage selecting circuit 380 comprises a voltage dividing unit 382 , a switch element 384 and a switch element 386 .
  • An output end of the counter 360 namely an output end Q n of the T flip-flop 362
  • an output end Q nb of the second NOT gate 372 respectively control the switch element 384 and the switch element 386 , so that the voltage dividing unit 382 outputs the corresponding critical current signal V th .
  • the critical current signal is preset to V t2 , and the output end Q n of the T flip-flop 362 is preset to a low level and the output end Q nb of the second NOT gate 372 is preset to a high level, so the switch element 386 is actuated and switch element 384 is opened.
  • the comparator 350 receives the current detector signal V CS , and outputs the comparison signal V C after comparing the current detector signal V CS and the critical current signal V t2 .
  • the comparison signal V C is at the high level (that is, the current detector signal V CS is smaller than the critical current signal V t2 )
  • the output end Q n of the T flip-flop 362 is at the high level
  • the output end Q nb of the second NOT gate 372 is at the low level, so that the switch element 384 is actuated, the switch element 386 is opened, and the voltage dividing unit 382 outputs the corresponding critical current signal V t1 .
  • the switch element 386 When the comparison signal V C is at the low level (that is, the current detector signal V CS is greater than the critical current signal V t1 ), the output end Q n of the T flip-flop 362 is at the low level (that is, the state signal Q n is at the low level) and the output end Q nb of the second NOT gate 372 is at the high level, so that the switch element 386 is actuated, the switch element 384 is opened, and the voltage dividing unit 382 outputs the corresponding critical current signal V t2 . Therefore, the switch element 384 and the switch element 386 can be actuated in order.
  • the second sensor module 300 comprises two types of critical current signals. However, the second sensor module 300 may also comprise more than two types of critical current signals.
  • an auto-selecting holding current circuit 100 provides four types of critical current signals. The fourth embodiment is not intended to limit the disclosure. The embodiments of the auto-selecting holding current circuit 100 may also accordingly provide three types or more than four types of reference current signals.
  • FIG. 15A and FIG. 15B are respectively schematic structural views of circuits of a comparator, a counter, a decoder and a preset threshold voltage selecting circuit of a auto-selecting holding current circuit according to a fourth embodiment of the disclosure.
  • the first sensor module 200 and the reference voltage selecting circuit 400 are the same as those in the second embodiment
  • a second sensor module 300 comprises a comparator 350 , a counter 360 , a decoder 370 and a preset threshold voltage selecting circuit 380 .
  • the comparator 350 receives a current detector signal V CS , and outputs a comparison signal V C after comparing the current detector signal V CS with a critical current signal V th .
  • the counter 360 performs cycle count and receives the comparison signal V C , so as to output a count value C o in real time.
  • the decoder 370 continuously receives the count value C o and outputs a state signal (in this embodiment, the state signal is V b1 , V b2 , V b3 or V b4 ).
  • the preset threshold voltage selecting circuit 380 continuously receives the state signal and outputs the critical current signal V th (namely, one of the critical current signal V t1 , the critical current signal V t2 , the critical current signal V t3 and the critical current signal V t4 , wherein the critical current signal V t4 is greater than the critical current signal V t3 , the critical current signal V t3 is greater than the critical current signal V t2 , and the critical current signal V t2 is greater than the critical current signal V t1 ).
  • the counter 360 comprises a T flip-flop 365 and a T flip-flop 366 .
  • a clock end CLK 1 of the T flip-flop 365 is coupled to an output end of the comparator 350 ; an output end Q n1 of the T flip-flop 365 is coupled to a clock end CLK 2 of the T flip-flop 366 , and an input end T n1 of the T flip-flop 365 and an input end T n2 of the T flip-flop 366 are coupled to a voltage source V G which is at a high level.
  • the decoder 370 comprises a second NOT gate 374 , a second NOT gate 375 , a third AND gate 376 , a third AND gate 377 , a third AND gate 378 and a third AND gate 379 .
  • An input end of the second NOT gate 374 is coupled to an output end Q 1 of the T flip-flop 365
  • an output end Q 1b of the second NOT gate 374 is coupled to an input end of the third AND gate 378 and an input end of the third AND gate 379 .
  • An input end of the second NOT gate 375 is coupled to an output end Q 2 of the T flip-flop 366 , and an output end Q 2b of the second NOT gate 375 is coupled to an input end of the third AND gate 377 and an input end of the third AND gate 379 .
  • the output end Q 1 of the T flip-flop 365 is coupled to an input end of the third AND gate 376 and an input end of the third AND gate 377 .
  • the output end Q 2 of the T flip-flop 366 is coupled to an input end of the third AND gate 376 and an input end of the third AND gate 378 .
  • the preset threshold voltage selecting circuit 380 comprises a voltage dividing unit 75 , a switch element 76 , a switch element 77 , a switch element 78 and a switch element 79 .
  • An output end of the third AND gate 376 , an output end of the third AND gate 377 , an output end of the third AND gate 378 and an output end of the third AND gate 379 respectively control the voltage dividing unit 75 , the switch element 76 , the switch element 77 , the switch element 78 and the switch element 79 , wherein the output end of the third AND gate 376 is used for output the state signal V b4 , the output end of the third AND gate 377 is used for output the state signal V b3 , the output end of the third AND gate 378 is used for output the state signal V b2 and the output end of the third AND gate 379 is used for output the state signal V b1 .
  • the critical current signal is preset to V t4
  • the output end Q 1 of the T flip-flop 365 is preset to the low level
  • the output end Q 2 of the T flip-flop is preset to the low level, so the switch element 79 is actuated.
  • the comparator 350 receives the current detector signal V CS , and outputs the comparison signal V C after comparing the current detector signal V CS and the critical current signal V t4 .
  • the comparison signal V C is at the high level (that is, the current detector signal V CS is smaller than the critical current signal V t4 )
  • the output end Q 1 of the T flip-flop 365 is at the high level
  • the output end Q 2 of the T flip-flop 366 is at the low level, so that the switch element 78 is actuated, and the voltage dividing unit 382 outputs the corresponding critical current signal V t3 .
  • the comparison signal V C is at the high level (that is, the current detector signal V CS is smaller than the critical current signal V t3 )
  • the output end Q 1 of the T flip-flop 365 is at the low level
  • the output end Q 2 of the T flip-flop 366 is at the high level, so that the switch element 77 is actuated, and the voltage dividing unit 382 outputs the corresponding critical current signal V t2 .
  • the comparison signal V C is at the high level (that is, the current detector signal V CS is smaller than the critical current signal V t2 )
  • the output end Q 1 of the T flip-flop 365 is at the high level
  • the output end Q 2 of the T flip-flop 366 is at the high level, so that the switch element 76 is actuated, and the voltage dividing unit 382 outputs the corresponding critical current signal V t1 .
  • the switch element 76 , the switch element 77 , the switch element 78 and the switch element 79 can be actuated in order.
  • the auto-selecting holding current circuit is applicable to a converter of any type.
  • the reference voltage selecting circuit obtains a holding-current value range of the TRIAC to output the corresponding reference current signal to the bleeder circuit, so that the bleeder circuit dynamically adjusts a pulse modulation signal to maintain the normal operation of the TRIAC.
  • the second sensor module may output the critical current signal through the design of the counter, decoder and preset threshold voltage selecting circuit.

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  • Measurement Of Current Or Voltage (AREA)
  • Inverter Devices (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Electronic Switches (AREA)
  • Power Conversion In General (AREA)
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JP2013016461A (ja) 2013-01-24
EP2544512A1 (de) 2013-01-09
KR20130006271A (ko) 2013-01-16
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JP5301003B2 (ja) 2013-09-25

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