US8214189B2 - Performance evaluation simulation - Google Patents

Performance evaluation simulation Download PDF

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US8214189B2
US8214189B2 US12/314,334 US31433408A US8214189B2 US 8214189 B2 US8214189 B2 US 8214189B2 US 31433408 A US31433408 A US 31433408A US 8214189 B2 US8214189 B2 US 8214189B2
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performance evaluation
unit
throughput
basic process
evaluation simulation
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US20090204380A1 (en
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Tomoki Kato
Nobukazu Koizumi
Noriyasu Nakayama
Naoki Yuzawa
Hiroyuki Hieda
Satoshi Hiramoto
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Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3457—Performance evaluation by simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold

Definitions

  • the present invention relates to a performance evaluation simulation performed on a software model and a hardware model for which process to be performed are provisionally determined from system specifications by using software and hardware, respectively, for performance evaluation.
  • a processor, a bus, a memory, and other components for use in electronic equipment are implemented on one LSI (Large Scale Integration) and, on that LSI (system LSI), a plurality of processes are performed.
  • LSI Large Scale Integration
  • system LSI system LSI
  • Such implementation of a plurality of processes on one LSI is for the purpose of downsizing the LSI and reducing cost and consumption power, for example.
  • an easy change is difficult, thereby increasing the difficulty in designing the functions of the LSI.
  • SW software
  • HW hardware
  • the software is written in C language, assembly language, or the like, and is executed on an actual machine model including a target processor, which is a processor implemented on the LSI for performance verification, or on an ISS (Instruction Set Simulator) for the target processor, thereby simulating the operation of the software.
  • the hardware is written in RTL (Register Transfer Level) or TLM (Transaction Level Model), which are languages for describing hardware, or in a language obtained by mixing RTM and TLM, thereby simulating the operation of the hardware.
  • Japanese Patent Application Laid-open No. 2001-142927 discloses that source codes completed to some extent are analyzed, and each processing unit is subjected to SW/HW division by taking a value of each processing unit as a determination factor, such as a throughput calculated from the number of clock cycles and an amount of consumed power calculated from the description part of a function.
  • Japanese Patent Application Laid-open No. H11-259552 discloses that architecture descriptions of a system LSI are converted to modules in units of execution to perform SW/HW division and the execution times of the respective modules obtained by executing simulations based on a benchmark program are compared, thereby determining the validity of SW/HW division.
  • a performance evaluation simulation apparatus evaluates performance by performing a simulation on a software model and a hardware model in which a process to be performed is provisionally determined by using software and hardware from specifications of a system.
  • the performance evaluation simulation apparatus includes a basic-process-unit dividing unit that makes a division into basic process units, which are execution units of process to be performed in the software model based on an execution log that represents execution history obtained by executing the software model on an actual machine or simulation software; a throughput calculating unit that calculates a throughput of each of the basic process units obtained through division by the basic-process-unit dividing unit, from the number of instruction address strings or the number of address strings for data access kept in the execution log; an arrangement-structure changing unit that compares each throughput calculated by the throughput calculating unit and a predetermined threshold and changes an arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed from the software model to the hardware model; and a statistical-information generating unit that generates statistical information on which performance evaluation is
  • a performance evaluation simulation method for evaluating performance by performing a simulation on a software model and a hardware model in which a process to be performed is provisionally determined by using software and hardware from specifications of a system.
  • the performance evaluation simulation method includes making a division into basic process units, which are execution units of process to be performed in the software model based on an execution log that represents execution history obtained by executing the software model on an actual machine or simulation software; calculating a throughput of each of the basic process units obtained through the division, from the number of instruction address strings or the number of address strings for data access kept in the execution log; comparing each of the calculated throughputs and a predetermined threshold; changing an arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed from the software model to the hardware model; and generating statistical information on which performance evaluation is based by performing a performance evaluation simulation on the basic process unit whose arrangement structure has been changed by the changing to the hardware model and basic process units arranged in the software model, the performance evaluation simulation executing
  • an electronic apparatus includes a performance evaluation simulation apparatus that performs a simulation on a process executed on software and hardware from specifications of a system and designs an LSI based on performance evaluations obtained by the performance evaluation simulation apparatus.
  • the electronic apparatus includes an accepting unit that accepts a software model and a hardware model; a basic-process-unit dividing unit that makes a division into basic process units, which are execution units of process to be performed in the software model based on an execution log that represents execution history obtained by executing the software model on an actual machine or simulation software; a throughput calculating unit that calculates a throughput of each of the basic process units obtained through division by the basic-process-unit dividing unit, from the number of instruction address strings or the number of address strings for data access kept in the execution log; an arrangement-structure changing unit that compares each throughput calculated by the throughput calculating unit and a predetermined threshold and changes an arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed from the software model to the hardware model; and
  • FIG. 1 is a drawing of general outlines and features of a performance evaluation simulation apparatus according to a first embodiment
  • FIG. 2 is a drawing of the configuration of the performance evaluation simulation apparatus according to the first embodiment
  • FIG. 3 is a drawing of a relation between accesses to addresses and basic process units in the entire execution log according to the first embodiment
  • FIG. 4 is a drawing of an example of statistical information according to the first embodiment
  • FIG. 5 is a drawing of an LSI development flow
  • FIG. 6 is a flowchart of a simulation process of the performance evaluation simulation apparatus according to the first embodiment
  • FIG. 7 is a drawing for explaining a SW/HW division process performed by the performance evaluation simulation apparatus according to the first embodiment
  • FIG. 8 is a drawing of a relation between a time and a CPU throughput when a CPU model periodically performs an event
  • FIG. 9 is a drawing of an event process when part of function modules in the CPU is converted to hardware according to a second embodiment
  • FIG. 10 is a drawing of an example of a UML class according to the second embodiment.
  • FIG. 11 is a drawing of an example of description in System C language according to the second embodiment.
  • FIG. 12 is a drawing of a relation between a degree of abstraction of a hardware model and a simulation process according to the second embodiment
  • FIG. 13 is a drawing for explaining a performance evaluation simulation process according to a third embodiment
  • FIG. 14 is a drawing for explaining a performance evaluation simulation process according to a fourth embodiment
  • FIG. 15 is a drawing of an event process when part of process handlings in the CPU is converted to hardware according to the fourth embodiment
  • FIG. 16 is a drawing for explaining the case where the file size of an execution log is used as the threshold of SW/HW division according to a fifth embodiment
  • FIG. 17 is a drawing for explaining a consideration of conversion to multi-core by using an add-on CPU according to a sixth embodiment.
  • FIG. 18 is a drawing of a computer that executes a performance evaluation simulation program.
  • FIG. 1 is a drawing of general outlines and features of the performance evaluation simulation apparatus according to the first embodiment.
  • This performance evaluation simulation apparatus performs a performance evaluation simulation, with an execution log (instruction strings) as an input.
  • the execution log represents execution history obtained from the results of dividing specifications of a system LSI into a software model and a hardware model and executing the software model obtained through the division on an actual machine or a target CPU using an ISS (Information Storage System) or the like.
  • the general outlines of the performance evaluation simulation apparatus are such that, in the software model and the hardware model, a process to be performed in the software and the hardware is provisionally determined from the specifications of the system, and a performance evaluation is performed on each of the software model and the hardware model.
  • main features of this apparatus are such that SW/HW division can be optimally performed at the initial stage of designing, and the validity of SW/HW division can be determined.
  • the performance evaluation simulation apparatus Based on the execution log representing execution history obtained by executing the software model on an actual machine or simulation software, the performance evaluation simulation apparatus makes a division into basic process units, which are execution units of process to be performed in the software model (refer to ( 1 ) in FIG. 1 ).
  • the performance evaluation simulation apparatus receives an input of an execution log representing execution history obtained from the results of dividing specifications of a system LSI into a software model and a hardware model and executing the software model on an actual machine or a target CPU using an ISS or the like. Then, based on the input execution log, the performance evaluation simulation apparatus makes a division into basic process units, which are execution units of process to be executed in the software model.
  • a division into basic process units in the case of communication process software, for example, after a task starting point of an OS (Operating System) is found from the pattern of a periodic process, a division is made in units of task. Also, for example, after a process flow among object files is tracked from an instruction address string, and a break is found for division.
  • the performance evaluation simulation apparatus calculates the throughput of each basic process unit obtained through division, from the number of instruction address strings or the number of address strings for data access kept in the execution log (refer to ( 2 ) in FIG. 1 ). Specifically, in the example above, the performance evaluation simulation apparatus calculates the throughput of each basic process unit obtained through division from the number of instruction address strings representing branch-destination address information at the time of process execution, the number of address strings for data access representing access-destination address information for accessing a database, or other information kept in the execution log.
  • the performance evaluation simulation apparatus compares each calculated throughput and a predetermined threshold, and changes an arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed from the software model to the hardware model (refer to ( 3 ) in FIG. 1 ). Specifically, in the example above, the performance evaluation simulation apparatus compares each calculated throughput and a predetermined threshold throughput. Then, as a result of comparison, the performance evaluation simulation apparatus changes the arrangement structure so that a basic process unit with an execution log indicating a throughput exceeding the predetermined threshold throughput is changed from software processing to hardware processing so as to be directly connected to a bus, thereby making a conversion to hardware.
  • the performance evaluation simulation apparatus performs a performance evaluation simulation of executing a bus access via an instruction cache and a data cache to measure data required for system operation analysis, thereby generating statistical information on which performance evaluation is based (refer to ( 4 ) in FIG. 1 ).
  • the performance evaluation simulation apparatus performs a performance evaluation simulation by executing a bus access via an instruction cache and a data cache.
  • the performance evaluation simulation apparatus measures an instruction execution time, an instruction fetch time, and a data access time, thereby generating statistical information on which performance evaluation is based, such as a CPU load factor.
  • the statistical information generated by this performance evaluation simulation apparatus is used in determining the validity of optimal SW/HW division.
  • highly-accurate simulation results can be obtained.
  • the performance evaluation simulation apparatus performs a performance evaluation simulation based on the execution log obtained from the results of executing the software model on the actual machine or on the target CPU by using the ISS or the like, among the basic process units obtained through division based on the information kept in the execution log, a basic process unit having a large throughput is converted to hardware for execution of the simulation.
  • SW/HW division can be optimally performed at the initial stage of designing and the validity of SW/HW division can be determined.
  • the performance evaluation simulation apparatus performs SW/HW division for each process by using the information kept in the execution log. Therefore, compared with the case as in the conventional technology where SW/HW division is performed depending on the degree of completion for each process implemented on the LSI, SW/HW division can be optimally performed at the initial stage of designing. Also, while measuring an instruction execution time, an instruction fetch time, and a data access time, the performance evaluation simulation apparatus performs a simulation by executing a bus access via an instruction cache and a data cache to output highly-accurate statistical information, such as a CPU load factor. Therefore, compared with the case as in the conventional technology where the process times of the respective execution units are compared each other, the validity of SW/HW division can be determined.
  • FIG. 2 is a drawing of the configuration of the performance evaluation simulation apparatus according to the first embodiment.
  • a performance evaluation simulation apparatus 10 includes function modules 11 - 1 to 11 - n , a scheduler unit 20 , and an access processing unit 21 .
  • the performance evaluation simulation apparatus 10 is connected via a bus 30 to the external RAM, which is a RAM connected outside of the performance evaluation simulation apparatus 10 , and peripheral HW including, for example, an external I/F (interface) and dedicated hardware for a specific purpose.
  • peripheral HW including, for example, an external I/F (interface) and dedicated hardware for a specific purpose.
  • portions other than a basic process execution log are constructed at a transaction level using the System C language, which is one of hardware description languages for the purpose of use in designing electronic circuitry. Transmission and reception between modules are performed with function calls.
  • the connection to the bus 30 is performed by using an interface common to the modules (for example, TLM-I/F).
  • the function modules 11 - 1 to 11 - n represent basic process units, which are execution units of process to be performed by the access processing unit 21 in the software model obtained through division based on the execution log.
  • the function module 11 - 1 (Fn[ 1 ]) retains, as depicted in FIG. 3 , an address “E050D6E0”, instruction/data access “I/D”, and load (read)/store (write) “R/W” in the case of data access.
  • an address to be accessed is known, which address is accessed can be known from the RAM storing each hardware address and data.
  • FIG. 3 is a drawing of a relation between accesses to addresses and basic process units in the entire execution log according to the first embodiment.
  • the access processing unit 21 Based on the execution log representing execution history obtained by executing the software model on the actual machine or simulation software, the access processing unit 21 makes a division into basic process units, which are execution units of process to be executed in the software model. The access processing unit 21 then calculates the throughput of each basic process unit obtained through division from the number of instruction address strings or the number of address strings for data access kept in the execution log. Thereafter, the access processing unit 21 compares each calculated throughput and a predetermined threshold, and changes an arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed from the software model to the hardware model. Then, the basic process unit whose arrangement structure has been changed to the hardware model and the basic process units arranged in the software model, the access processing unit 21 performs a performance evaluation simulation of executing a bus access via the instruction cache and the data cache.
  • a specific example is as follows. Based on the execution log, the access processing unit 21 makes a division into basic process units, which are execution units of process to be executed in the software model. The access processing unit 21 then calculates the throughput of each basic process unit obtained through division from the number of instruction address strings representing branch-destination address information at the time of process execution, the number of address strings for data access representing access-destination address information for accessing a database, or other information kept in the execution log.
  • the access processing unit 21 compares each calculated throughput and a predetermined threshold, and changes the arrangement structure so that a basic process unit with an execution log indicating a throughput exceeding the predetermined threshold throughput is changed from software processing to hardware processing so as to be directly connected to the bus 30 , thereby making a conversion to hardware. Then, when accepting a request for process handling from the scheduler unit 20 , the access processing unit 21 performs, on the basic process unit whose arrangement structure has been changed to the hardware model for conversion to hardware, a performance evaluation simulation by executing a bus access via the instruction cache (I-cache) and the data cache (D-cache), while measuring an instruction execution time, an instruction fetch time, and a data access time.
  • I-cache instruction cache
  • D-cache data cache
  • the scheduler unit 20 generates, from the simulation process executed by the access processing unit 21 , statistical information on which performance evaluation is based. Specifically, in the example above, with an event that occurred as a trigger, the scheduler unit 20 requests a corresponding function module (basic process unit) for process handling. From the simulation results obtained by the access processing unit 21 , the scheduler unit 20 then generates statistical information on which performance evaluation is based, such as a CPU load factor.
  • This statistical information has stored therein, as depicted in FIG. 4 , for example, an instruction execution time of “100 nanoseconds”, an instruction fetch time of “3 nanoseconds”, a data access time of “2 nanoseconds”, and a CPU load factor of “30%” every basic process unit “Fn[ 1 ]”.
  • the access processing unit 21 manages port IDs (IDentifiers) of interfaces connected to the external RAM, the peripheral HW, and others via the bus 30 and block IDs of the function modules 11 - 1 to 11 - n in a unified manner, and knows the order of the function modules in which they requests of the access processing unit 21 process handling and also knows the arrangement of the function modules.
  • FIG. 4 is a drawing of an example of statistical information according to the first embodiment.
  • FIG. 5 is a drawing of the LSI development flow.
  • this flow is to design the entire LSI including the process of the performance evaluation simulation apparatus according to the first embodiment.
  • a system request is analyzed from the generated specifications (step S 602 ). Then, from the analyzed system request, a scheme of considering an algorism is designed (step S 603 ). Then, with performance evaluation and consideration of SW/HW division, architecture is designed (step S 604 ). Thereafter, an RTL logical design is performed on a hardware part (step S 605 ), and then a physical design of that hardware is performed (step S 606 ). Also, software development is performed on the software part (step S 607 ). Then, the hardware and the software are combined to generate an actual machine model (step S 608 ), and then a product is shipped (step S 609 ).
  • FIG. 6 is a flowchart of the simulation process of the performance evaluation simulation apparatus 10 according to the first embodiment.
  • the process explained in FIG. 6 is part of the architecture designing at step S 604 depicted in FIG. 5 .
  • the performance evaluation simulation apparatus 10 divides the specifications into software processing and hardware processing (step S 102 ), and then outputs provisional software, which is a software model, and an operational model, which is a hardware model (steps S 103 and S 104 ).
  • provisional software which is a software model
  • an operational model which is a hardware model
  • step S 103 and S 104 Upon output of an execution log representing execution history obtained from the results of executing the output provisional software on the actual machine or the target CPU using the ISS or the like (steps S 105 and S 106 ), based on the execution log, a division is made into basic process units, which are execution units of process to be performed in the software model (step S 107 ).
  • the performance evaluation simulation apparatus 10 calculates the throughput of each basic process unit obtained through division from the number of instruction address strings representing branch-destination address information at the time of process execution, the number of address strings for data access representing access-destination address information for accessing a database, or other information kept in the execution log (step S 108 ).
  • the performance evaluation simulation apparatus 10 compares each calculated throughput and a predetermined threshold (step S 109 ). Then, as a result of comparison, the performance evaluation simulation apparatus 10 changes the arrangement structure so that a basic process unit with an execution log indicating a throughput exceeding the predetermined threshold throughput is changed from software processing to hardware processing so as to be directly connected to a bus, thereby making a conversion to hardware (step S 110 ).
  • the performance evaluation simulation apparatus 10 searches for a function module corresponding to the basic process unit with the throughput exceeding the predetermined threshold throughput based on the block ID, thereby changing the arrangement structure of that function module. That is, the performance evaluation simulation apparatus 10 moves the function module from inside of the CPU to a port capable of direct bus connection, thereby converting the work of the function module from software processing by the CPU to hardware.
  • the performance evaluation simulation apparatus 10 performs a performance evaluation simulation by executing a bus access via the instruction cache and the data cache, while measuring an instruction execution time, an instruction fetch time, and a data access time. Thereafter, from the instruction execution time, the instruction fetch time, and the data access time, the performance evaluation simulation apparatus 10 generates statistical information on which performance evaluation is based, such as a CPU load factor (step S 111 ).
  • FIG. 7 is a drawing for explaining the SW/HW division process performed by the performance evaluation simulation apparatus 10 according to the first embodiment.
  • the performance evaluation simulation apparatus 10 determines a throughput threshold (predetermined threshold) serving as a SW/HW division condition for the basic process unit (step S 201 ). The performance evaluation simulation apparatus 10 then counts the number of instruction address strings and the number of address strings for data access kept in the execution log for the basic process unit obtained through division, and calculates the throughput of the basic process unit from either one of these counts (or from total counts) (steps S 202 to S 204 ).
  • a throughput threshold predetermined threshold
  • the performance evaluation simulation apparatus 10 then counts the number of instruction address strings and the number of address strings for data access kept in the execution log for the basic process unit obtained through division, and calculates the throughput of the basic process unit from either one of these counts (or from total counts) (steps S 202 to S 204 ).
  • the performance evaluation simulation apparatus 10 searches for the basic process unit corresponding to the execution log exceeding the threshold based on the block ID (step S 206 ). Then, the performance evaluation simulation apparatus 10 allocates the found basic process unit to a port capable of direct bus connection, and changes the port ID according to the change of the arrangement structure of the basic process unit to hardware (steps S 207 and S 208 ).
  • the performance evaluation simulation apparatus 10 does not require a cache access to the basic process unit converted to hardware, and requires a direct access to the RAM. However, since no instruction fetch is required for the execution log, an instruction address string is deleted, and only the data access is extracted in performing a simulation (steps S 209 and S 210 ).
  • the performance evaluation simulation apparatus 10 uses information kept in the execution log to perform SW/HW division for each process. Also, the performance evaluation simulation apparatus 10 performs a simulation by executing a bus access via the instruction cache and the data cache, while measuring the instruction execution time, the instruction fetch time, and the data access time. Therefore, SW/HW division can be optimally performed at the initial stage of designing, and the validity of SW/HW division can be determined.
  • the performance evaluation simulation apparatus 10 calculates the throughput of each basic process unit based on either one of the number of instruction address strings or the number of address strings for data access kept in the execution log, or the total numbers thereof, and then changes the arrangement structure so that a basic process unit with a throughput exceeding the predetermined threshold is changed to a hardware model.
  • the basic process unit whose arrangement structure has been changed to the hardware model and the basic process units arranged in the software model, the performance evaluation simulation apparatus 10 then performs a performance evaluation simulation of executing a bus access via the instruction cache and the data cache to generate statistical information, such as the instruction execution time, the instruction fetch time, and the data access time.
  • the performance evaluation simulation apparatus 10 can optimally perform SW/HW division at the initial stage of designing, and can also determine the validity of SW/HW division.
  • FIG. 8 is a drawing of a relation between a time and a CPU throughput when the CPU model periodically performs an event.
  • FIG. 9 is a drawing of an event process when part of function modules in the CPU is converted to hardware according to the second embodiment.
  • FIG. 10 is a drawing of an example of a UML class according to the second embodiment.
  • FIG. 11 is a drawing of an example of description in System C language according to the second embodiment.
  • FIG. 12 is a drawing of a relation between degrees of abstraction of a hardware model and a simulation process according to the second embodiment.
  • the configuration, functions, and others of the performance evaluation simulation apparatus according to the second embodiment are similar to those according to the first embodiment, and therefore are not explained herein.
  • each basic process unit is formed of a whitebox portion having described therein a function unique to each basic process unit according to a process handling unit with combination of plurality of basic process units, and a blackbox portion where a process for collecting statistical information is performed.
  • process handling is a process of executing a plurality of basic process units in combination, whilst an event is formed of a combination of process handlings including processes of only basic process units.
  • the performance evaluation simulation apparatus 10 calls basic process units Fn[ 1 ] and Fn[ 2 ] sequentially. Then, when a periodic event B occurs, with the event B as a trigger, the performance evaluation simulation apparatus 10 calls basic process units Fn[ 2 ], Fn[ 3 ], Fn[ 1 ] sequentially. Then, when a periodic event C occurs, with the event C as a trigger, the performance evaluation simulation apparatus 10 calls the basic process unit Fn[ 1 ].
  • the function module which is a basic process unit
  • statistical information is collected by the blackbox portion, such as the instruction execution time, the instruction fetch time, and the data access time.
  • the process time for the basic process is determined by “whitebox+blackboxxthe number of calls” and, the longer the process time takes, the larger the CPU throughput.
  • a level of priority is provided so that a process is performed with a collision in time being avoided.
  • FIG. 9 an event process when part of the function modules in the CPU is converted to hardware is explained.
  • the configuration of each basic process unit and others are similar to those depicted in FIG. 8 , and therefore are not explained herein, and an event process when a basic process unit with a large throughput is converted to hardware is explained.
  • the performance evaluation simulation apparatus 10 changes the arrangement structure of the basic process unit Fn[ 3 ] with a throughput exceeding the predetermined threshold to hardware.
  • the process time of the basic process unit Fn[ 3 ] converted to hardware is reduced, and also the CPU throughput for the entire event B is reduced.
  • the performance evaluation simulation apparatus 10 converts the function module with a large load to hardware, thereby reducing the CPU throughput. Also, since the function module converted to hardware directly accesses the RAM, an instruction execution string is not required, and the address range for data access is also restricted. Therefore, the time is reduced compared with the case of accessing the D-cache (the cache for use at the time of data access), thereby reducing the process time of the blackbox portion and further reducing the process time of the entire process handling.
  • the threshold for SW/HW division should be set in consideration of an increase of an implementation area for conversion to hardware, an increase in power consumption, an increase in bus occupancy, and others.
  • FIGS. 10 and 11 an example of a UML class and an example of description in System C language according to the second embodiment are explained. Also, by using FIG. 12 , a relation between a degree of abstraction of the hardware model and a simulation process according to the second embodiment is explained.
  • “Fn_*” represents a function module
  • “Fn_if” represents a function-module common interface
  • “Fn_*.h” represents a header portion of each function module
  • Fn_*.cpp” represents source code
  • Fn_if.h represents a header portion of the function-module common interface
  • Fn_if.cpp represents source code.
  • the blackbox portion for performing a process for collecting statistical information is placed in the function-module common interface, and the whitebox portion in which a function unique to each module is described according to the purpose of performance verification and the degree of completion of the hardware model is placed in a process handling of “do_process( )” in each function module.
  • each function module “Fn_*” instructed for the process handling of “do_process( )” from the scheduler unit executes the whitebox portion. Thereafter, the whitebox portion executes the function unique to each module, and then an argument “x” determined for each module is given to call a function of “blackbox( )”. Then, based on the argument “x”, the blackbox portion obtains the execution log of the basic process unit, the number of processes of instruction fetch and/or data access is specified from the execution log to cause a load to occur on the CPU, and also statistical information is collected, such as the instruction execution time.
  • the performance evaluation simulation apparatus 10 provides a CPU load irrespectively of execution of the function unique to each basic process unit. Therefore, cache analysis and obtainment of CPU statistical information and the like can be performed.
  • the performance evaluation simulation apparatus 10 can perform a performance evaluation simulation and optimum consideration of SW/HW division even the degree of abstraction of the hardware model according to the progress of LSI designing.
  • the throughput of the basic process unit in SW/HW division and the predetermined threshold are compared each other to perform a simulation.
  • the present invention is not meant to be restricted to this.
  • the predetermined threshold of the basic process unit in SW/HW division can be changed with the CPU load factor, and then the predetermined threshold and the throughput can be compared each other to perform a simulation.
  • FIG. 13 is a drawing for explaining the performance evaluation simulation process according to the third embodiment.
  • a performance evaluation simulation is performed with all function modules being contained in the target processor to correlate the number of times of instruction execution, the number of times of data loading, and the number of times of data storing in the execution log, and the CPU determination condition (for example, the CPU load factor and the bus occupancy).
  • the performance evaluation simulation apparatus 10 sets a threshold for determining a CPU performance based on the CPU load factor or the like (step S 301 ) to determine a predetermined threshold for the basic process unit, which is a SW/HW division condition (step S 302 ). Then, as with the first embodiment, the performance evaluation simulation apparatus 10 counts the number of instruction address strings, the number of address strings for data access, and others kept in the execution log obtained through division into basic process units, and then calculates the throughput of the basic process unit from either one of these counts (or from total counts) (steps S 303 to S 305 ).
  • the performance evaluation simulation apparatus 10 searches for a basic process unit corresponding to the execution log with a threshold exceeding the threshold based on the block ID (step S 307 ). Then, the performance evaluation simulation apparatus 10 allocates the found basic process unit to a port capable of direct bus connection, and changes the port ID according to the change of the arrangement structure of the basic process unit to hardware (steps S 308 and S 309 ).
  • the performance evaluation simulation apparatus 10 does not require a cache access to the basic process unit converted to hardware, and requires a direct access to the RAM. However, since no instruction fetch is required for the execution log, an instruction address string is deleted, and only the data access is extracted in performing a simulation (steps S 310 and S 311 ). Then, when the CPU-performance determination condition is not satisfied (“Yes” at step S 312 ), the procedure returns to step S 302 , where the performance evaluation simulation apparatus 10 determines (corrects) the threshold of throughput of the basic process unit.
  • the correction range of the threshold of the throughput of the basic process unit may be calculated from a correlation between the throughput of the execution log found in advance and the CPU-performance determination condition.
  • the function modules may be converted to hardware one by one in decreasing (or increasing) order of basic process unit to perform a simulation until the CPU-performance determination condition is satisfied.
  • the performance evaluation simulation apparatus 10 changes the determination threshold of the basic process unit. With this, a more highly-accurate simulation can be performed to determine the validity of SW/HW division.
  • the throughput of the basic process unit in SW/HW division and the predetermined threshold are compared each other to perform a simulation.
  • the present invention is not meant to be restricted to this.
  • the predetermined threshold of the process handling unit in SW/HW division can be changed with the CPU load factor, and then the predetermined threshold and the throughput can be compared each other to perform a simulation.
  • FIG. 14 is a drawing for explaining the performance evaluation simulation process according to the fourth embodiment.
  • FIG. 15 is a drawing of an event process when part of process handling in the CPU is converted to hardware according to the fourth embodiment.
  • the number of times of instruction execution and the number of times of data access in the execution log and the CPU determination condition are correlated in advance.
  • the performance evaluation simulation apparatus 10 sets a threshold for determining a CPU performance based on the CPU load factor or the like (step S 401 ) to determine a predetermined threshold for the process handling unit, which is a SW/HW division condition (step S 402 ). Then, as with the first embodiment, the performance evaluation simulation apparatus 10 counts the number of instruction address strings, the number of address strings for data access, and others kept in the execution log obtained through division into basic process units, and then calculates the throughput of the process handling unit from either one of these counts (or from total counts) (steps S 403 to S 405 ).
  • the performance evaluation simulation apparatus 10 searches for a basic process unit corresponding to the execution log with a threshold exceeding the threshold based on the block ID (step S 407 ). Then, the performance evaluation simulation apparatus 10 allocates the found basic process unit to a port capable of direct bus connection, and changes the port ID according to the change of the arrangement structure of the process handling unit to hardware (steps S 408 and S 409 ).
  • the performance evaluation simulation apparatus 10 does not require a cache access to the process handling unit converted to hardware, and requires a direct access to the RAM. However, since no instruction fetch is required for the execution log, an instruction address string is deleted, and only the data access is extracted in performing a simulation (steps S 410 and S 411 ). Then, when the CPU-performance determination condition is not satisfied (“Yes” at step S 412 ), the procedure returns to step S 402 , where the performance evaluation simulation apparatus 10 determines (corrects) the threshold of throughput of the process handling unit.
  • the correction range of the threshold of the throughput of the process handling unit may be calculated from a correlation between the number of times of instruction execution and the number of times of data access found in advance in the execution log, and the CPU-performance determination condition.
  • the function modules may be converted to hardware one by one in decreasing (or increasing) order of process handling unit to perform a simulation until the CPU-performance determination condition is satisfied.
  • the performance evaluation simulation apparatus 10 changes the arrangement structure of the process handling units Fn[ 3 ] and Fn[ 1 ] with their throughputs exceeding the predetermined threshold to hardware.
  • the process time is reduced, and also the CPU throughput in the entire event B is decreased.
  • the performance evaluation simulation apparatus 10 converts a function module with a large load to hardware by process handling units, thereby reducing the CPU throughput. Also, since the function module converted to hardware directly accesses the RAM, an instruction execution string is not required, and the address range for data access is also restricted. Therefore, the time is reduced compared with the case of accessing the D-cache (the cache for use at the time of data access), thereby reducing the process time of the blackbox portion and further reducing the process time of the entire process handling.
  • the performance evaluation simulation apparatus 10 changes the determination threshold of the process handling unit. With this, a more highly-accurate simulation can be performed to determine the validity of SW/HW division.
  • the predetermined threshold of the basic process unit in SW/HW division can be determined in advance.
  • the present invention is not meant to be restricted to this.
  • the predetermined threshold of the basic process unit in SW/HW division can be determined by using the file size of the execution log.
  • FIG. 16 is a drawing for explaining the case where the file size of the execution log is used as the threshold of SW/HW division according to the fifth embodiment.
  • the performance evaluation simulation apparatus 10 counts the number of instruction address strings and the number of address strings for data access kept in the execution log of the basic process unit obtained through division, performs a simulation with all function modules being contained in the target processor, and, from statistical information obtained by execution of the simulation, calculates the CPU throughput (steps S 501 to S 504 ).
  • the performance evaluation simulation apparatus 10 uses the calculated CPU throughput to correlate the number of times of instruction execution, the number of times of data loading, and the number of times of data storing in the execution log, and the CPU determination condition (for example, the CPU load factor) (step S 505 ).
  • the performance evaluation simulation apparatus 10 then correlates each file size of the execution log obtained through division into basic process units and the number of times of instruction execution and/or the number of times of data access in that file (step S 506 ).
  • the performance evaluation simulation apparatus 10 correlates the CPU throughput and the file size of the execution log of the basic process unit (step S 507 ). Based on the process above, the performance evaluation simulation apparatus 10 takes the file size of the execution log as the threshold of SW/HW division.
  • the performance evaluation simulation apparatus 10 uses the file size of the execution log as the threshold in SW/HW division. With this, a more highly-accurate simulation can be performed to determine the validity of SW/HW division.
  • FIG. 17 is a drawing for explaining a consideration of conversion to multi-core by using an add-on CPU according to the sixth embodiment.
  • a new bus model is configured outside of the performance evaluation simulation device to be subjected to performance evaluation and, on the bus, an ADDON-CPU, an I-cache, a D-cache, and peripheral HW as required are disposed, thereby constructing a performance evaluation simulation environment.
  • the structures of the ADDON-CPU, the I-cache, and the D-cache are similar to these in CPU, and the process is performed so that a port ID and a block ID for managing the arrangement of each module and the process order do not overlap each other.
  • the performance evaluation simulation apparatus 10 separates the relevant function module Fn[n] from the CPU module, places it in the interface in the ADDON-CPU, and changes the port ID of the function module Fn[n]. Then, the statistical information obtained from the simulation execution results is collected individually by the CPU and the ADDON-CPU for cache analysis on effects when the software processing is distributed among a plurality of CPUs.
  • the performance evaluation simulation apparatus 10 distributes and outputs the function modules to be converted to hardware in the CPU based on the threshold to the ADDON-CPU.
  • the output is in a form of software ⁇ software.
  • the performance evaluation simulation apparatus 10 distributes and outputs the function modules to be converted to hardware in the CPU based on the threshold of SW/HW division to the ADDON-CPU. With this, multi-core where a plurality of CPU core is present in one CPU can be considered.
  • the process procedure, the control procedure, and the information including specific names and various data and parameters can be arbitrarily change unless otherwise specified.
  • each component of each apparatus depicted is conceptual in function, and is not necessarily physically configured as depicted. That is, the specific patterns of distribution and unification of each apparatus are not meant to be restricted to those depicted in the drawings.
  • the access processing unit 21 may be distributed into a basic-process-unit dividing unit that makes a division into basic process units based on an execution log, a throughput calculating unit that calculates a throughput of each basic process unit, an arrangement-structure changing unit that changes an arrangement structure so that a basic process unit is changed to hardware, and a simulation performing unit that performs a performance evaluation simulation.
  • all or part of the components can be functionally or physically distributed or unified in arbitrary units according to various loads and the state of use.
  • all or arbitrary part of the process function performed in each apparatus can be achieved by a CPU and a program analyzed and executed on that CPU, or can be achieved as hardware with a wired logic.
  • the performance evaluation simulation apparatus for performing optimal SW/HW division for a software model and a hardware model is explained.
  • the present invention is not meant to be restricted to this.
  • an electronic apparatus with the performance evaluation simulation apparatus being included as one design process can be thought for processing.
  • such an electronic apparatus accepts a software model and a hardware model in which a process to be performed is provisionally determined by using software and hardware from specifications of a system, and uses the accepted software model and hardware model to implement software and hardware obtained through re-division on an LSI, based on statistical information generated by performing such a performance evaluation simulation as explained above.
  • FIG. 18 is a drawing of a computer that executes a performance evaluation simulation program.
  • a computer 110 as a performance evaluation simulation apparatus includes an HDD 130 , a CPU 140 , a ROM 150 , and a RAM 160 that are connected each other via a bus 180 .
  • performance evaluation simulation programs that achieve functions similar to those of the performance evaluation simulation apparatus 10 explained in the first embodiment are stored in advance: That is, as depicted in FIG. 18 , those programs stored in advance are a basic-process-unit dividing program 150 a , a throughput calculating program 150 b , an arrangement-structure changing program 150 c , and a statistical-information generating program 150 d .
  • these programs 150 a to 150 d may be unified or distributed as appropriated.
  • the CPU 140 reads these programs 150 a to 150 d from the ROM 150 for execution.
  • they become functioning as a basic-process-unit dividing process 140 a , a throughput calculating process 140 b , an arrangement-structure changing process 140 c , and a statistical-information generating process 140 d .
  • the processes 140 a to 140 d correspond to the scheduler unit 20 and the access processing unit 21 depicted in FIG. 2 .
  • the CPU 140 executes the performance evaluation simulation programs based on the data recorded on the RAM 160 .
  • each program 150 a to 150 d are not necessarily required to be stored in advance in the ROM 150 .
  • each program may be stored in, for example, a “portable physical medium”, such as a flexible disk (FD), a CD-ROM (Compact-Disk Read-Only Memory), a DVD (Digital Versatile Disk), a magneto-optical disk, or an IC (Integrated Circuit) card inserted to the computer 110 ; a “fixed physical medium”, such as an HDD (Hard Disk Drive) internally or externally provided to the computer 110 ; or “another computer (or server)” connected to the computer 110 via a public circuit, the Internet, a LAN (Local-Area Network), or a WAN (Wide-Area Network), and may be read by the computer 110 therefrom for execution.
  • a “portable physical medium” such as a flexible disk (FD), a CD-ROM (Compact-Disk Read-Only Memory), a DVD (Digital Versatile Disk), a magneto
  • effects can be achieved such that SW/HW division can be optimally performed at the initial stage of designing and the validity of SW/HW division can be determined.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10303588B2 (en) 2015-05-26 2019-05-28 Samsung Electronics Co., Ltd. Systems and methods for test booting a device
US10303832B2 (en) * 2015-09-18 2019-05-28 Mitsubishi Electric Corporation Architecture generating device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8112425B2 (en) 2006-10-05 2012-02-07 Splunk Inc. Time series search engine
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Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05158740A (ja) 1991-12-09 1993-06-25 Matsushita Electric Ind Co Ltd 計算機性能評価装置
JPH11259553A (ja) 1998-03-13 1999-09-24 Omron Corp ハードウエアとソフトウエアの混在するシステムの設計支援方法
JPH11259552A (ja) 1998-03-13 1999-09-24 Omron Corp システム仕様記述のシミュレーション方法
JP2001142927A (ja) 1999-11-16 2001-05-25 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法，回路の消費電力解析方法及び消費電力解析装置
JP2001318812A (ja) 2000-05-11 2001-11-16 Nec Corp 性能評価モデル生成装置および性能評価モデル生成方法
WO2002027565A1 (en) 2000-09-28 2002-04-04 Cadence Design Systems, Inc. Performance level modeling and simulation of electronic systems having both hardware and software
US20020066082A1 (en) * 2000-06-02 2002-05-30 Nec Corporation Bus performance evaluation method for algorithm description
JP2002215423A (ja) 2001-01-22 2002-08-02 Hitachi Ltd ソフトウェアモデル作成方法
US20030121010A1 (en) 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US20050256692A1 (en) 2002-04-23 2005-11-17 France Telecom Method of generating a performance model from a functional model
US20050261884A1 (en) 2004-05-14 2005-11-24 International Business Machines Corporation Unified modeling language (UML) design method
JP2006059108A (ja) 2004-08-19 2006-03-02 Mitsubishi Electric Corp 情報システム開発試験支援システム
US20070271080A1 (en) 2006-05-16 2007-11-22 Fujitsu Limited Model generation method for software/hardware collaboration design
KR100812938B1 (ko) 2000-04-11 2008-03-11 양세양 초대규모급 설계 검증을 위한 하드웨어적으로 구현된대규모 디지털 시스템과 시뮬레이션을 이용하는 디버깅장치 및 이를 이용한 디버깅 방법
US20080306721A1 (en) 2004-03-09 2008-12-11 Sei Yang Yang Dynamic-Verification-Based Verification Apparatus Achieving High Verification Performance and Verification Efficiency and the Verification Methodology Using the Same
US20090150136A1 (en) 2005-10-10 2009-06-11 Sei Yang Yang Dynamic-based verification apparatus for verification from electronic system level to gate level, and verification method using the same
US20090204380A1 (en) 2008-01-08 2009-08-13 Fujitsu Limited Performance evaluation simulation
US20090313001A1 (en) * 2008-06-11 2009-12-17 Fujitsu Limited Simulation apparatus, simulation method and computer-readable recording medium on or in which simulation program is recorded
US20100204975A1 (en) 2007-10-15 2010-08-12 Fujitsu Limited Simulation method, electronic apparatus design method, and simulation apparatus
US20110184713A1 (en) 2005-10-10 2011-07-28 Sei Yang Yang Dynamic-based verification apparatus for verification from electronic system level to gate level, and verification method using the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100347683C (zh) * 2005-04-15 2007-11-07 清华大学 结构无关的微处理器验证及评测方法
JP2007018313A (ja) * 2005-07-08 2007-01-25 Fujitsu Ltd 回路設計プログラム、回路設計装置、回路設計方法

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05158740A (ja) 1991-12-09 1993-06-25 Matsushita Electric Ind Co Ltd 計算機性能評価装置
JPH11259553A (ja) 1998-03-13 1999-09-24 Omron Corp ハードウエアとソフトウエアの混在するシステムの設計支援方法
JPH11259552A (ja) 1998-03-13 1999-09-24 Omron Corp システム仕様記述のシミュレーション方法
US6513146B1 (en) * 1999-11-16 2003-01-28 Matsushita Electric Industrial Co., Ltd. Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption
JP2001142927A (ja) 1999-11-16 2001-05-25 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法，回路の消費電力解析方法及び消費電力解析装置
KR100812938B1 (ko) 2000-04-11 2008-03-11 양세양 초대규모급 설계 검증을 위한 하드웨어적으로 구현된대규모 디지털 시스템과 시뮬레이션을 이용하는 디버깅장치 및 이를 이용한 디버깅 방법
JP2001318812A (ja) 2000-05-11 2001-11-16 Nec Corp 性能評価モデル生成装置および性能評価モデル生成方法
US20020022942A1 (en) 2000-05-11 2002-02-21 Nec Corporation Apparatus and method for producing a performance evaluation model
US20020066082A1 (en) * 2000-06-02 2002-05-30 Nec Corporation Bus performance evaluation method for algorithm description
US7366647B2 (en) 2000-06-02 2008-04-29 Nec Electronics Corporation Bus performance evaluation method for algorithm description
WO2002027565A1 (en) 2000-09-28 2002-04-04 Cadence Design Systems, Inc. Performance level modeling and simulation of electronic systems having both hardware and software
US20020129329A1 (en) 2001-01-22 2002-09-12 Daisuke Nishioka Method for creating an application software model
JP2002215423A (ja) 2001-01-22 2002-08-02 Hitachi Ltd ソフトウェアモデル作成方法
US20030121010A1 (en) 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US20050256692A1 (en) 2002-04-23 2005-11-17 France Telecom Method of generating a performance model from a functional model
US20080306721A1 (en) 2004-03-09 2008-12-11 Sei Yang Yang Dynamic-Verification-Based Verification Apparatus Achieving High Verification Performance and Verification Efficiency and the Verification Methodology Using the Same
US20050261884A1 (en) 2004-05-14 2005-11-24 International Business Machines Corporation Unified modeling language (UML) design method
JP2006059108A (ja) 2004-08-19 2006-03-02 Mitsubishi Electric Corp 情報システム開発試験支援システム
US20090150136A1 (en) 2005-10-10 2009-06-11 Sei Yang Yang Dynamic-based verification apparatus for verification from electronic system level to gate level, and verification method using the same
US20110184713A1 (en) 2005-10-10 2011-07-28 Sei Yang Yang Dynamic-based verification apparatus for verification from electronic system level to gate level, and verification method using the same
JP2007310449A (ja) 2006-05-16 2007-11-29 Fujitsu Ltd ソフトウェア／ハードウェア協調設計のためのモデル生成プログラム、およびモデル生成方法
US20070271080A1 (en) 2006-05-16 2007-11-22 Fujitsu Limited Model generation method for software/hardware collaboration design
US20100204975A1 (en) 2007-10-15 2010-08-12 Fujitsu Limited Simulation method, electronic apparatus design method, and simulation apparatus
US20090204380A1 (en) 2008-01-08 2009-08-13 Fujitsu Limited Performance evaluation simulation
US20090313001A1 (en) * 2008-06-11 2009-12-17 Fujitsu Limited Simulation apparatus, simulation method and computer-readable recording medium on or in which simulation program is recorded

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
C. Hein et al., "Rassp Virtual Prototyping of DsP Systems", Proceedings of the Design Automation Conference, Anaheim, Jun. 9-13, 1997, pp. 492-497.
European Search Report dated Apr. 29, 2009 and issued in corresponding European Patent Application 08169674.2.
Korean Office Action issued Dec. 30, 2010 in a Korean Patent Application No. 10-2009-0024890 related to the copending U.S. Appl. No. 12/393,155 (4 pages, 4 pages English Translation).
T. Egolf et al., "VHDL-Based Rapid System Protyping", Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Springer, New York, vol. 2, No. 4, Nov. 1, 1996, pp. 125-154.
U.S. Appl. No. 12/393,155, filed Feb. 26, 2009, Tomoki Kato, Fujitsu Limited.
US Office Action issued in related U.S. Appl. No. 12/393,155.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10303588B2 (en) 2015-05-26 2019-05-28 Samsung Electronics Co., Ltd. Systems and methods for test booting a device
US10303832B2 (en) * 2015-09-18 2019-05-28 Mitsubishi Electric Corporation Architecture generating device

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