US8198731B2 - Protective layer for bond pads - Google Patents

Protective layer for bond pads Download PDF

Info

Publication number
US8198731B2
US8198731B2 US12/390,012 US39001209A US8198731B2 US 8198731 B2 US8198731 B2 US 8198731B2 US 39001209 A US39001209 A US 39001209A US 8198731 B2 US8198731 B2 US 8198731B2
Authority
US
United States
Prior art keywords
protective layer
bond pad
aluminum
array
aluminum bond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/390,012
Other languages
English (en)
Other versions
US20100117240A1 (en
Inventor
Mattia Cichocki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aptina Imaging Corp
Original Assignee
Aptina Imaging Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aptina Imaging Corp filed Critical Aptina Imaging Corp
Assigned to APTINA IMAGING CORPORATION reassignment APTINA IMAGING CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CICHOCKI, MATTIA
Publication of US20100117240A1 publication Critical patent/US20100117240A1/en
Priority to US13/471,151 priority Critical patent/US8372763B2/en
Application granted granted Critical
Publication of US8198731B2 publication Critical patent/US8198731B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01016—Sulfur [S]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • Disclosed embodiments relate generally to semiconductor circuits, and more particularly to a process for forming a protective layer on the surface of aluminum bond pads that protects the surface of the bond pads during subsequent processing.
  • bond pads are used to make electrical contact between various components of the circuit or device.
  • bond pads for imagers; however, the scope of the invention should not be limited as such and may be used for any type of integrated circuit device.
  • Imagers including charge coupled devices (CCDs), photodiode arrays, charge injection devices (CIDs), hybrid focal plane arrays, and complementary metal oxide semiconductor (CMOS) imagers, have commonly been used in photo-imaging applications.
  • Current applications of solid-state imagers include cameras, scanners, machine vision systems, vehicle navigation systems, star trackers, and motion detector systems, among others.
  • a CMOS imager typically includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge.
  • Each pixel cell has a charge storage region, which is connected to the gate of an output transistor that is part of a readout circuit.
  • the charge storage region may be constructed as a floating diffusion region.
  • each pixel cell may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
  • each pixel must be sensitive only to one color or spectral band.
  • a color filter array (CFA) is typically placed in front of the optical path to the photosensors so that each photosensor detects the light of the color of its associated filter.
  • the magnitude of the signal produced by each pixel is proportional to the amount of light impinging on the photosensor, it is also desirable to improve the photosensitivity of the imager by collecting light from a large light collecting area and focusing it onto a small photosensitive area of the photosensor. This can be done using a micro-lens array formed over the pixel array.
  • FIGS. 1A and 1B illustrate an imager 10 including a color filter array 30 and micro-lens array 35 over a pixel array 25 .
  • imaging portion 15 may be surrounded by peripheral circuitry 18 and bond pads 20 .
  • the bond pads 20 are electrically connected to device circuitry of the imager 10 .
  • Peripheral circuitry 18 controls the imaging portion 15 and converts electrical signals received from the imaging portion 15 into a digital image.
  • the pixel array 25 , peripheral circuitry 18 and bond pads 20 are formed in semiconductor wafer 50 .
  • Other conventional parts of the imager 10 are not shown or described herein.
  • the process for forming the color filter array 30 and/or micro-lens array 35 over the pixel array 25 requires a multi-step fabrication process.
  • a common method of forming these structures includes a tetramethylammonium hydroxide (TMAH)-based developing solution.
  • TMAH-based developing solutions used for color filter array formation have a TMAH concentration ranging from about 0.6% to about 2.6%.
  • the entire CFA/microlens formation process typically involves about six developing steps where this developing solution comes into contact with the bond pad for approximately 30 seconds to 1 minute per each step.
  • the TMAH contained in this developing solution is very aggressive on the aluminum from which the bond pads 20 are typically formed. As can be seen in FIG.
  • An organic protective layer or an oxide layer can be formed over the bond pads 20 before the CFA/micro-lens formation process to protect the bond pads 20 from the TMAH solution.
  • these layers must be removed after the CFA/micro-lens formation process in order to avoid problems (e.g., bonding issues during packaging of the imager) during later processing steps.
  • the oxide layer for example, must be removed using an expensive hard-coat process.
  • FIG. 1A is a schematic version of a top view of a conventional imager.
  • FIG. 1B is a schematic cross-sectional side view of the imager of FIG. 1A .
  • FIG. 2 illustrates the effect of a TMAH-based developing solution on an unprotected aluminum bond pad.
  • FIG. 3 illustrates a process for forming a protective Al—Si—O layer on bond pads, in accordance with disclosed embodiments.
  • FIG. 4 illustrates experimental results of the silicon depth profile of eight bond pads processed with the disclosed process.
  • FIG. 5 illustrates experimental results of the oxygen depth profile of eight bond pads processed with the disclosed process.
  • FIG. 6 illustrates experimental results of the aluminum depth profile of eight bond pads processed with the disclosed process.
  • FIG. 7 illustrates the effect of a TMAH-based developing solution on a protected aluminum bond pad, in accordance with disclosed embodiments.
  • FIG. 8 illustrates an element composition depth profile of an aluminum bond pad processed in accordance with the disclosed process and through a color filter array process.
  • Disclosed embodiments relate to a process performed on an imager before formation of the color filter array and/or micro-lens array, though, as noted, the process can be used with bond pads of other semiconductor devices and circuits.
  • the disclosed process is able to effectively protect the aluminum bond pads from unwanted damage typically caused by a TMAH-based developing process used in the CFA/micro-lens formation process.
  • a wet process is performed that creates a very thin layer of an aluminum-silicon-oxygen (Al x Si x O x ) compound on the surface of the bond pad.
  • Al x Si x O x aluminum-silicon-oxygen
  • FIG. 3 illustrates the wet process by which the Al—Si—O compound is formed on the surface of a bond pad 20 a.
  • the bond pad 20 a is exposed in a wet process to a solution 65 comprising deionized water, silicon (Si), ammonium persulfate (AP) and TMAH (TMA + and OH ⁇ ) and having a pH of 12+/ ⁇ 0.1.
  • silicon and oxygen are incorporated into the surface of the aluminum bond pad 20 a, thereby forming a thin layer of an Al x Si x O x compound 70 and resulting in a protected bond pad 20 b.
  • the solution 65 comprises between about 3.0% and about 3.4% silicon, between about 2.2% and about 2.8% ammonium persulfate and between about 6.5% and about 8.5% TMA + ions.
  • the bond pad 20 a is exposed to the solution 65 , followed by a DI water rinse and a Marangoni rinse, which dries the wafer.
  • the solution has an ionic interaction with the aluminum on the surface of the bond pad. Some aluminum atoms are brought into the solution and substituted with the silicon atoms, thereby forming a more resistant bond on the surface of the bond pad. This interaction stops when the surface has been uniformly implanted with the maximum amount silicon with respect to the temperature and pH at which it is being processed.
  • the process solution 65 comprises deionized water containing about 3.2% silicon, about 2.5% ammonium persulfate and about 7.5% TMA + and has a pH of 12+/ ⁇ 0.1.
  • the bond pad 20 a is exposed to the solution 65 for about 6 minutes, maintaining the temperature at about 90° C., followed by a DI water rinse at about 40° C. and a Marangoni rinse, which dries the wafer. It may also be possible to expose the bond pad to the process solution 65 at temperatures as low as about 60° C. The variation in temperature results in a variation in concentration of silicon in the protective layer.
  • the thin layer of Al—Si—O compound 70 may have a thickness of up to about 3.5 nm. Preferably the thickness is about 2 nm. This thickness is sufficient to protect the bond pad 20 b from attack by TMAH solution used in subsequent processing, such as during formation of a CFA and/or micro-lens array, but thin enough to allow uninhibited wire bonding at later processing steps (without needing to remove the protective layer).
  • the Al x Si x O x compound 70 formed at an upper portion of the bond pad 20 b contains between about 4% and about 18% silicon, between about 40% and about 60% oxygen and between about 5% and about 30% aluminum.
  • the balance of the compound is small amounts of other elements, such as carbon, nitrogen, fluorine and sulfur present in the bond pad 20 a before processing.
  • the Al x Si x O x compound 70 formed at an upper portion of the bond pad 20 b contains about 15% silicon, about 50% oxygen and about 20% aluminum.
  • FIG. 4 illustrates experimental results of the silicon depth profile of eight bond pads processed with the disclosed process.
  • FIG. 5 illustrates experimental results of the oxygen depth profile of eight bond pads processed with the disclosed process.
  • FIG. 6 illustrates experimental results of the aluminum depth profile of eight bond pads processed with the disclosed process.
  • FIGS. 4-6 illustrate the concentration of silicon, oxygen and aluminum, respectively, at increasing depths below the surface of the bond pad. These charts show the extent of incorporation of silicon and oxygen into the surface of the aluminum bond pads by using the claimed process. These depth profiles were created based on an X-ray Photoelectron Spectroscopy (XPS) analysis of the bondpad surfaces.
  • XPS X-ray Photoelectron Spectroscopy
  • the wafers can be subjected to subsequent processing, such as CFA/micro-lens formation using a standard, known process, without corrosion or pitting occurring on the bond pads. Additionally, the protective layer does not need to be removed prior to the subsequent processing. As can be seen in FIG. 7 , when the protected aluminum bond pad 20 b is exposed to a TMAH-based developing solution 55 , aluminum is not removed from the surface of the pad 20 b. Therefore, the problems associated with the pitting seen in FIG. 2 are avoided.
  • FIG. 8 illustrates a typical element composition depth profile of an aluminum bond pad processed with the wet solution in accordance with disclosed embodiments and then through a color filter array formation process. Again, these depth profiles were created based on an XPS analysis of the bondpad surfaces.
  • FIG. 8 demonstrates that the protective layer (circled region on FIG. 8 ) is able to resist the rework process performed in the CFA process to allow reprocessing of the wafers. This means that this layer can easily stand multiple CFA/micro-lens processes without the necessity to reapply it.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Formation Of Insulating Films (AREA)
  • Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
  • Orthopedics, Nursing, And Contraception (AREA)
US12/390,012 2008-11-13 2009-02-20 Protective layer for bond pads Active 2029-07-31 US8198731B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/471,151 US8372763B2 (en) 2008-11-13 2012-05-14 Process for wet passivation of bond pads for protection against subsequent TMAH-based processing

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IT000610A ITRM20080610A1 (it) 2008-11-13 2008-11-13 Procedimento per passivazione in umido di piazzole di unione per protezione contro un trattamento successivo basato su tmah.
ITRM2008A000610 2008-11-13
ITRM2008A0610 2008-11-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/471,151 Division US8372763B2 (en) 2008-11-13 2012-05-14 Process for wet passivation of bond pads for protection against subsequent TMAH-based processing

Publications (2)

Publication Number Publication Date
US20100117240A1 US20100117240A1 (en) 2010-05-13
US8198731B2 true US8198731B2 (en) 2012-06-12

Family

ID=40985102

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/390,012 Active 2029-07-31 US8198731B2 (en) 2008-11-13 2009-02-20 Protective layer for bond pads
US13/471,151 Active US8372763B2 (en) 2008-11-13 2012-05-14 Process for wet passivation of bond pads for protection against subsequent TMAH-based processing

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/471,151 Active US8372763B2 (en) 2008-11-13 2012-05-14 Process for wet passivation of bond pads for protection against subsequent TMAH-based processing

Country Status (2)

Country Link
US (2) US8198731B2 (it)
IT (1) ITRM20080610A1 (it)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120080767A1 (en) * 2010-10-04 2012-04-05 Sony Corporation Solid-state imaging device, method for manufacturing the same, and electronic apparatus
US20160190022A1 (en) * 2014-12-25 2016-06-30 Renesas Electronics Corporation Manufacturing method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999850B2 (en) * 2011-12-29 2015-04-07 Stmicroelectronics Pte Ltd Methods and apparatus for TMAH etching
JP2018046242A (ja) * 2016-09-16 2018-03-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190040B1 (en) * 1999-05-10 2001-02-20 Sensarray Corporation Apparatus for sensing temperature on a substrate in an integrated circuit fabrication tool
US6214717B1 (en) 1998-11-16 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for adding plasma treatment on bond pad to prevent bond pad staining problems
US20010023127A1 (en) 1998-09-15 2001-09-20 Andreas Michael T. Methods and solutions for cleaning polished aluminum-containing layers, methods for making metallization structures, and the structures resulting from these methods
US20030030942A1 (en) * 2001-08-10 2003-02-13 Hipwell Roger L. Integrated interconnect and method of manufacture therefor
KR20030026664A (ko) 2001-09-26 2003-04-03 주식회사 동진쎄미켐 티에프티 엘시디용 칼라 레지스트 박리액 조성물
US6582983B1 (en) * 2002-07-12 2003-06-24 Keteca Singapore Singapore Method and wafer for maintaining ultra clean bonding pads on a wafer
US20030197816A1 (en) * 2002-04-22 2003-10-23 Paul Winer Liquid crystal display devices having fill holes and electrical contacts on the back side of the die
US20050101043A1 (en) 2003-11-12 2005-05-12 Wei-Shiau Chen Manufacturing method of image sensor device
US6989608B2 (en) * 2004-04-01 2006-01-24 Atmel Corporation Method and apparatus to eliminate galvanic corrosion on copper doped aluminum bond pads on integrated circuits
US20060113674A1 (en) * 2001-03-01 2006-06-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
US20060141654A1 (en) * 2004-12-24 2006-06-29 Lim Bi O Method for fabricating a CMOS image sensor
US20070037314A1 (en) 2005-08-09 2007-02-15 Magnachip Semiconductor, Ltd. Method for fabricating image sensor without LTO-based passivation layer
US20070102842A1 (en) 2005-11-10 2007-05-10 Irizo Naniwa Process of microlens mold
US20080169267A1 (en) 2007-01-12 2008-07-17 C. Uyemura & Co., Ltd. Solution for removing aluminum oxide film and method for surface treatment of aluminum or aluminum alloy
US7871756B2 (en) * 2003-11-25 2011-01-18 Tokyo Ohka Kogyo Co., Ltd. Chemically amplified positive photosensitive thermosetting resin composition, method of forming cured article, and method of producing functional device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999055527A2 (de) * 1998-04-29 1999-11-04 Siemens Aktiengesellschaft Erzeugnis mit einer schutzschicht gegen korrosion sowie verfahren zur herstellung einer schutzschicht gegen korrosion

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010023127A1 (en) 1998-09-15 2001-09-20 Andreas Michael T. Methods and solutions for cleaning polished aluminum-containing layers, methods for making metallization structures, and the structures resulting from these methods
US6214717B1 (en) 1998-11-16 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for adding plasma treatment on bond pad to prevent bond pad staining problems
US6190040B1 (en) * 1999-05-10 2001-02-20 Sensarray Corporation Apparatus for sensing temperature on a substrate in an integrated circuit fabrication tool
US20060113674A1 (en) * 2001-03-01 2006-06-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
US20030030942A1 (en) * 2001-08-10 2003-02-13 Hipwell Roger L. Integrated interconnect and method of manufacture therefor
KR20030026664A (ko) 2001-09-26 2003-04-03 주식회사 동진쎄미켐 티에프티 엘시디용 칼라 레지스트 박리액 조성물
US20030197816A1 (en) * 2002-04-22 2003-10-23 Paul Winer Liquid crystal display devices having fill holes and electrical contacts on the back side of the die
US6582983B1 (en) * 2002-07-12 2003-06-24 Keteca Singapore Singapore Method and wafer for maintaining ultra clean bonding pads on a wafer
US20050101043A1 (en) 2003-11-12 2005-05-12 Wei-Shiau Chen Manufacturing method of image sensor device
US7871756B2 (en) * 2003-11-25 2011-01-18 Tokyo Ohka Kogyo Co., Ltd. Chemically amplified positive photosensitive thermosetting resin composition, method of forming cured article, and method of producing functional device
US6989608B2 (en) * 2004-04-01 2006-01-24 Atmel Corporation Method and apparatus to eliminate galvanic corrosion on copper doped aluminum bond pads on integrated circuits
US20060141654A1 (en) * 2004-12-24 2006-06-29 Lim Bi O Method for fabricating a CMOS image sensor
US20070037314A1 (en) 2005-08-09 2007-02-15 Magnachip Semiconductor, Ltd. Method for fabricating image sensor without LTO-based passivation layer
US7294524B2 (en) 2005-09-08 2007-11-13 Magnachip Semiconductor, Ltd. Method for fabricating image sensor without LTO-based passivation layer
US20070102842A1 (en) 2005-11-10 2007-05-10 Irizo Naniwa Process of microlens mold
US20080169267A1 (en) 2007-01-12 2008-07-17 C. Uyemura & Co., Ltd. Solution for removing aluminum oxide film and method for surface treatment of aluminum or aluminum alloy

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Charavel, et al."Advantages of p++ Polysilicon Etch Stop Layer Versus p++ Silicon" Proceedings of the SPIE-The International Society for Optical Engineering, vol. 5116, pp. 699-709 (2003).
Charavel, et al."Advantages of p++ Polysilicon Etch Stop Layer Versus p++ Silicon" Proceedings of the SPIE—The International Society for Optical Engineering, vol. 5116, pp. 699-709 (2003).
Fujitsuka, et al., "Silicon Anisotropic Etching Without Attacking Aluminum with Si and Oxidizing Agent Dissolved in TMAH Solution" Sensors and Actuators A, vol. 114, No. 2-3, pp. 510-515 (2004).
Italian Search Report for IT RM20080610, Sep. 3, 2009.
Written Opinion for IT RM2008A000610, (Nov. 13, 2008).

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120080767A1 (en) * 2010-10-04 2012-04-05 Sony Corporation Solid-state imaging device, method for manufacturing the same, and electronic apparatus
US8524594B2 (en) * 2010-10-04 2013-09-03 Sony Corporation Solid-state imaging device, method for manufacturing the same, and electronic apparatus
US8896039B2 (en) 2010-10-04 2014-11-25 Sony Corporation Solid-state imaging device, method for manufacturing the same, and electronic apparatus
US20160190022A1 (en) * 2014-12-25 2016-06-30 Renesas Electronics Corporation Manufacturing method of semiconductor device
US9799572B2 (en) * 2014-12-25 2017-10-24 Renesas Electronics Corporation Manufacturing method of semiconductor device
US20180033702A1 (en) * 2014-12-25 2018-02-01 Renesas Electronics Corporation Manufacturing method of semiconductor device
US10153216B2 (en) * 2014-12-25 2018-12-11 Renesas Electronics Corporation Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
ITRM20080610A1 (it) 2010-05-14
US8372763B2 (en) 2013-02-12
US20100117240A1 (en) 2010-05-13
US20120225567A1 (en) 2012-09-06

Similar Documents

Publication Publication Date Title
US11637141B2 (en) Solid-state image pickup apparatus and image pickup system
JP5347520B2 (ja) 固体撮像装置の製造方法
US6169319B1 (en) Backside illuminated image sensor
US20160064432A1 (en) Solid-state image sensor and method of manufacturing the same
JP4997879B2 (ja) 半導体装置及びその製造方法並びに固体撮像装置及びその製造方法並びに撮像装置
US20080150057A1 (en) Image sensor and method of manufacturing the same
JP2010192483A (ja) 固体撮像素子及び固体撮像素子の製造方法
JP2015029011A (ja) 固体撮像装置およびその製造方法、並びに電子機器
US10032820B2 (en) Imaging device and manufacturing method of the same
JP2009506542A (ja) 窒化ゲート酸化膜を有するｃｍｏｓイメジャーおよびその製造方法
US8372763B2 (en) Process for wet passivation of bond pads for protection against subsequent TMAH-based processing
KR100843968B1 (ko) 이미지센서의 제조방법
US20050007474A1 (en) Solid-state imaging device
US8293560B2 (en) Method of manufacturing photoelectric conversion device
JP2008147332A (ja) 固体撮像装置、その製造方法および撮像装置
JP6862129B2 (ja) 光電変換装置および撮像システム
US20090057798A1 (en) Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus
JP2008294479A (ja) 固体撮像装置
JP2013179224A (ja) 固体撮像素子の製造方法
KR100945866B1 (ko) 이미지 센서의 제조 방법
JP2010040636A (ja) 固体撮像装置の製造方法
US7772626B2 (en) Image sensor and fabricating method thereof
JP2005260076A (ja) 固体撮像装置及びその製造方法
TW202315149A (zh) 受光元件及電子機器
JP2014086552A (ja) 固体撮像素子及び固体撮像素子の製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: APTINA IMAGING CORPORATION,CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CICHOCKI, MATTIA;REEL/FRAME:022291/0355

Effective date: 20090213

Owner name: APTINA IMAGING CORPORATION, CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CICHOCKI, MATTIA;REEL/FRAME:022291/0355

Effective date: 20090213

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12