US7755955B2 - Apparatus and method for controlling data strobe signal - Google Patents

Apparatus and method for controlling data strobe signal Download PDF

Info

Publication number
US7755955B2
US7755955B2 US12/051,105 US5110508A US7755955B2 US 7755955 B2 US7755955 B2 US 7755955B2 US 5110508 A US5110508 A US 5110508A US 7755955 B2 US7755955 B2 US 7755955B2
Authority
US
United States
Prior art keywords
delay time
strobe signal
data strobe
read
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/051,105
Other languages
English (en)
Other versions
US20090067268A1 (en
Inventor
Yoon-Bum Seo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEO, YOON-BUM
Publication of US20090067268A1 publication Critical patent/US20090067268A1/en
Application granted granted Critical
Publication of US7755955B2 publication Critical patent/US7755955B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the present invention relates to an apparatus for and method of controlling a data strobe signal, and more particularly, to an apparatus for and method of controlling a data strobe signal to optimize a read margin in a memory controller as much as possible.
  • SDRAM synchronous dynamic random access memory
  • FIG. 1 is a view illustrating a general apparatus for controlling a data strobe signal to read external data.
  • the general apparatus for controlling a data strobe signal includes a delay locked loop (DLL) 110 , a controller 120 , a delay line 130 , and a flip-flop 140 .
  • DLL delay locked loop
  • the general apparatus for controlling a data strobe signal may be included in a memory controller.
  • External data (DQ) and a data strobe signal (DQS) are transmitted from the SDRAM to the memory controller generally with the same phase. Therefore, the memory controller latches the transmitted external data by using the data strobe signal. Since the data strobe signal has the same phase as that of the external data, the apparatus for controlling a data strobe signal delays the data strobe signal by a predetermined time and latches the external data by using the data strobe signal.
  • the data strobe signal has to be shifted by 90°.
  • An external system clock signal or data strobe signal is applied to the DLL 110 and the DLL 110 measures and outputs a period of the applied system clock signal or data strobe signal.
  • Outputs of the DLL 110 may be represented according to the number of delay chains included in the DLL 110 .
  • the controller 120 receives the period of the system clock signal or data strobe signal from the DLL 110 and determines a delay length of the data strobe signal for optimizing the setup margin and the hold margin of the data.
  • the data strobe signal may be shifted by 90° in the DDR SDRAM.
  • the DLL 110 counts the number of delay chains for a cycle of the data strobe signal, and the controller 120 multiplies the number of delay chains for the cycle by 1 ⁇ 4 to calculate the number of delay chains required to shift the data strobe signal by 90°.
  • the delay line 130 delays the data strobe signal according to the delay length determined by the controller 120 .
  • the flip-flop 140 latches and outputs external data by using the system clock signal or data strobe signal delayed and output from the delay line 130 as a trigger signal.
  • the general apparatus for controlling a data strobe signal cannot monitor the setup margin and the hold margin for the read operation of the data strobe signal.
  • a margin in the read operation is smaller than that in a write operation due to input/output (I/O) power noise and jitter of the clock signal, so a method of optimizing the read margin is required.
  • the present invention provides an apparatus for and method of controlling a data strobe signal capable of optimizing a setup margin and a hold margin of read data for the data strobe signal.
  • FIG. 1 is a view illustrating a general apparatus for controlling a data strobe signal to read external data
  • FIG. 2 is a view illustrating an apparatus for controlling a data strobe signal according to an exemplary embodiment of the present invention
  • FIG. 3 is a view illustrating an apparatus for controlling a data strobe signal according to another exemplary embodiment of the present invention
  • FIG. 4 is a timing diagram of signals in the apparatus for controlling a data strobe signal according to the embodiments illustrated in FIGS. 2 and 3 ;
  • FIG. 5 is a flowchart of a method of controlling a data strobe signal according to an exemplary embodiment of the present invention.
  • FIG. 6 is a flowchart of a method of controlling a data strobe signal according to another exemplary embodiment of the present invention.
  • FIG. 2 is a view illustrating an apparatus for controlling a data strobe signal according to an embodiment of the present invention.
  • the apparatus 200 for controlling a data strobe signal includes a period measurement unit 210 , a controller 220 , a delay circuit unit 230 , a flip-flop unit 240 , and a comparator 250 .
  • the period measurement unit 210 receives an external system clock signal or data strobe signal and measures and outputs a period of the received system clock signal or data strobe signal.
  • the controller 220 receives the period of the system clock signal or data strobe signal from the period measurement unit 210 and determines a read delay time, a setup margin delay time, and a hold margin delay time of the data strobe signal for optimizing a setup margin and a hold margin of read data on the basis of the received period.
  • the read delay time is a delay time used to allow the received data strobe signal (having the same phase as the read data) to be used for a read operation.
  • the read delay time (for example, A+B in FIG. 4 ) is a delay time of the data strobe signal for optimizing the setup margin (for example, A+B in FIG. 4 ) and the hold margin (for example, C+D in FIG. 4 ) of data.
  • the received data strobe signal is delayed by the read delay time, and external data is latched by the data strobe signal delayed by the read delay time by the flip-flop unit 240 so as to be output.
  • the read delay time may be determined to be a value obtained by dividing the sum of the setup margin delay time and the hold margin delay time by 2.
  • the setup margin delay time is a value (for example, A in FIG. 4 ) used to determine the setup margin (for example, A+B in FIG. 4 ) that is a time interval between a time point at which a read data transition occurs and a time point at which a read operation occurs.
  • the setup margin delay time may be set to an arbitrary value by a user when a system initially begins operation, and the external data is latched by the data strobe signal delayed by the setup margin delay time by the flip-flop unit 240 so as to be output.
  • the setup margin delay time is not set to a proper value and has to be changed to a different value. A detailed description thereof is provided with reference to FIG. 2 .
  • the hold margin delay time is a value (for example, A+B+C in FIG. 4 ) used to determine the hold margin (for example, C+D in FIG. 4 ) that is a time interval between a time point at which the read operation occurs and a time point at which another data transition occurs.
  • the hold margin delay time may be set to an arbitrary value by the user when the system initially begins operation.
  • the external data is latched by the data strobe signal delayed by the hold margin delay time by the flip-flop unit 240 so as to be output.
  • the delay circuit unit 230 receives the read delay time, the setup margin delay time, and the hold margin delay time from the controller 220 and receives an external data strobe signal.
  • the delay circuit unit 230 outputs three signals generated by delaying the external data strobe signal by the read delay time, the setup margin delay time, and the hold margin delay time.
  • the flip-flop unit 240 receives the data strobe signals delayed by the read delay time, the setup margin delay time, and the hold margin delay time from the delay circuit unit 230 and externally (for example, from the SDRAM) receives data DQ.
  • the external data DQ is latched by the data strobe signal delayed by the read delay time so as to be output.
  • the data DQ is latched by the data strobe signals delayed by the read delay time, the setup margin delay time, and the hold margin delay time so as to be transmitted to the comparator 250 .
  • the comparator 250 compares outputs from the flip-flop unit 240 with each other and feeds a result of the comparison back to the controller 220 .
  • the comparator 250 may compare the data strobe signals delayed by the read delay time and the setup margin delay time with each other, or the data strobe signals delayed by the read delay time and the hold margin delay time with each other. The comparison is performed so that the controller 220 can monitor an accurate setup margin or hold margin. Specifically, the controller 220 adjusts the setup margin delay time or the hold margin delay time according to the result of the comparison of the comparator 250 to determine a proper read delay time.
  • the setup margin or the hold margin for latching the external data may be changed. Therefore, the setup margin and the hold margin of the data can be optimized by the apparatus 200 for controlling the data strobe signal according to an embodiment of the present invention.
  • FIG. 3 is a view illustrating an apparatus for controlling a data strobe signal according to another embodiment of the present invention.
  • the apparatus 300 for controlling a data strobe signal includes a delay locked loop (DLL) 310 , a controller 320 , delay lines 325 , 330 , and 335 , flip-flops 340 , 345 , and 350 , and comparators 355 and 360 .
  • DLL delay locked loop
  • the DLL 310 receives an external system clock or data strobe signal and measures and outputs a period of the received system clock or data strobe signal. Outputs of the DLL 310 may be represented according to the number of delay chains included in the DLL 310 .
  • the controller 320 receives the period of the system clock signal or data strobe signal from the DLL 310 and determines a read delay time, a setup margin delay time, and a hold margin delay time of the data strobe signal on the basis of the received period.
  • the read delay time, the setup margin delay time, and the hold margin delay time are described above.
  • the controller 320 may analyze feedback from the comparators 355 and 360 for a period of time set by the user in advance and update the read delay time according to a result of the analysis.
  • the controller 320 may determine the read delay time, the setup margin delay time, and the hold margin delay time to be values set by the user in advance when the system initially operates.
  • the delay lines 325 , 330 , and 335 include the first delay line 325 for outputting signals generated by delaying the data strobe signal by the read delay time, the second delay line 330 for outputting signals generated by delaying the data strobe signal by the setup margin delay time, and the third delay line 335 for outputting signals generated by delaying the data strobe signal by the hold margin delay time.
  • Outputs of each of the delay lines 325 , 330 , and 335 are input to the flip-flops 340 , 345 , and 350 described later, and used as trigger signals.
  • the flip-flops 340 , 345 , and 350 include the first flip-flop 340 for latching and outputting external data by using the signal output from the first delay line 325 , the second flip-flop 345 for latching and outputting input data by using the signal output from the second delay line 330 , and the third flip-flop 350 for latching and outputting input data by using the signal output from the third delay line 335 .
  • the external data transmitted to the apparatus 300 for controlling a data strobe signal is latched by the first flip-flip 340 so as to be output as read data.
  • the comparators 355 and 360 include the first comparator 355 for comparing outputs from the first and second flip-flips 340 and 345 with each other and the second comparator 360 for comparing outputs from the first and third flip-flops 340 and 350 with each other.
  • the comparators 355 and 360 compare data latched by the flip-flops 340 , 345 , and 350 with each other so as to allow the controller 320 to check whether or not a margin exists.
  • the controller 320 receives feedback signals from the first and second comparators 355 and 360 .
  • the controller 320 determines that a setup margin exists as desired by the user, and when the output data are different from each other, the controller 320 determines that the setup margin does not exist. Therefore, for example, when the outputs from the first and second flip-flops 340 and 345 are different from each other, the controller 320 may increase the setup margin delay time by a predetermined time on the basis of the feedback from the first comparator 355 . In another embodiment, when the data output from the first and second flip-flops 340 and 345 are the same, the controller 320 decreases the setup margin delay time by a predetermined time so as to acquire a result as close as possible to a practical setup margin.
  • the controller 320 decreases the hold margin delay time by a predetermined time.
  • the controller 320 increases the hold margin delay time by a predetermined time so as to acquire a result as close as possible to a practical hold margin. Increments and decrements of the setup margin delay time and the hold margin delay time may be arbitrarily set by the user.
  • the controller 320 determines and updates the read delay time to be a value obtained by dividing the sum of the setup margin delay time and the hold margin delay time by 2 when reading data from the DDR SDRAM. Specifically, the controller 320 performs control operations so that the external data is read at the center of a corrected setup boundary and hold boundary.
  • the controller 320 may be affected by a momentary change in the external data or the data strobe signal, and therefore the controller 320 may be constructed to control the read delay time after monitoring changes for a predetermined time.
  • controller 320 may not continuously determine the read delay time from power-on to power-off but determine the read delay time during a data read refresh interval. This is because a latch failure may occur if the delay line is updated while I/O operates.
  • FIG. 4 is a timing diagram of signals in the apparatus for controlling a data strobe signal according to the embodiments illustrated in FIGS. 2 and 3 . This is described above with reference to FIGS. 2 and 3 , so that an additional description is omitted.
  • FIG. 5 is a flowchart of a method of controlling a data strobe signal according to an embodiment of the present invention.
  • a period of an input system clock signal or data strobe signal is measured.
  • the period may be measured by the DLL.
  • a read delay time, a setup margin delay time, and a hold margin delay time of the system clock signal or data strobe signal are determined on the basis of the period measured in operation 5 10 .
  • operation 530 signals generated by delaying the data strobe signal by the read delay time, the setup margin delay time, and the hold margin delay time are generated. Operation 530 may be performed by the delay lines.
  • operation 540 external data is latched by the signals generated in operation 530 so as to be output. Operation 540 may be performed by the flip-flops.
  • operation 550 the signals output in operation 540 are compared with each other, and in operation 560 , depending on a result of the comparison, operations 520 to 560 are repeated. Operations 550 and 560 may be performed by the comparator and the controller.
  • FIG. 6 is a flowchart of a method of controlling a data strobe signal according to another embodiment of the present invention.
  • operations 510 to 540 are performed before operation 610 in FIG. 6 .
  • the data latched and output by a flip-flop by using the data strobe signal delayed by the read delay time that is, the output from the first flip-flip F/F 1
  • the data latched and output by a flip-flop by using the data strobe signal delayed by the setup margin delay time that is, the output from the second flip-flop F/F 2
  • the setup margin delay time that is, the output from the second flip-flop F/F 2
  • operation 620 according to a result of the comparison, when the data are the same, operation 640 is performed, and when the data are different from each other, operation 630 is performed.
  • the setup margin delay time is increased.
  • operation 520 may be performed.
  • the data latched and output by a flip-flop by using the data strobe signal delayed by the read delay time that is, the output from the first flip-flop F/F 1
  • the data latched and output by a flip-flop by using the data strobe signal delayed by the hold margin delay time that is, the output from the third flip-flop F/F 3
  • operation 650 according to a result of the comparison, when the data are the same, operation 670 is performed, and when the data are different from each other, operation 660 is performed.
  • the hold margin delay time is decreased.
  • operation 520 may be performed.
  • the read delay time shifted by 90° is determined to be a value obtained by dividing the sum of the setup margin delay time and the hold margin delay time by 2.
  • determining the read delay time in operation 670 is not continuously performed from power-on to power-off, but performed only in the data read refresh interval. This is because latch failure may occur when the delay line is updated while I/O operates.
  • the setup margin delay time may be decreased.
  • the hold margin delay time may be increased. Accordingly, the setup margin and the hold margin may be increased as much as possible.
  • the setup margin and the hold margin of the read data for the data strobe signal are optimized, so that it is possible to stably read the data recorded in a memory.
  • the invention can also be embodied as computer readable codes on a computer readable recording medium or on a computer readable transmission medium.
  • the computer readable recording medium is any data storage device that can store data which can be thereafter be read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices.
  • ROM read-only memory
  • RAM random-access memory
  • CD-ROMs compact discs
  • magnetic tapes magnetic tapes
  • floppy disks and optical data storage devices.
  • An example of a computer readable transmission medium is carrier waves (such as data transmission through the Internet).
  • the computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
US12/051,105 2007-09-11 2008-03-19 Apparatus and method for controlling data strobe signal Active 2028-11-29 US7755955B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070092043A KR20090026939A (ko) 2007-09-11 2007-09-11 데이터 스트로브 신호 제어 장치 및 그 제어 방법
KR10-2007-0092043 2007-09-11

Publications (2)

Publication Number Publication Date
US20090067268A1 US20090067268A1 (en) 2009-03-12
US7755955B2 true US7755955B2 (en) 2010-07-13

Family

ID=40431672

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/051,105 Active 2028-11-29 US7755955B2 (en) 2007-09-11 2008-03-19 Apparatus and method for controlling data strobe signal

Country Status (2)

Country Link
US (1) US7755955B2 (ko)
KR (1) KR20090026939A (ko)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315892A1 (en) * 2004-12-28 2010-12-16 Panasonic Corporation Method and apparatus for timing adjustment
US8520455B2 (en) * 2012-01-10 2013-08-27 Apple Inc. Method and apparatus for training a DLL in a memory subsystem
US9405506B2 (en) 2012-12-13 2016-08-02 Samsung Electronics Co., Ltd. Method of operating system on chip and apparatuses including the same
US10095420B2 (en) 2015-02-13 2018-10-09 Samsung Electronics Co., Ltd. Storage device communicating with specific pattern and operating method thereof
US10388402B2 (en) * 2016-09-09 2019-08-20 Samsung Electronics Co., Ltd. Memory system and memory control method

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431091B2 (en) * 2008-06-06 2016-08-30 Uniquify, Inc. Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
JP2011003088A (ja) * 2009-06-19 2011-01-06 Panasonic Corp データラッチ調整装置およびそれを用いたメモリアクセスシステム
EP2330478A1 (de) * 2009-12-01 2011-06-08 VEGA Grieshaber KG Schaltung und Verfahren zum Bestimmen eines Wertes, insbesondere einer Dauer eines Messsignals
KR20150018163A (ko) 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 시스템 장치
KR102469171B1 (ko) * 2016-02-05 2022-11-22 에스케이하이닉스 주식회사 래치 회로, 리시버 회로, 이를 이용하는 반도체 장치 및 시스템
JP6518801B2 (ja) 2017-03-10 2019-05-22 エスアンドエス テック カンパニー リミテッド 極紫外線リソグラフィ用ペリクル及びその製造方法
US10103718B1 (en) * 2017-04-05 2018-10-16 Xilinx, Inc. Recalibration of source synchronous systems
US10026462B1 (en) * 2017-05-16 2018-07-17 Micron Technology, Inc. Apparatuses and methods for providing constant DQS-DQ delay in a memory device
US10347307B2 (en) * 2017-06-29 2019-07-09 SK Hynix Inc. Skew control circuit and interface circuit including the same
KR101981950B1 (ko) 2017-11-10 2019-05-24 주식회사 에스앤에스텍 극자외선 리소그래피용 펠리클
KR102495361B1 (ko) * 2018-03-14 2023-02-06 에스케이하이닉스 주식회사 입출력 회로
US10199937B1 (en) * 2018-04-09 2019-02-05 Texas Instruments Incorporated Methods and apparatus to digitally control pulse frequency modulation pulses in power converters
KR20190053766A (ko) 2018-08-24 2019-05-20 주식회사 에스앤에스텍 극자외선 리소그래피용 펠리클 및 그의 제조방법
KR102635773B1 (ko) * 2018-09-13 2024-02-08 삼성전자주식회사 저장 장치
KR20200076258A (ko) 2018-12-19 2020-06-29 주식회사 에스앤에스텍 판면에 주름부를 구비한 펠리클 및 그의 제조방법
KR102266786B1 (ko) 2018-12-19 2021-06-21 주식회사 에스앤에스텍 판면에 주름부를 구비한 펠리클
KR20190107604A (ko) 2019-04-22 2019-09-20 주식회사 에스앤에스텍 극자외선 리소그래피용 펠리클 및 그의 제조방법
KR20190107603A (ko) 2019-04-22 2019-09-20 주식회사 에스앤에스텍 극자외선 리소그래피용 펠리클 및 그의 제조방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512719B2 (en) * 2000-07-05 2003-01-28 Hitachi, Ltd. Semiconductor memory device capable of outputting and inputting data at high speed
US20030021164A1 (en) * 2001-03-09 2003-01-30 Samsung Electronics Co., Ltd. Semiconductor memory device having different data rates in read operation and write operation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512719B2 (en) * 2000-07-05 2003-01-28 Hitachi, Ltd. Semiconductor memory device capable of outputting and inputting data at high speed
US20030021164A1 (en) * 2001-03-09 2003-01-30 Samsung Electronics Co., Ltd. Semiconductor memory device having different data rates in read operation and write operation

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100315892A1 (en) * 2004-12-28 2010-12-16 Panasonic Corporation Method and apparatus for timing adjustment
US8094506B2 (en) * 2004-12-28 2012-01-10 Panasonic Corporation Method and apparatus for timing adjustment
US8634259B2 (en) 2004-12-28 2014-01-21 Panasonic Corporation Method and apparatus for timing adjustment
US9159382B2 (en) 2004-12-28 2015-10-13 Socionext Inc. Method and apparatus for timing adjustment
US9472254B2 (en) 2004-12-28 2016-10-18 Socionext Inc. Method and apparatus for timing adjustment
US9570131B2 (en) 2004-12-28 2017-02-14 Socionext Inc. Method and apparatus for timing adjustment
US9685212B2 (en) 2004-12-28 2017-06-20 Socionext Inc. Method and apparatus for timing adjustment
US9805778B2 (en) 2004-12-28 2017-10-31 Socionext Inc. Method and apparatus for timing adjustment
US8520455B2 (en) * 2012-01-10 2013-08-27 Apple Inc. Method and apparatus for training a DLL in a memory subsystem
US9405506B2 (en) 2012-12-13 2016-08-02 Samsung Electronics Co., Ltd. Method of operating system on chip and apparatuses including the same
US10095420B2 (en) 2015-02-13 2018-10-09 Samsung Electronics Co., Ltd. Storage device communicating with specific pattern and operating method thereof
US10388402B2 (en) * 2016-09-09 2019-08-20 Samsung Electronics Co., Ltd. Memory system and memory control method

Also Published As

Publication number Publication date
KR20090026939A (ko) 2009-03-16
US20090067268A1 (en) 2009-03-12

Similar Documents

Publication Publication Date Title
US7755955B2 (en) Apparatus and method for controlling data strobe signal
US10290336B2 (en) Methods and apparatuses including command delay adjustment circuit
US9000817B2 (en) Apparatuses and methods for altering a forward path delay of a signal path
JP4450586B2 (ja) 半導体集積回路
KR101144519B1 (ko) 앞선 위상 등화를 이용한 ｄｌｌ 위상 검출
US7733140B2 (en) Delay locked loop in semiconductor memory device
US7825711B2 (en) Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals
US7672191B2 (en) Data output control circuit
US9601170B1 (en) Apparatuses and methods for adjusting a delay of a command signal path
US8674734B2 (en) Synchronous semiconductor device having delay locked loop for latency control
US7605622B2 (en) Delay locked loop circuit
US7692980B2 (en) Method of and apparatus for reading data
US6760263B2 (en) Method and device for controlling data latch time
US8766686B2 (en) Semiconductor device and method for driving the same
US20080175343A1 (en) Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus, program and computer readable information recording medium
US8035431B2 (en) Delay locked loop and delay locking method having burst tracking scheme
US20050243607A1 (en) Data output controller in semiconductor memory device and control method thereof
US20090319744A1 (en) Digital Television, Memory Controller, and Method for Controlling Access of a Memory Device
JP4514272B2 (ja) デジタルデータ処理回路
US7902889B2 (en) Delay locked loop
JP2007148914A (ja) ラッチタイミング調整装置及びその調整方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEO, YOON-BUM;REEL/FRAME:020672/0025

Effective date: 20080303

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12