US7710376B2 - Display and method of driving same - Google Patents
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- US7710376B2 US7710376B2 US11/352,234 US35223406A US7710376B2 US 7710376 B2 US7710376 B2 US 7710376B2 US 35223406 A US35223406 A US 35223406A US 7710376 B2 US7710376 B2 US 7710376B2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
Definitions
- the present invention relates to a display and a method of driving the display and more particularly to a TFT (Thin Film Transistor) active matrix display.
- TFT Thin Film Transistor
- a display with as high a resolution as printed matters is desired.
- the resolution of the currently available displays is 200 ppi (pixels per inch) at the highest, far less than that of printed matters.
- the conventional displays have another problem that even at a resolution of around 200 ppi a large number of pixels used consumes a large amount of electricity.
- a most effective method for reducing power consumption is to reduce a frame frequency.
- a reduction in frame frequency may be achieved by having a memory in pixels.
- liquid crystal displays having a memory in pixels an example of a conventional pixel circuit configuration related to this invention is disclosed in JP-A-2-272521.
- JP-A-2003-302936 describes that, in an amorphous TFT, a transistor for driving an OLED (Organic Light Emitting Diode), an increased component of a threshold voltage (Vth) is removed by turning on or off a gate voltage and a drain voltage simultaneously.
- OLED Organic Light Emitting Diode
- JP-A-2002-341828 describes that a display pixel circuit using organic EL (electroluminescence) devices adjusts a brightness of displayed image practically without reducing the number of grayscale levels of the image.
- JP-A-10-319909 describes that a plurality of organic EL elements emit light for respective picture sub-frames with its own brightness, that images for each of sub-frames are visually combined and that brightness within a frame can be represented.
- JP-A-7-111341 describes that an organic thin film EL display reduces a failure rate caused by wire breaks and short circuits, by reducing a total wiring length and the number of crossings.
- the number of pixels per unit area needs to be increased compared with the conventional displays.
- the use of the conventional display driving method to perform an image display at the superfine resolution requires increasing a reference clock frequency significantly, which results in a substantial increase in power consumption, making this method impractical.
- One conceivable method for realizing a high resolution at low power consumption involves incorporating a memory in pixels and reducing the frame frequency. If a complex memory circuit such as static RAM or a CMOS transistor memory circuit is used, it is difficult to realize a high resolution.
- this invention adopts a memory-incorporated pixel system of single channel transistor configuration which is the simplest configuration.
- the memory-incorporated pixel system using the single channel transistor configuration has two single channel transistors for each pixel.
- CMOS transistor configuration In the case of the CMOS transistor configuration, one of two reference voltage lines can be chosen, whereas the conventional single channel transistor configuration has only one reference voltage line and thus no method is available so far to switch from one state to another without adversely affecting the image display performance.
- the present invention provides a display comprising: a plurality of pixels arranged in matrix; wherein each of the pixels has at least a first transistor, a second transistor, an image signal memory, an added capacitor, an electrooptical medium, and a common electrode; wherein each of the pixels is connected to at least a signal line, a scan line and a reference voltage line; wherein one of drain and source of the first transistor is connected to the signal line; wherein the other of drain and source of the first transistor is connected to a gate of the second transistor; wherein a gate of the first transistor is connected to the scan line; wherein one of drain and source of the second transistor is connected to the electrooptical medium; wherein the other of drain and source of the second transistor is connected to the reference voltage line; wherein the image signal memory is connected to a gate of the second transistor and the reference voltage line; wherein the added capacitor is connected to the gate of the second transistor and to one of drain and source of the second transistor; wherein the electrooptical medium is connected to one of drain and source of the second transistor; where
- a method for driving the display defined in the first aspect includes the steps of: refreshing the image signal memory during a scanning period by a voltage applied through the signal line; and holding, by a voltage applied through the signal line and a voltage applied through the reference voltage line, an image signal written into the image signal memory during an image hold period; wherein in the image hold period a drive waveform of the reference voltage line is a rectangular waveform of a particular frequency; wherein a period of selecting one scan line during the scanning period has a reset period to initialize a voltage difference between ends of the electrooptical medium and an image signal write period to write an image signal into the image signal memory; wherein in the image signal write period, a voltage of the signal line is set to a high level or a low level according to the image signal.
- This invention therefore can provide a low power consumption display which uses a memory-incorporated pixel technology and which can perform refreshing of the image signal memory and update an image without causing a flicker.
- This invention also provides a method of driving such a display.
- FIG. 1 is a block diagram of a display according to this invention.
- FIG. 2 is a layout diagram showing a pixel unit in a layer below a reflective electrode 146 .
- FIG. 3 is a layout diagram showing the pixel unit including the reflective electrode 146 .
- FIG. 4 is a circuit configuration diagram of a pixel 102 .
- FIG. 5 is a fundamental circuit configuration diagram of the pixel 102 .
- FIGS. 6A and 6B are fundamental drive sequence diagrams (when writing black data).
- FIGS. 7A and 7B are fundamental drive sequence diagrams (when writing white data).
- FIGS. 8A and 8B are drive sequence diagrams of this invention (when writing black data).
- FIGS. 9A and 9B are drive sequence diagrams of this invention (when writing white data).
- FIG. 10 is an applied voltage vs. reflectivity (brightness) characteristic of a liquid crystal display.
- FIG. 11 is a drive sequence diagram of this invention (when writing white data).
- FIG. 12 is another drive sequence diagram of this invention (when writing white data).
- FIG. 1 is a block diagram of a display according to this invention which comprises: a panel unit 101 , or a so-called active matrix printed circuit board having a display unit 107 formed with a matrix of a plurality of pixels 102 ; a scan line driver 103 for driving scan lines 109 ; a timing controller 105 ; and a signal line driver 111 for driving signal lines 110 .
- the pixels 102 have an electrooptical medium 123 which controls each pixel 102 electrically independently to control a brightness of each pixel and thereby display a desired image.
- the timing controller 105 receives a timing signal and an image signal from external devices not shown.
- the timing controller 105 controls the signal line driver 111 , the scan line driver 103 , and a reference voltage circuit 104 .
- the reference voltage circuit 104 drives a reference voltage line 108 .
- control circuits such as signal line driver 111 and timing controller 105 are provided separate from the panel unit 101 , they may be formed directly on the panel unit 101 .
- FIG. 2 and FIG. 3 are layout diagrams of the pixels 102 of FIG. 1 , each of which has, at an intersection of the signal line 110 and the scan line 109 , a first transistor 121 and a second transistor 122 with its gate connected via a through-hole contact 142 to a source of the first transistor 121 on the opposite side of the signal line 110 .
- the first transistor 121 and the second transistor 122 in this embodiment are amorphous silicon TFTs (thin film transistors) using an amorphous silicon layer 145 as a semiconductor layer.
- the source electrode of the first transistor 121 and an electrode 144 which is connected to the reference voltage line 108 and the source or drain of the second transistor 122 via a through-hole contact 143 , together form a capacitor that functions as an image signal memory 124 .
- the gate electrode of the second transistor 122 forms a capacitor as an added capacitor at an overlapping portion 154 between it and the source or drain of the second transistor.
- One of the source and drain of the second transistor 122 is connected via a through-hole contact 141 to a reflective electrode 146 ( FIG. 3 ) disposed on the pixel 102 .
- the first transistor 121 has its gate connected to a scan line 109 ( i ) at an i-th row, one of its drain and source connected to the signal line 110 , and the other of the drain and source connected to one end of the image signal memory 124 and to the gate of the second transistor 122 .
- the other end of the image signal memory 124 is connected to the reference voltage line 108 .
- One of the drain and source of the second transistor 122 is connected to the electrooptical medium 123 and the other to the reference voltage line 108 .
- a holding capacitor 117 is connected between one of the drain and source of the second transistor 122 and a scan line 109 ( i - 1 ), which is one row before.
- One end of the electrooptical medium 123 opposite the second transistor 122 is connected to a common electrode 120 .
- the common electrode 120 is provided on the same printed circuit board as the TFT or on an opposing printed circuit board, or both, depending on the kind of the electrooptical medium 123 . Further, there is a TFT parasitic capacitor 119 between the gate of the first transistor 121 and the other of its drain and source. Further, there is a pixel electrode parasitic capacitor 118 between one of the drain or source of the second transistor 122 and the reference voltage line 108 .
- the transistors in this embodiment are thin film transistors (TFTs).
- TFTs may use amorphous silicon TFTs or polysilicon TFTs.
- Organic TFTs using organic semiconductors may also be used.
- liquid crystal display system uses a liquid crystal as the electrooptical medium 123
- liquid crystal display system examples include a reflective twisted nematic system, a guest-host liquid crystal system, and a reflective homeotropic ECB (Electrically Controlled Birefringence) system.
- ECB Electrode Controlled Birefringence
- a reflective in-plane switching system can also be used.
- the common electrode 120 is provided on the same printed circuit board as the TFT.
- the method of driving the display of this invention will be explained as follows. First, for easy understanding, let us explain about the driving method with the parasitic capacitors 118 , 119 , the added capacitor 129 and the holding capacitor 117 removed, by referring to FIG. 5 . Then, the actual driving method will be described referring to FIG. 4 .
- FIG. 5 is a fundamental circuitry of a pixel circuit.
- the first transistor 121 has its gate connected to an i-th row scan line 109 ( i ), one of its drain and source connected to the signal line 110 , and the other of drain and source connected to one end of the image signal memory 124 and to a gate of the second transistor 122 .
- the other end of the image signal memory 124 is connected to the reference voltage line 108 .
- the second transistor 122 has one of its drain and source connected to the electrooptical medium 123 and the other of drain and source connected to the reference voltage line 108 .
- One end of the electrooptical medium 123 opposite the second transistor 122 is connected to a common electrode 120 .
- the common electrode 120 is provided on the same printed circuit board as the TFT or on an opposing printed circuit board, or both, depending on the kind of the electrooptical medium 123 .
- a drive waveform for driving the pixel of the configuration shown in FIG. 5 will be explained for a case of writing black data and for a case of writing white data, separately.
- FIGS. 6A and 6B show drive waveforms when writing black data.
- FIG. 6A represents a gate waveform (voltage) 138 of the second transistor and
- FIG. 6B represents a pixel electrode voltage 139 .
- denoted 131 is a gate pulse, a pulse waveform ranging between voltage V GL and voltage V GH .
- Denoted 132 is a drive waveform of the signal line, a pulse waveform ranging between voltage V DL and voltage V DH .
- Designated 136 is a drive waveform of the reference voltage line which can take one of three levels V RR , V RL , V RH .
- Denoted 137 is a common voltage which in this embodiment is a DC waveform of voltage V com .
- Reference number 138 in FIG. 6A represents a gate waveform of the second transistor, and 139 in FIG. 6B represents an pixel electrode voltage. These reference numbers remain the same in the following waveform diagrams.
- Reference number 126 represents a scanning period and 127 an image hold period.
- the scanning period 126 is a period in which to refresh the image signal memory 124 and to update a state of the voltage applied to the electrooptical medium 123 , i.e., update the displayed image.
- the image hold period 127 is a period in which to halt the scanning of a screen and hold a display state of each pixel determined according to the state of the associated image signal memory 124 .
- Reference number 133 represents a selection period for one scan line, 134 a reset period in the selection period, and an image signal write period.
- the signal line voltage is V DH in both a reset period 134 and an image signal write period 135 and therefore is always V DH during a selection period 133 of one scan line.
- a gate voltage 138 of the second transistor 122 is higher than the voltage V RR of the reference voltage line 108 by (V DH ⁇ V RR ), turning on the second transistor.
- the first transistor turns off and the gate voltage 138 of the second transistor is held in the image signal memory 124 .
- the pixel electrode voltage 139 (Vpix) is almost equal to voltage V RR of the reference voltage line, as shown in FIG. 6B .
- the image hold period 127 is explained.
- the gate of the second transistor 122 is floating and is connected to the reference voltage line 108 through the image signal memory 124 .
- the gate voltage 138 of the second transistor also changes similarly, holding the second transistor turned on.
- the pixel electrode voltage 139 reaches the same voltage level as the reference voltage line 108 through the on-state second transistor.
- the voltage 136 of the reference voltage line has a waveform with V RH and V RL alternating in a predetermined cycle and is set so as to make the absolute values of V com ⁇ V RH and V com ⁇ V RL equal.
- FIGS. 7A and 7B show drive waveforms during the white data writing, FIG. 7A representing a gate waveform (voltage) 138 of the second transistor and FIG. 7B representing the pixel electrode voltage 139 .
- a signal line voltage 132 is V DH in the reset period 134 and, in the image signal write period 135 , is V DL .
- the other of drain and source of the second transistor 122 has a voltage V RR and the gate voltage 138 of the second transistor 122 is V DL .
- the second transistor 122 since V RR >V DL , the second transistor 122 is off. In a reset period 134 at the first half of the scan line selection period 133 the second transistor 122 turns on. Since the reference voltage line 108 and the pixel electrode are connected through the ON-state second transistor 122 , the pixel electrode voltage 139 becomes V RR .
- the first transistor 121 turns off and the gate voltage 138 of the second transistor 122 is held in the image signal memory 124 .
- the only difference from the black data writing is that at the end of the scan line selection period 133 , the second transistor 122 is off.
- the gate voltage 138 of the second transistor 122 in the image hold period 127 varies with the reference voltage line 108 by the capacitance coupling of the image signal memory 124 , holding the second transistor 122 turned off, as in the black data.
- the reference voltage line 108 is connected commonly to all pixels and, as explained in connection with FIGS. 6A and 6B and FIGS. 7A and 7B , the reference voltage line voltage V RR is V com in the scanning period 126 , the pixel electrode voltage 139 is V com across the entire screen during the scanning period 126 whether the data being written is white or black. Therefore, during the scanning period 126 , the entire screen turns white, resulting in a flicker.
- FIG. 8A shows a waveform of the gate voltage 138 of the second transistor 122 when writing black data
- FIG. 8B shows a waveform of the pixel electrode voltage 139 when writing black data
- FIG. 9A shows a waveform of the gate voltage 138 when writing white data
- FIG. 9B shows a waveform of the pixel electrode voltage 139 when writing white data.
- C gs1 represents a capacitance of the TFT parasitic capacitor 119
- C s a capacitance of the holding capacitor 117
- C pix a capacitance (called a pixel capacitor) produced by the electrooptical medium 123 interposed between the pixel electrode and the common electrode
- C opc a capacitance of the pixel electrode parasitic capacitor 118
- C m a capacitance of the image signal memory 124
- C b a capacitance of the added capacitor 129 .
- ⁇ V pxg occurs both during the white data writing and the black data writing when the voltage variation of the gate pulse 131 from V GH to V GL changes the pixel electrode voltage 139 by the capacitance coupling of the TFT parasitic capacitor 119 and the added capacitor 129 .
- This variation factor may be expressed by equation (1):
- ⁇ V pxw occurs during the white data writing when the voltage variation of the signal line 110 from V DH to V DL while the first transistor 121 is on changes the pixel electrode voltage 139 by the capacitance coupling of the added capacitor 129 .
- This variation factor may be expressed by equation (3):
- ⁇ V pxr occurs during the image hold period 127 of white data when the voltage variation of the reference voltage line 108 from V RH to V RL in the image hold period 127 changes the pixel electrode voltage 139 by the capacitance coupling of the pixel electrode parasitic capacitor C opc , the image signal memory capacitor C m and the added capacitor C b .
- This variation factor may be expressed by equation (4):
- the voltage of the reference voltage line falls from V RH by ⁇ V pxw + ⁇ V pxg during the scanning period 126 and further falls ⁇ V pxr during the switching from the scanning period 126 to the image hold period 127 .
- the pixel electrode voltage 139 varies greatly.
- the pixels are driven such that the voltage V RR of the reference voltage line 108 during scanning period is made equal to V RH and that the pixel electrode voltage 139 for only those pixels that are written with white data is made almost equal to V com by using the voltage variations mentioned above.
- the pixel electrode voltage for the pixels that are written with black data can be set to V RH and the pixel electrode voltage for the pixels that are written with white data can be set to nearly V com . Since these pixel electrode voltages are equal to the pixel electrode voltages during the holding period, no flicker occurs at all during the scanning period. That is, if the following equation (5) is satisfied, the flicker during the scanning period can be prevented.
- V RH - ( ⁇ ⁇ ⁇ V pxw + ⁇ ⁇ ⁇ V pxg + ⁇ ⁇ ⁇ V pxr 2 ) V com ( 5 )
- FIG. 10 shows an example of applied voltage vs. reflectivity (brightness) characteristic of liquid crystal.
- the brightness does not change even when applied with a voltage up to around 0.7 V.
- the maximum applied voltage that does not influence the brightness be a liquid crystal dead voltage V W .
- V w V pxr /2
- V com ⁇ V W ⁇ V RH ⁇ ( ⁇ V pxw + ⁇ V pxg + ⁇ V pxr ) (6)
- the gate voltage of the second transistor 122 falls from V DL by ⁇ V tlg +(V RH ⁇ V RL ), as shown in FIG. 9A , due to the capacitor coupling of the image signal memory 124 when the scanning period 126 is switched to the image hold period 127 .
- V GL must be a voltage that can turn off the first transistor 121 well. To hold this transistor turned off, V GL needs to be approximately 5 V less than the drain or source voltage. Thus, the following equation (8) holds. V DL ⁇ V GL + ⁇ V tlg +( V RH ⁇ V RL )+5 (8)
- the pixel capacitor C pix may change depending on the display state immediately before. This is caused by a dielectric constant anisotropy of the liquid crystal material.
- white is displayed by using ⁇ V pxw to push down the pixel electrode voltage 139 .
- ⁇ V pxw the displayed image cannot be changed completely from black to white with a single refreshing, leaving a faint image like an afterimage for a period of a few refreshing operations.
- the frame frequency is 1-2 Hz or less, the afterimage will remain for a few seconds.
- FIG. 11 is a drive waveform diagram for the above case, showing the pixel electrode voltage 139 as the immediately preceding displayed image changes from black to white.
- C pix is large. So, the value of ⁇ V pxw is small and, compared with the case of FIG. 9B , the pixel electrode voltage 139 during the image hold period 127 is shifted in the positive direction.
- FIG. 12 is a waveform diagram showing the pixel electrode voltage 139 when the scanning period 126 is provided twice as the immediately preceding displayed image changes from black to white.
- equation (5) or equation (7) cannot be satisfied for the reason described above and thus a faint gray image remains. But in the second scanning period 126 B the data is written again.
- the pixel electrode variation ⁇ V pxwB caused by data line voltage variation in the second scanning period 126 B is larger than ⁇ V pxwA in the first scanning period 126 A.
- equation (5) or equation (7) it is made easier to satisfy equation (5) or equation (7). If equation (5) or equation (7) can not still be satisfied after the two scans, another scanning period may be added to meet equation (5) or equation (7).
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Abstract
Description
V com −V W ≦V RH−(ΔV pxw +ΔV pxg +ΔV pxr) (6)
V com +V W ≧V RH−(ΔV pxw +ΔV pxg) (7)
V DL ≧V GL +ΔV tlg+(V RH −V RL)+5 (8)
Claims (15)
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JP2005036652A JP4580775B2 (en) | 2005-02-14 | 2005-02-14 | Display device and driving method thereof |
JP2005-036652 | 2005-02-14 |
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US (1) | US7710376B2 (en) |
JP (1) | JP4580775B2 (en) |
KR (1) | KR100783238B1 (en) |
CN (1) | CN100414579C (en) |
TW (1) | TW200629211A (en) |
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US20110216104A1 (en) * | 2010-03-08 | 2011-09-08 | Bryan Hans Chan | Driving methods for electrophoretic displays |
US20130342435A1 (en) * | 2011-12-29 | 2013-12-26 | Benjie N. Limketkai | Thin-film transitor backplane for displays |
US9013394B2 (en) | 2010-06-04 | 2015-04-21 | E Ink California, Llc | Driving method for electrophoretic displays |
US9019318B2 (en) | 2008-10-24 | 2015-04-28 | E Ink California, Llc | Driving methods for electrophoretic displays employing grey level waveforms |
US9171508B2 (en) | 2007-05-03 | 2015-10-27 | E Ink California, Llc | Driving bistable displays |
US9251736B2 (en) | 2009-01-30 | 2016-02-02 | E Ink California, Llc | Multiple voltage level driving for electrophoretic displays |
US9299294B2 (en) | 2010-11-11 | 2016-03-29 | E Ink California, Llc | Driving method for electrophoretic displays with different color states |
US9373289B2 (en) | 2007-06-07 | 2016-06-21 | E Ink California, Llc | Driving methods and circuit for bi-stable displays |
US10339876B2 (en) | 2013-10-07 | 2019-07-02 | E Ink California, Llc | Driving methods for color display device |
US10380931B2 (en) | 2013-10-07 | 2019-08-13 | E Ink California, Llc | Driving methods for color display device |
US10726760B2 (en) | 2013-10-07 | 2020-07-28 | E Ink California, Llc | Driving methods to produce a mixed color state for an electrophoretic display |
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US8643595B2 (en) | 2004-10-25 | 2014-02-04 | Sipix Imaging, Inc. | Electrophoretic display driving approaches |
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US10002575B2 (en) | 2007-06-07 | 2018-06-19 | E Ink California, Llc | Driving methods and circuit for bi-stable displays |
US10535312B2 (en) | 2007-06-07 | 2020-01-14 | E Ink California, Llc | Driving methods and circuit for bi-stable displays |
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US9251736B2 (en) | 2009-01-30 | 2016-02-02 | E Ink California, Llc | Multiple voltage level driving for electrophoretic displays |
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US10339876B2 (en) | 2013-10-07 | 2019-07-02 | E Ink California, Llc | Driving methods for color display device |
US10726760B2 (en) | 2013-10-07 | 2020-07-28 | E Ink California, Llc | Driving methods to produce a mixed color state for an electrophoretic display |
US11004409B2 (en) | 2013-10-07 | 2021-05-11 | E Ink California, Llc | Driving methods for color display device |
US11217145B2 (en) | 2013-10-07 | 2022-01-04 | E Ink California, Llc | Driving methods to produce a mixed color state for an electrophoretic display |
Also Published As
Publication number | Publication date |
---|---|
JP2006221095A (en) | 2006-08-24 |
US20060181497A1 (en) | 2006-08-17 |
JP4580775B2 (en) | 2010-11-17 |
TWI315860B (en) | 2009-10-11 |
KR100783238B1 (en) | 2007-12-06 |
TW200629211A (en) | 2006-08-16 |
CN100414579C (en) | 2008-08-27 |
CN1822076A (en) | 2006-08-23 |
KR20060091249A (en) | 2006-08-18 |
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