US7626260B2 - Stack-type semiconductor device having cooling path on its bottom surface - Google Patents

Stack-type semiconductor device having cooling path on its bottom surface Download PDF

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US7626260B2
US7626260B2 US11/751,464 US75146407A US7626260B2 US 7626260 B2 US7626260 B2 US 7626260B2 US 75146407 A US75146407 A US 75146407A US 7626260 B2 US7626260 B2 US 7626260B2
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stack
cooling path
type semiconductor
semiconductor device
semiconductor chip
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US20070267738A1 (en
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Hyun-Soo Chung
Cha-Jea JO
Dong-Ho Lee
Seong-Deok Hwang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HWANG, SEONG-DEOK, JO, CHA-JEA, LEE, DONG-HO, CHUNG, HYUN-SOO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Definitions

  • the invention relates to a semiconductor device, and more particularly, to a semiconductor device which includes a vertical interconnection and provides an enhanced heat dissipation path, and a stack-type semiconductor device with an enhanced heat dissipation path.
  • Such stack-type semiconductor devices have increasingly used internal wire connections using solder bumps or vertical interconnections, instead of the traditional wire bonding.
  • connections using solder bumps or vertical interconnections prevent effective dissipation of the heat generated by the densely packed semiconductor chips.
  • the invention provides a semiconductor device having an additional cooling path on its bottom surface.
  • the invention also provides a stack-type semiconductor device having an additional cooling path inside the stack-type semiconductor device.
  • a semiconductor device has a cooling path.
  • the semiconductor device comprises a first surface of a semiconductor chip in which a circuit unit is disposed; and a second surface opposite the first surface of the semiconductor chip in which a cooling path having a concave shape is disposed.
  • FIG. 1 is a cross-sectional view of a semiconductor device having a cooling path according to an embodiment of the invention
  • FIG. 2 is a bottom view of the semiconductor device of FIG. 1 ;
  • FIG. 3 is a cross-sectional view of a modified example of FIG. 1 ;
  • FIGS. 4 through 7 are cross-sectional views illustrating a method of fabricating a semiconductor device having a cooling path according to an embodiment of the invention
  • FIGS. 8 and 9 are cross-sectional views of a stack-type semiconductor device having a cooling path according to an embodiment of the invention.
  • FIG. 10 is a cross-sectional view of an example of a stack-type semiconductor device having a cooling path according to an embodiment of the invention.
  • FIGS. 11 and 12 are flowcharts illustrating methods of fabricating a stack-type semiconductor chip having a cooling path according to embodiments of the invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device having a cooling path according to an embodiment of the invention
  • FIG. 2 is a bottom view of the semiconductor device of FIG. 1 .
  • a semiconductor device 100 having a cooling path includes a first surface A of a semiconductor chip 101 in which a circuit unit (not shown) is formed, and a second surface B, opposite the first surface A, in which a cooling path 102 having an engraved shape is formed.
  • the cooling path 102 can also be described as, for example, having a concave shape or an elongate recess. However, the present invention may not be limited to such particular shapes and other shapes can be employed within the spirit and the scope of the invention as explained further below.
  • the cooling path 102 may include a plurality of channels. Each of the channels of the cooling path 102 may have an approximately semicircular cross-section. However, the channels of the cooling path 102 may be formed in various shapes including substantially rectangular or substantially polygonal shapes.
  • the semiconductor device 100 having a cooling path of FIG. 1 further includes a vertical interconnection 110 that penetrates the first surface A and the second surface B.
  • the vertical interconnection 110 is an electrical connection path between upper and lower semiconductor chips when a stack-type semiconductor device is fabricated by stacking semiconductor chips.
  • the vertical interconnection 110 may be advantageous in reducing the length and increasing the density of electrical connections in the stack-type semiconductor device.
  • a bond pad 104 is formed on the first surface A, and a passivation layer 106 is formed on the bond pad 104 and the first surface A so as to expose a portion of the bond pad 104 .
  • the bond pad 104 is electrically connected to a pad redistribution pattern 108 which extends to a scribe lane area D of the semiconductor chip.
  • a portion marked as C denotes an active region in which a circuit unit of the semiconductor device 100 is formed.
  • the vertical interconnection 110 is formed in the scribe lane area D.
  • the pad redistribution pattern 108 may be a conductive material that can be plated, such as copper, nickel or gold.
  • the scribe lane area D of the semiconductor device 100 is a region over which a blade passes in a sawing process.
  • the sawing process is used to separate individual semiconductor chips from a wafer containing a plurality of semiconductor chips. In other words, the sawing process is used to separate a wafer into a plurality of individual semiconductor chips.
  • the vertical interconnection 110 is adjacent to the active region C at both sides of the region over which the blade passes in the sawing process.
  • the bonding pad 104 may be disposed at the edge or a central portion of the semiconductor device 100 .
  • the thickness of the semiconductor device 100 having the cooling path 102 of FIG. 1 may be reduced by grinding the bottom surface, which is the second surface B of the semiconductor chip 101 .
  • a back-grinding process may be used on the second surface B to reduce the thickness of the semiconductor chip 101 to a desired thickness.
  • the thickness (WT) of the semiconductor chip 101 may be in the range of 50-100 ⁇ m and a through via depth (TD) in which the cooling path 102 is disposed may be about 1-30 ⁇ m.
  • the cooling path 102 may form a mesh pattern in the second surface B of the semiconductor device 100 .
  • the cooling path 102 does not need to be a mesh pattern.
  • the cooling path 102 may run in only one direction in the second surface B of the semiconductor device 100 .
  • the cooling path 102 is a path through which heat generated in the semiconductor device is effectively dissipated to the outside when the semiconductor device 100 is stacked on a printed circuit board (PCB) or on another semiconductor device having the same shape as the PCB (see FIG. 8 ).
  • the semiconductor device 100 may be cooled by air flow through the cooling path 102 .
  • another coolant such as water or oil may be used in the cooling path 102 .
  • the cooling path 102 formed in the second surface B may be formed in various shapes or patterns including a radial pattern.
  • FIG. 3 is a cross-sectional view of a modified example of FIG. 1 .
  • the vertical interconnection 110 is formed in the scribe lane region D using the pad redistribution pattern 108 .
  • the vertical interconnection 110 does not extend using the pad redistribution pattern 108 , but a vertical interconnection 110 A is formed by directly forming a through hole in the bond pad 104 . This can reduce the overall size of the semiconductor device 100 having the cooling path 102 .
  • FIGS. 4 through 7 are cross-sectional views illustrating a method of fabricating a semiconductor device having a cooling path according to an embodiment of the invention.
  • a semiconductor device 100 having a vertical electrode 110 is prepared.
  • the semiconductor device 100 may be in a wafer state.
  • a photoresist pattern 112 for forming a cooling path 102 is formed on the second surface B which is the bottom surface of the semiconductor device 100 .
  • the second surface B of the semiconductor device 100 is etched using the photoresist pattern 112 as an etch mask and an etchant or etch gas which can easily etch silicon, thereby forming the cooling path 102 .
  • the photoresist pattern 112 is removed by an ashing process and a sulfuric acid strip process, thereby leaving the cooling path 102 on the bottom surface of the semiconductor device 100 .
  • cooling path 102 a wet or dry etching method has been described for forming the cooling path 102 , but this is just an illustrative method.
  • the cooling path 102 may also be formed by general laser drilling or grinding.
  • FIGS. 8 and 9 are cross-sectional views of a stack-type semiconductor device having a cooling path according to an embodiment of the invention.
  • FIG. 8 is a cross-sectional view illustrating the case where two semiconductor devices 100 and 200 are bonded to each other
  • FIG. 9 is a cross-sectional view illustrating the case where a terminal for external connection, for example, a solder ball 302 , is attached to the bonded semiconductor device when the two semiconductor devices 100 and 200 are completely bonded to each other.
  • a terminal for external connection for example, a solder ball 302
  • Two semiconductor devices each having the cooling paths 102 and 202 , respectively, are aligned and bonded to each other.
  • the cooling paths 102 and 202 in the two semiconductor devices 100 and 200 are aligned with each other.
  • vertical interconnections 110 and 210 are connected using a conductive adhesion means 214 such as solder paste, and other regions are connected using an insulating adhesion means 212 such as an adhesive tape or liquid epoxy.
  • a third circular cooling path 310 is formed in the middle of a stack-type semiconductor device 300 using the first cooling path 102 in the first semiconductor device 100 and the second cooling path 202 in the second semiconductor device 200 .
  • cooling air may flow directly through the third cooling path 310 , to effectively dissipate heat generated when the stack-type semiconductor device 300 operates.
  • the first and second cooling paths 102 and 202 are aligned forming the third circular cooling path 310 , it is not necessary for the first and second cooling paths 102 and 202 to be aligned.
  • the two semiconductor devices 100 and 200 may be bonded together such that the first and second cooling paths 102 and 202 are not aligned.
  • a third circular cooling path 310 is not formed, but heat can still be removed from the two semiconductor devices 100 and 200 through their respective cooling paths 102 and 202 when the stack-type semiconductor device 300 operates.
  • the first and second cooling paths 102 and 202 may not be aligned when the first and second cooling paths 102 and 202 have different patterns.
  • the third cooling path 310 may include a plurality of channels. Each of the channels of the third cooling path 310 may have a circular shape. However, the channels of the third cooling path 310 may be formed in various shapes such as a rectangular shape or a polygonal shape.
  • a portion of the second surfaces of the first and second semiconductor devices 100 and 200 may be ground so that the first and second semiconductor devices 100 and 200 have very small thicknesses in the range of 50-100 ⁇ m. At this thickness, warpage of the first and second semiconductor devices 100 and 200 would normally occur in the direction in which a circuit unit is generally formed (directions of the arrows in FIG. 9 ). In other words, due to stresses caused by the layers and materials on the first surface of the semiconductor devices 100 and 200 and defects in the second surfaces of the semiconductor devices 100 and 200 caused by the grinding process, the semiconductor devices 100 and 200 are subject to warpage. This warpage tends to deflect the corners and edges of the semiconductor devices in the directions shown by the arrows in FIG. 9 .
  • warpage in the first and second semiconductor devices 100 and 200 is prevented by bonding the second surfaces of the first and second semiconductor devices 100 and 200 .
  • the two semiconductor devices 100 and 200 are bonded as one body to effectively double their thickness, warpage effects are effectively suppressed.
  • FIG. 10 is a cross-sectional view of an example of a stack-type semiconductor device having a cooling path according to an embodiment of the invention.
  • another stack-type semiconductor device 400 having the same structure as the stack-type semiconductor device 300 shown in FIG. 9 may be easily stacked on the stack-type semiconductor device 300 of FIG. 9 .
  • the stack-type semiconductor device 400 could include a third semiconductor device 420 and a fourth semiconductor device 430 .
  • Each of the third and fourth semiconductor devices 420 and 430 includes a first surface including a circuit unit and a second surface including a cooling path. The second surface of the third semiconductor device 420 is bonded to the second surface of the fourth semiconductor device 430 .
  • FIG. 10 shows two stack-type semiconductor devices 300 and 400 stacked, but the number of stack-type semiconductor devices may be easily increased. Electrical connection between the stack-type semiconductor devices 300 and 400 is performed by a solder ball 402 attached to the upper stack-type semiconductor device 400 .
  • the lower stack-type semiconductor device 300 must be electrically connected to a printed circuit board (PCB) 304 so that the stack-type semiconductor devices 300 and 400 can operate.
  • This electrical connection may be performed by a solder ball 302 attached to the lower stack-type semiconductor device 300 .
  • the solder balls 302 and 402 may be replaced by solder bumps formed by a plating process.
  • the PCB 304 may be a substrate used in manufacturing a ball grid array (BGA) package, a PCB used in a memory module, or a main board on which a semiconductor package is mounted.
  • the stack-type semiconductor device 300 having the cooling path 310 may be applied in a three-dimensional structure to a semiconductor device such as a multi-chip package (MCP) or a system in package (SIP) effectively dissipating heat to the outside.
  • MCP multi-chip package
  • SIP system in package
  • FIGS. 11 and 12 are flowcharts illustrating a method of fabricating a stack-type semiconductor chip having a cooling path according to an embodiment of the invention.
  • the stack-type semiconductor devices shown in FIGS. 8 and 9 may be fabricated using two methods.
  • the first method shown in FIG. 11 , two wafers each having a circuit unit formed on a first surface and a vertical interconnection perforating the wafer are prepared in operation S 100 , and a cooling path is formed on a second surface of each of the wafers using the method described with reference to FIGS. 4 through 7 , in operation S 102 .
  • the two wafers are bonded to each other so that their second surfaces having the cooling paths face each other, in operation S 104 .
  • a sawing process using a blade is performed on the bonded wafers, in operation S 106 .
  • the bonded wafers are separated into a plurality of stack-type semiconductor devices.
  • two wafers each having a circuit unit formed on a first surface and a vertical interconnection perforating the wafer are prepared in operation P 100 , and a cooling path is formed on a second surface of each of the wafers using the method described with reference to FIGS. 4 through 7 , in operation P 102 .
  • a sawing process is performed on each wafer and the two wafers are separated into unit semiconductor chips, in operation P 104 .
  • the second surfaces of the separated semiconductor chips are aligned and bonded to each other, in operation P 106 .
  • heat generated in semiconductor chips can be effectively dissipated through the cooling path, thus preventing degradation of the electrical characteristics of the semiconductor device due to heat. Also, since the bottom surfaces of the semiconductor chips are bonded to each other to fabricate a stack-type semiconductor chip, warpage is avoided even though the semiconductor chips are thin.
  • a semiconductor device having a cooling path including: a first surface of a semiconductor chip in which a circuit unit is formed; and a second surface opposite the first surface of the semiconductor chip, and in which a cooling path having a concave shape is formed.
  • the semiconductor device having a cooling path may further include a vertical interconnection which penetrates the first and second surfaces.
  • the vertical interconnection may be formed in a bond pad region of the semiconductor chip or may be electrically connected to a bond pad of the semiconductor chip using a pad redistribution pattern and may extend to a scribe lane region of the semiconductor chip.
  • a cross-section of channels of the cooling path may be approximately semicircular, rectangular or polygonal.
  • the second surface of the semiconductor device may be ground and the thickness of the semiconductor chip may be in the range of about 50-100 ⁇ m.
  • the cooling path may have an engraved depth in the range of about 1-30 ⁇ m.
  • the cooling path formed on the second surface of the semiconductor chip may be a mesh type.
  • a stack-type semiconductor device having a cooling path
  • the stack-type semiconductor device including: a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip, the first semiconductor chip comprising a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed and the second semiconductor chip comprising a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed, wherein the second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other; and a third cooling path formed in the middle of the stack-type semiconductor chip using the first and second cooling paths.
  • the first and second semiconductor chips of the stack-type semiconductor chip may further include vertical interconnections inside the stack-type semiconductor chip.
  • the vertical interconnections may be connected to each other by solder paste, in the stack-type semiconductor chip.
  • the channels of third cooling path may have a cross-section of one shape selected from a circular shape, a rectangular shape, and a polygonal shape.
  • the second surfaces of the first and second semiconductor chips may be ground and thicknesses of the first and second semiconductor chips may be in the range of about 50-100 ⁇ m.
  • the stack-type semiconductor device having a cooling path may further include another stack-type semiconductor chip formed on the stack-type semiconductor chip and having the same structure as the stack-type semiconductor chip.
  • the stack-type semiconductor device having a cooling path may further include a printed circuit board (PCB) connected to a lower portion of the stack-type semiconductor chip.
  • PCB printed circuit board
  • electrical connection between the stack-type semiconductor chip and the printed circuit board (PCB) may be performed by one selected from a solder ball and a solder bump.
  • the first and second cooling paths may be formed using one of etching, grinding, and laser drilling.
  • the stack-type semiconductor chip may be formed by bonding two wafers to each other and then sawing them or by bonding two semiconductor chips which have already been sawed, to each other.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
US11/751,464 2006-05-22 2007-05-21 Stack-type semiconductor device having cooling path on its bottom surface Active 2027-10-24 US7626260B2 (en)

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US20080286531A1 (en) * 2007-05-15 2008-11-20 Son Jae Hyun Printed circuit board provided with heat circulating medium and method for manufacturing the same
US20140071628A1 (en) * 2012-08-30 2014-03-13 International Business Machines Corporation Chip stack structures that implement two-phase cooling with radial flow
US9653430B2 (en) 2014-12-01 2017-05-16 Samsung Electronics Co., Ltd. Semiconductor devices having stacked structures and methods for fabricating the same
US9679874B2 (en) 2014-11-11 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor package and semiconductor device including the same
US11991885B2 (en) 2017-06-12 2024-05-21 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of fabricating the same

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KR100876895B1 (ko) * 2007-07-27 2009-01-07 주식회사 하이닉스반도체 반도체 칩, 이를 갖는 반도체 패키지 및 반도체 패키지의제조 방법
US8269341B2 (en) 2008-11-21 2012-09-18 Infineon Technologies Ag Cooling structures and methods
US8980688B2 (en) * 2012-06-28 2015-03-17 Soitec Semiconductor structures including fluidic microchannels for cooling and related methods
US9136233B2 (en) 2013-06-06 2015-09-15 STMicroelctronis (Crolles 2) SAS Process for fabricating a three-dimensional integrated structure with improved heat dissipation, and corresponding three-dimensional integrated structure
KR102572154B1 (ko) * 2017-11-06 2023-08-30 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법

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