US7566920B2 - Bipolar transistor and power amplifier - Google Patents

Bipolar transistor and power amplifier Download PDF

Info

Publication number
US7566920B2
US7566920B2 US11/484,753 US48475306A US7566920B2 US 7566920 B2 US7566920 B2 US 7566920B2 US 48475306 A US48475306 A US 48475306A US 7566920 B2 US7566920 B2 US 7566920B2
Authority
US
United States
Prior art keywords
base
emitter
layer
hbt
finger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/484,753
Other versions
US20070012949A1 (en
Inventor
Katsuhiko Kawashima
Masahiro Maeda
Keiichi Murayama
Hirotaka Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuvoton Technology Corp Japan
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2005204606A external-priority patent/JP2007027269A/en
Priority claimed from JP2005221213A external-priority patent/JP2007036138A/en
Application filed by Panasonic Corp filed Critical Panasonic Corp
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIYAMOTO, HIROTAKA, MURAYAMA, KEIICHI, MAEDA, MASAHIRO, KAWASHIMA, KATSUHIKO
Publication of US20070012949A1 publication Critical patent/US20070012949A1/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application granted granted Critical
Publication of US7566920B2 publication Critical patent/US7566920B2/en
Assigned to PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD. reassignment PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PANASONIC CORPORATION
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Definitions

  • the present invention relates to a bipolar transistor and a power amplifier. More particularly, the present invention relates to a bipolar transistor which is formed as an active element on a semiconductor integrated circuit for power amplification which is used in a signal transmitting section of a mobile radio terminal (a mobile telephone, etc.) which uses a radio frequency band, and a power amplifier employing the bipolar transistor.
  • a semiconductor integrated circuit for power amplification which employs, as an active element, a bipolar transistor made of a compound semiconductor which enables a radio frequency operation and a positive power supply operation, is widely used in a signal transmitting section of a mobile radio terminal, such as a mobile telephone or the like.
  • a heterojunction bipolar transistor hereinafter abbreviated as HBT
  • a base layer thereof is a p type GaAs layer
  • an emitter layer thereof in a heterojunction with the base layer is an AlGaAs or InGaP layer having a large band gap.
  • the HBT generally has a multi-finger structure in which one or a plurality of stripline-type emitter fingers are arranged side by side. See, for example, Japanese Patent Laid-Open Publication No. 6-342803 and Japanese Patent Laid-Open Publication No. 2002-110904.
  • FIGS. 10A and 10B are a plan view and a cross-sectional view illustrating an exemplary HBT structure in which one emitter finger is provided.
  • one emitter finger an emitter layer 104 and an emitter electrode 101
  • base fingers base electrodes 102
  • an output power of the HBT is determined, depending on an area of the emitter. Therefore, in the case of the HBT having one emitter finger, a length L of the emitter finger needs to be large so as to achieve a high output power. However, the emitter finger needlessly occupies a semiconductor chip area.
  • FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating an exemplary HBT structure in which four emitter fingers are provided.
  • four emitter fingers and five base fingers provided on both sides of the emitter fingers are interposed between two collector fingers.
  • a high-output power HBT can be achieved using the emitter fingers each having a length L smaller than that of the HBT of FIG. 10A .
  • FIGS. 12A and 12B A multi-cell structure in which the multi-finger structure HBT having excellent radio frequency characteristics is considered as a unit cell and a plurality of the HBT cells are connected in parallel to combine outputs thereof, is widely used as a power-amplification HBT structure.
  • Exemplary power-amplification HBTs having the multi-cell structure are illustrated in FIGS. 12A and 12B .
  • FIG. 12A illustrates an exemplary multi-cell structure in which a plurality of HBT cells each having one emitter finger are provided.
  • FIG. 12B illustrates a multi-cell structure in which a plurality of HBT cells each having four emitter fingers are provided.
  • FIGS. 12A illustrates an exemplary multi-cell structure in which a plurality of HBT cells each having one emitter finger are provided.
  • FIG. 12B illustrates a multi-cell structure in which a plurality of HBT cells each having four emitter fingers are provided.
  • the collector outputs of the HBT cells are collectively connected to a common collector conductor 100
  • the emitters of the HBT cells are collectively connected to a common emitter conductor 110 .
  • the emitter conductor 110 is provided with a via hole 120 and is grounded via the via hole 120 .
  • each HBT cell generates heat due to high current density.
  • the HBT cells do not uniformly generate heat, so that a failure occurs in the operation of the HBT cell due to non-uniformity of heat generation between each HBT cell. More specifically, the HBT cell having a temperature higher than the surrounding having a high increase in temperature further generates heat due to positive feedback (thermal runaway), finally leading to breakdown.
  • heat generation is not uniform between each HBT cell, none of the HBT emitters effectively functions, resulting in a deterioration in radio frequency characteristics.
  • a method of inserting an external base resistance 130 between a DC bias supply line 150 for supplying a DC bias to each HBT cell and a base conductor 140 of each HBT cell is employed as clearly illustrated in FIGS. 12A and 12B .
  • the external base resistance 130 is used to stabilize an operation of the HBT cell, and is generally called a base ballast resistance.
  • ballast resistance to the emitter of each HBT cell, an increase in collector current is also suppressed, thereby making it possible to avoid thermal runaway.
  • a base ballast resistance is used more often than a collector ballast resistance is, in view of the narrowness of a value range within which the ballast resistance can take.
  • the conventional power-amplification HBT employing a base ballast resistance takes measures against the non-uniformity of heat generation between each HBT cell, however, the non-uniformity of heat generation in each HBT cell is not taken into consideration.
  • the non-uniformity of heat generation in each HBT cell refers to the non-uniformity of heat generation between each emitter finger, which occurs due to the following cause.
  • a base-collector parasitic capacitance is high, and power feedback due to the parasitic capacitance causes a gain deterioration in radio frequency band applications.
  • the radio frequency characteristics of the HBT are determined, mainly depending on a parasitic capacitance occurring between the base layer and the collector layer, and the parasitic capacitance is proportional to a base mesa width W 1 illustrated in FIGS. 10B and 11B . This is because the base-collector capacitance is proportional to areas between the base layers sandwiching the collector layer, and the collector layer. In order to reduce the base mesa width W 1 , it is necessary to reduce areas other than a required emitter area to the extent possible.
  • the HBT cell structure of FIG. 10B has five bases for four emitters and the HBT cell structure of FIG. 10B has two bases for one emitter, i.e., the base area is invariably larger by an area corresponding to one base electrode than the required emitter area.
  • the base mesa width W 1 due to the influence of the base finger, resulting in a deterioration in gain characteristics in a radio frequency band.
  • the value of the external base resistance 130 is large as illustrated in FIGS. 12A and 12B . Therefore, when the power-amplification HBT is actually integrated on a semiconductor, a large area needs to be secured for an external base resistance, resulting in a large chip area, i.e., an increase in cost.
  • an object of the present invention is to provide a bipolar transistor which has uniform heat generation in an HBT cell and improves gain characteristics in a radio frequency band, and a power amplifier which employs a multi-cell structure to reduce a chip area.
  • a bipolar transistor of the present invention is directed to a bipolar transistor formed on a semiconductor substrate.
  • a bipolar transistor of the present invention comprises a base finger, two emitter fingers disposed symmetric with respect to the base finger as a center, and in parallel with the base finger, and two collector fingers disposed sandwiching the base finger and the two emitter fingers. Note that an even number of emitter fingers may be disposed symmetric with respect to the base finger as a center and longitudinally disposed in parallel with the base finger.
  • the two emitter fingers each have a length of 30 ⁇ m or less.
  • the base finger has an electrode width of 1 ⁇ m or less.
  • the base finger can have an electrode having a structure in which the electrode penetrates through a wide gap layer of the emitter layer to ohmically join the base layer.
  • a power amplifier which comprises a plurality of the bipolar transistors, wherein bases thereof are connected in common, collectors thereof are connected to a radio frequency signal output terminal, and emitters are grounded, a capacitance inserted between the radio frequency signal input terminal and the bases connected in common, and a resistance inserted between a bias supply terminal and the bases connected in common.
  • a uniform operation in a cell is excellent, and a base-collector capacitance can be reduced, thereby obtaining excellent radio frequency characteristics with low cost.
  • an internal base resistance value is high, when a power amplifier having a multi-cell structure is configured, a power amplifier having a small size and an excellent breakdown withstanding property without an external base resistance can be achieved.
  • FIG. 1A is a plan view illustrating a structure of a bipolar transistor according to an embodiment of the present invention
  • FIG. 1B is a cross-sectional view illustrating the bipolar transistor, taken along line a-a in FIG. 1A ;
  • FIG. 2 is a diagram illustrating a unit cell temperature distribution of the bipolar transistor of FIG. 1A ;
  • FIG. 3 is a characteristics diagram illustrating a correlation between an emitter finger length and a breakdown withstanding property
  • FIG. 4 is a diagram illustrating an exemplary configuration of a power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 1A ;
  • FIG. 5 is a characteristics diagram illustrating a correlation between a base electrode width (an internal base resistance value) and a breakdown withstanding property
  • FIG. 6A is a plan view illustrating another bipolar transistor according to an embodiment of the present invention.
  • FIG. 6B is a diagram illustrating an exemplary configuration of a power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 6A ;
  • FIG. 7 is a diagram for describing steps of fabricating the bipolar transistor of the embodiment of the present invention of FIG. 1B ;
  • FIG. 8 is a diagram for describing other steps of fabricating a bipolar transistor obtained by modifying that of FIG. 1B ;
  • FIG. 9A is a diagram illustrating an exemplary configuration of a power amplifier in which a plurality of the bipolar transistors of the embodiment of the present invention are connected in parallel;
  • FIG. 9B is an equivalent circuit diagram illustrating the power amplifier of FIG. 9A ;
  • FIG. 10A is a plan view illustrating a structure of a conventional bipolar transistor
  • FIG. 10B is a cross-sectional view illustrating the bipolar transistor, taken along line c-c in FIG. 10A .
  • FIG. 11A is a plan view illustrating a structure of another conventional bipolar transistor
  • FIG. 11B is a cross-sectional view illustrating the bipolar transistor, taken along line d-d in FIG. 11A .
  • FIG. 12A is a diagram illustrating an exemplary configuration of a conventional power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 10A ;
  • FIG. 12B is a diagram illustrating an exemplary configuration of a conventional power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 11A ;
  • FIG. 13 is a diagram illustrating a unit cell temperature distribution of the bipolar transistor of FIG. 11A .
  • FIG. 1A is a plan view illustrating the structure of the bipolar transistor according to the embodiment of the present invention.
  • FIG. 1B is a cross-sectional view illustrating the bipolar transistor, taken along line a-a in FIG. 1A .
  • a base mesa finger an emitter ledge layer 15 , a base layer 16 , and a collector layer 17
  • collector electrodes 13 two collector fingers
  • one base finger a base electrode 12
  • two emitter fingers an emitter layer 14 and an emitter electrode 11
  • the two emitter fingers are formed at locations symmetric with respect to the base finger as a reference.
  • This bipolar transistor is typically a heterojunction bipolar transistor (HBT).
  • HBT heterojunction bipolar transistor
  • the two emitter fingers are provided at locations symmetric with respect to the base finger, the two emitter fingers have a uniform head generation as illustrated in FIG. 2 . Since there is only one base finger, the non-uniformity problem with base fingers does not occur.
  • the emitter finger preferably has a length L of 30 ⁇ m or less so as to prevent occurrence of non-uniformity.
  • a length L of 30 ⁇ m or less so as to prevent occurrence of non-uniformity.
  • the larger the value the higher the stability of the device.
  • the number of base fingers per emitter finger is minimum. Therefore, an area of the base finger with respect to an emitter area corresponding to a required output power is small, so that an area of the base layer which is larger than the emitter area can be reduced. Therefore, the base mesa width W 1 can be narrowed, so that a base-collector capacitance can be reduced, thereby making it possible to achieve a high gain in a radio frequency band.
  • FIG. 4 illustrates an exemplary structure of a power-amplification HBT in which the bipolar transistor of the present invention is considered as one cell, and a plurality of cells are connected in parallel.
  • FIG. 5 illustrates a characteristic correlation diagram of the base electrode width, a breakdown withstanding property, and a base-contact resistance, where the emitter finger length L of the HBT is 30 ⁇ m. As can be seen from FIG.
  • the transistor when the base electrode width is 1 ⁇ m or less, the transistor has a parasitic base resistance of as high as 20 ⁇ , and the breakdown withstanding performance is high, so that a base ballast resistance for preventing thermal runaway is no longer required. Therefore, when a power-amplification HBT is configured to have a structure in which a bipolar transistor is considered as one cell and a plurality of cells are connected in parallel, an area of the configuration can be reduced by an amount corresponding to the external base resistance (base ballast resistance) 130 required for the conventional configuration ( FIG. 11A , etc.).
  • FIG. 6A illustrates an exemplary structure of the bipolar transistor. Despite a long base finger length, one base mesa portion has a base resistance of about 20 ⁇ , so that non-uniformity is suppressed in two base mesa portions in a new unit cell. According to the structure of the present invention, cells can be easily connected, and a new cell can be configured.
  • FIG. 6B illustrates an exemplary configuration of a power-amplification HBT in which this bipolar transistor is considered as one cell and a plurality of cells are connected in parallel.
  • FIG. 7 is a diagram for describing steps A to E of fabricating the bipolar transistor of the embodiment of the present invention of FIG. 1B .
  • An emitter portion is a layer including the n type GaAs emitter layer 14 and the n type InGaP emitter ledge layer 15 .
  • a layer which contacts the emitter electrode 11 made of WSi requires ohmic contact. Therefore, a thin layer of InGaAs is provided at an uppermost layer of the emitter.
  • the p type GaAs base layer 16 (base portion) is provided under the emitter portion.
  • the n type GaAs collector layer 17 is provided under the p type GaAs base layer 16 .
  • An n+ type GaAs sub-collector layer 18 (called sub-collector layer) which is doped at a high concentration is provided under the n type GaAs collector layer 17 .
  • This epitaxial layer is subjected to an etching process to form an emitter mesa layer and a base mesa layer, thereby forming three terminal electrodes of the transistor on the semiconductor layer. In this manner, the transistor is fabricated.
  • the collector electrode 13 is made of an alloy of Ni/AuGe/Au, and the base electrode 12 is made of Ti/Pt/Au.
  • the n type GaAs emitter layer 14 is etched while masking the WSi emitter electrode 11 formed on an emitter region, to expose the n type InGaP emitter ledge layer 15 (step A). In this case, selective etching of GaAs and InGaP is used.
  • the n type InGaP emitter ledge layer 15 , the p type GaAs base layer 16 , and the n type GaAs collector layer 17 are etched to expose the n+ type GaAs sub-collector layer 18 (step B).
  • the step B is a step of forming the base mesa layer. The smaller the base mesa width W 1 , the smaller the base-collector capacitance, i.e., the more excellent the radio frequency characteristics.
  • a surface of the p type base layer exposed by etching and removing the emitter portion has a number of surface states, and surface recombination in the states causes crystal deterioration.
  • an emitter ledge layer To take measures against this problem, such large a base layer surface surrounding a required area of the emitter layer as possible is protected by depositing another stable layer (i.e., an emitter ledge layer).
  • This structure employing the emitter ledge layer is also called a girdling structure.
  • the n type InGaP emitter ledge layer 15 is etched within an emitter mesa interval W 4 to expose the p type GaAs base layer 16 (step C). This etching is selective etching, thereby forming an opening having a ledge opening width W 2 .
  • a high-precision photolithography technique and a high-precision etching technique are required, i.e., a high-cost fabrication method is required.
  • the base electrode 12 having a width of 1 ⁇ m or less and made of Ti/Pt/Au is formed using deposition lift-off (step D).
  • the collector electrode 13 made of AuGeNi/Au is formed on the n+ type GaAs sub-collector layer 18 using deposition lift-off, followed by heating at about 400° C. into an alloy (step E).
  • the fabrication cost is increased as described above.
  • FIG. 8 a simplified version of this fabrication method and an HBT structure fabricated with this simplified method are illustrated in FIG. 8 .
  • a ledge opening is not originally provided, and a base electrode 82 penetrates through the n type InGaP emitter ledge layer 15 which is typically in a heterojunction with the p type GaAs base layer 16 , to contact the p type GaAs base layer 16 .
  • a step of etching the n type InGaP emitter ledge layer 15 to form a small opening is not required, resulting in a simple fabrication method.
  • the base electrode 82 is thermally diffused into the n type InGaP emitter ledge layer 15 by heating, so that the base electrode 82 contacts the p type GaAs base layer 16 .
  • a ledge opening width is not present, and the base width W 3 is narrow, so that the base mesa width W 1 can be caused to be smaller than that of any structure, and the base-collector capacitance is also small, resulting in an improvement in gain and efficiency and satisfactory radio frequency characteristics.
  • the collector electrode 13 is made of an alloy of Ni/AuGe/Au
  • the base electrode 82 is made of Pt/Ti/Pt/Au where Pt is introduced into a lowermost layer.
  • the n type GaAs emitter layer 14 is etched while masking the WSi emitter electrode 11 formed on the emitter region, to expose the n type InGaP emitter ledge layer 15 (step A). In this case, selective etching of GaAs and InGaP is used.
  • the n type InGaP emitter ledge layer 15 , the p type GaAs base layer 16 , and the n type GaAs collector layer 17 are etched to expose the n+ type GaAs sub-collector layer 18 (step B).
  • the step B is a step of forming the base mesa layer. The smaller the base mesa width W 1 , the smaller the base-collector capacitance, i.e., the more excellent the radio frequency characteristics. Steps A and B are the same as those of FIG. 7 .
  • the base electrode 82 made of Pt/Ti/Pt/Au is formed on n type InGaP emitter ledge layer 15 using deposition lift-off (step F).
  • the collector electrode 13 made of AuGeNi/Au is formed using deposition lift-off, followed by heating at about 400° C. into an alloy to form the collector electrode 13 (step G). The heating at about 400° C.
  • the improvement of radio frequency performance does not require a high-performance fabrication method for forming the high-precision narrow emitter ledge opening width W 2 in the narrow emitter mesa interval W 4 , resulting in low cost.
  • W 1 >W 4 >W 3 is required, the emitter mesa interval W 4 can be caused to be narrower for the same base width W 3 , and as a result, the base mesa width W 1 can be narrowed. Thereby, the base-collector capacitance can be further reduced, thereby making it possible to improve performance in a radio frequency band.
  • FIG. 9A is a diagram illustrating an exemplary configuration of a power amplifier in which a plurality of the bipolar transistors of the embodiment of the present invention of FIG. 1B are connected in parallel.
  • FIG. 9B is an equivalent circuit diagram illustrating the power amplifier of FIG. 9A .
  • four bipolar transistors are connected in parallel.
  • the power amplifier is composed of a plurality of bipolar transistors Q, a capacitance C, and a resistance R.
  • the base electrodes of the plurality of bipolar transistors Q are connected in common via the capacitance C to a radio frequency signal input (RF input) terminal and via the resistance R to a bias supply (DC input) terminal.
  • the capacitance C is a capacitance for passing a radio frequency signal.
  • the resistance R is a suppression resistance for preventing an excessive amount of base current from flowing.
  • the emitter electrodes of the plurality of bipolar transistors Q are grounded via a common conductor and a via hole.
  • the collector electrodes of the plurality of bipolar transistors Q are connected in common to a radio frequency signal output (RF output) terminal.
  • the power amplifier has the structure in which a plurality of the bipolar transistors of FIG. 1B are connected in parallel, the base-collector capacitance is small, so that the gain and the efficiency are improved, resulting in satisfactory radio frequency characteristics.
  • the breakdown withstanding property is high, so that a base ballast resistance for preventing thermal runaway is no longer required.
  • the area of the configuration can be reduced by an amount corresponding to the external base resistance (base ballast resistance) 130 which is required for the conventional configuration ( FIG. 11A , etc.).
  • the bipolar transistor of the embodiment of the present invention there is an excellent uniform operation in a cell, and the base-collector capacitance can be reduced, thereby obtaining excellent radio frequency characteristics with low cost.
  • a power amplifier having a small size (without an external base resistance) and an excellent breakdown withstanding property can be achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bipolar transistor and a power amplifier. More particularly, the present invention relates to a bipolar transistor which is formed as an active element on a semiconductor integrated circuit for power amplification which is used in a signal transmitting section of a mobile radio terminal (a mobile telephone, etc.) which uses a radio frequency band, and a power amplifier employing the bipolar transistor.
2. Description of the Background Art
In recent years, a semiconductor integrated circuit for power amplification which employs, as an active element, a bipolar transistor made of a compound semiconductor which enables a radio frequency operation and a positive power supply operation, is widely used in a signal transmitting section of a mobile radio terminal, such as a mobile telephone or the like. Particularly, a heterojunction bipolar transistor (hereinafter abbreviated as HBT) is widely used in which a base layer thereof is a p type GaAs layer, and an emitter layer thereof in a heterojunction with the base layer is an AlGaAs or InGaP layer having a large band gap. The reason why the HBT is adopted among bipolar transistors is that holes of the base layer can be prevented from flowing backward into the emitter layer and recombining with electron carriers of the emitter, thereby increasing the efficiency of injection of electron carriers from the emitter to the base, resulting in a high-efficiency operation of the transistor.
The HBT generally has a multi-finger structure in which one or a plurality of stripline-type emitter fingers are arranged side by side. See, for example, Japanese Patent Laid-Open Publication No. 6-342803 and Japanese Patent Laid-Open Publication No. 2002-110904. FIGS. 10A and 10B are a plan view and a cross-sectional view illustrating an exemplary HBT structure in which one emitter finger is provided. In the structure of the conventional HBT of FIGS. 10A and 10B, one emitter finger (an emitter layer 104 and an emitter electrode 101) and two base fingers (base electrodes 102) provided on both sides of the emitter finger, are interposed between two collector fingers (collector electrodes 103). Typically, an output power of the HBT is determined, depending on an area of the emitter. Therefore, in the case of the HBT having one emitter finger, a length L of the emitter finger needs to be large so as to achieve a high output power. However, the emitter finger needlessly occupies a semiconductor chip area.
To avoid this, a plurality of emitter fingers are provided so as to achieve a high output power of the HBT without increasing the emitter finger length L. FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating an exemplary HBT structure in which four emitter fingers are provided. In the structure of the conventional HBT of FIGS. 11A and 11B, four emitter fingers and five base fingers provided on both sides of the emitter fingers, are interposed between two collector fingers. In the case of the HBT of FIG. 11A, since the emitter area can be occupied by the plurality of emitter fingers, a high-output power HBT can be achieved using the emitter fingers each having a length L smaller than that of the HBT of FIG. 10A.
A multi-cell structure in which the multi-finger structure HBT having excellent radio frequency characteristics is considered as a unit cell and a plurality of the HBT cells are connected in parallel to combine outputs thereof, is widely used as a power-amplification HBT structure. Exemplary power-amplification HBTs having the multi-cell structure are illustrated in FIGS. 12A and 12B. FIG. 12A illustrates an exemplary multi-cell structure in which a plurality of HBT cells each having one emitter finger are provided. FIG. 12B illustrates a multi-cell structure in which a plurality of HBT cells each having four emitter fingers are provided. In FIGS. 12A and 12B, the collector outputs of the HBT cells are collectively connected to a common collector conductor 100, and the emitters of the HBT cells are collectively connected to a common emitter conductor 110. The emitter conductor 110 is provided with a via hole 120 and is grounded via the via hole 120.
However, in the case of such a multi-cell structure, the following points should be noted. In the power-amplification HBT, each HBT cell generates heat due to high current density. However, the HBT cells do not uniformly generate heat, so that a failure occurs in the operation of the HBT cell due to non-uniformity of heat generation between each HBT cell. More specifically, the HBT cell having a temperature higher than the surrounding having a high increase in temperature further generates heat due to positive feedback (thermal runaway), finally leading to breakdown. Also, when heat generation is not uniform between each HBT cell, none of the HBT emitters effectively functions, resulting in a deterioration in radio frequency characteristics.
Therefore, in order to correct the non-uniformity of heat generation between each HBT cell, a method of inserting an external base resistance 130 between a DC bias supply line 150 for supplying a DC bias to each HBT cell and a base conductor 140 of each HBT cell, is employed as clearly illustrated in FIGS. 12A and 12B. By insertion of the external base resistance 130, an increase in base current of the HBT can be suppressed, thereby making it possible to avoid thermal runaway even if temperature increases. The external base resistance 130 is used to stabilize an operation of the HBT cell, and is generally called a base ballast resistance. Note that, by providing a ballast resistance to the emitter of each HBT cell, an increase in collector current is also suppressed, thereby making it possible to avoid thermal runaway. However, recently, a base ballast resistance is used more often than a collector ballast resistance is, in view of the narrowness of a value range within which the ballast resistance can take.
As described above, the conventional power-amplification HBT employing a base ballast resistance takes measures against the non-uniformity of heat generation between each HBT cell, however, the non-uniformity of heat generation in each HBT cell is not taken into consideration. The non-uniformity of heat generation in each HBT cell refers to the non-uniformity of heat generation between each emitter finger, which occurs due to the following cause.
In the HBT cell having four emitter fingers of FIG. 11A, when all of the emitter fingers generate almost the same amount of heat, two central emitter fingers are affected by heat from two outer emitter fingers, so that the two central emitter fingers have a higher temperature. Specifically, heat generation distribution regions of the two central emitter fingers overlap heat generation distribution regions of the two outer emitter fingers, so that the two central emitter fingers have a higher temperature (see FIG. 13). Note that, in order to correct the problem, it is considered to provide a sufficient interval between each emitter finger to completely separate the heat generation distribution regions from each other. In this case, however, the area of the HBT cell is increased, resulting in newly arising problems: an increase in chip area; a deterioration in radio frequency characteristics; and the like. Therefore, it is not practical.
In the case of the HBT cell of FIG. 11A, since the five base fingers are provided on both the sides of the four emitter fingers, non-uniformity is likely to occur between each finger in terms of a contact resistance of the base electrode and the base layer of each base finger. Therefore, non-uniformity occurs in the injection amount of a base current, resulting in non-uniformity between each emitter finger.
This problem similarly exists in the HBT cell having one emitter finger and two base fingers of FIG. 10A. Specifically, non-uniformity is likely to occur between the two base fingers in terms of a contact resistance of the base electrode and the base layer of the two base fingers. Particularly, in this HBT cell, the base finger is long, corresponding to the emitter finger, so that the non-uniformity of the contact resistance increases in the length direction. Due to non-uniformity of the base resistances of both the sides, non-uniformity in the operation of the HBT cell increases. For example, a current flowing through the emitter finger is larger in a portion closer to the right base finger than in a portion closer to the left base finger.
Further, in the HBT cell, a base-collector parasitic capacitance is high, and power feedback due to the parasitic capacitance causes a gain deterioration in radio frequency band applications. The radio frequency characteristics of the HBT are determined, mainly depending on a parasitic capacitance occurring between the base layer and the collector layer, and the parasitic capacitance is proportional to a base mesa width W1 illustrated in FIGS. 10B and 11B. This is because the base-collector capacitance is proportional to areas between the base layers sandwiching the collector layer, and the collector layer. In order to reduce the base mesa width W1, it is necessary to reduce areas other than a required emitter area to the extent possible. However, the HBT cell structure of FIG. 11B has five bases for four emitters and the HBT cell structure of FIG. 10B has two bases for one emitter, i.e., the base area is invariably larger by an area corresponding to one base electrode than the required emitter area. Thus, in the conventional HBT cell structure, there is a limitation on the reduction of the base mesa width W1 due to the influence of the base finger, resulting in a deterioration in gain characteristics in a radio frequency band.
On the other hand, in the power-amplification HBT having the multi-cell structure, the value of the external base resistance 130 is large as illustrated in FIGS. 12A and 12B. Therefore, when the power-amplification HBT is actually integrated on a semiconductor, a large area needs to be secured for an external base resistance, resulting in a large chip area, i.e., an increase in cost.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a bipolar transistor which has uniform heat generation in an HBT cell and improves gain characteristics in a radio frequency band, and a power amplifier which employs a multi-cell structure to reduce a chip area.
The present invention is directed to a bipolar transistor formed on a semiconductor substrate. To achieve the object, a bipolar transistor of the present invention comprises a base finger, two emitter fingers disposed symmetric with respect to the base finger as a center, and in parallel with the base finger, and two collector fingers disposed sandwiching the base finger and the two emitter fingers. Note that an even number of emitter fingers may be disposed symmetric with respect to the base finger as a center and longitudinally disposed in parallel with the base finger.
Preferably, the two emitter fingers each have a length of 30 μm or less. Also, preferably, the base finger has an electrode width of 1 μm or less.
When the bipolar transistor is a heterojunction bipolar transistor having an emitter layer which is in a heterojunction with the base layer, the base finger can have an electrode having a structure in which the electrode penetrates through a wide gap layer of the emitter layer to ohmically join the base layer.
In addition, a power amplifier can be provided which comprises a plurality of the bipolar transistors, wherein bases thereof are connected in common, collectors thereof are connected to a radio frequency signal output terminal, and emitters are grounded, a capacitance inserted between the radio frequency signal input terminal and the bases connected in common, and a resistance inserted between a bias supply terminal and the bases connected in common.
According to the present invention, a uniform operation in a cell is excellent, and a base-collector capacitance can be reduced, thereby obtaining excellent radio frequency characteristics with low cost. In addition, since an internal base resistance value is high, when a power amplifier having a multi-cell structure is configured, a power amplifier having a small size and an excellent breakdown withstanding property without an external base resistance can be achieved.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a plan view illustrating a structure of a bipolar transistor according to an embodiment of the present invention;
FIG. 1B is a cross-sectional view illustrating the bipolar transistor, taken along line a-a in FIG. 1A;
FIG. 2 is a diagram illustrating a unit cell temperature distribution of the bipolar transistor of FIG. 1A;
FIG. 3 is a characteristics diagram illustrating a correlation between an emitter finger length and a breakdown withstanding property;
FIG. 4 is a diagram illustrating an exemplary configuration of a power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 1A;
FIG. 5 is a characteristics diagram illustrating a correlation between a base electrode width (an internal base resistance value) and a breakdown withstanding property;
FIG. 6A is a plan view illustrating another bipolar transistor according to an embodiment of the present invention;
FIG. 6B is a diagram illustrating an exemplary configuration of a power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 6A;
FIG. 7 is a diagram for describing steps of fabricating the bipolar transistor of the embodiment of the present invention of FIG. 1B;
FIG. 8 is a diagram for describing other steps of fabricating a bipolar transistor obtained by modifying that of FIG. 1B;
FIG. 9A is a diagram illustrating an exemplary configuration of a power amplifier in which a plurality of the bipolar transistors of the embodiment of the present invention are connected in parallel;
FIG. 9B is an equivalent circuit diagram illustrating the power amplifier of FIG. 9A;
FIG. 10A is a plan view illustrating a structure of a conventional bipolar transistor;
FIG. 10B is a cross-sectional view illustrating the bipolar transistor, taken along line c-c in FIG. 10A.
FIG. 11A is a plan view illustrating a structure of another conventional bipolar transistor;
FIG. 11B is a cross-sectional view illustrating the bipolar transistor, taken along line d-d in FIG. 11A.
FIG. 12A is a diagram illustrating an exemplary configuration of a conventional power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 10A;
FIG. 12B is a diagram illustrating an exemplary configuration of a conventional power-amplification HBT having a multi-cell structure where each cell is the bipolar transistor of FIG. 11A; and
FIG. 13 is a diagram illustrating a unit cell temperature distribution of the bipolar transistor of FIG. 11A.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
(Structure of Bipolar Transistor)
Initially, a structure of a bipolar transistor according to an embodiment of the present invention will be described.
FIG. 1A is a plan view illustrating the structure of the bipolar transistor according to the embodiment of the present invention. FIG. 1B is a cross-sectional view illustrating the bipolar transistor, taken along line a-a in FIG. 1A. In the structure of the bipolar transistor of this embodiment, a base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and one base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed on the base mesa finger. The two emitter fingers are formed at locations symmetric with respect to the base finger as a reference. This bipolar transistor is typically a heterojunction bipolar transistor (HBT).
In the structure of the bipolar transistor of this embodiment, since the two emitter fingers are provided at locations symmetric with respect to the base finger, the two emitter fingers have a uniform head generation as illustrated in FIG. 2. Since there is only one base finger, the non-uniformity problem with base fingers does not occur.
The emitter finger preferably has a length L of 30 μm or less so as to prevent occurrence of non-uniformity. For example, as illustrated in FIG. 3, characteristics of an applied power with respect to a saturated output which breaks one HBT cell due to thermal runaway where the HBT has an output load VSWR=10:1, are considered as an indicator indicating non-uniformity. In this case, the larger the value, the higher the stability of the device. Even when the emitter finger length L is 30 μm or less, and the applied power is 5 dB, the HBT is not broken.
Further, in the structure of the bipolar transistor of this embodiment, since only one base finger is provided between the two emitter fingers, the number of base fingers per emitter finger is minimum. Therefore, an area of the base finger with respect to an emitter area corresponding to a required output power is small, so that an area of the base layer which is larger than the emitter area can be reduced. Therefore, the base mesa width W1 can be narrowed, so that a base-collector capacitance can be reduced, thereby making it possible to achieve a high gain in a radio frequency band.
Here, if a width of the base electrode 12 is set to be 1 μm or less, a contact area of the base electrode 12 and the base layer 16 is small, so that the contact resistance is large. FIG. 4 illustrates an exemplary structure of a power-amplification HBT in which the bipolar transistor of the present invention is considered as one cell, and a plurality of cells are connected in parallel. FIG. 5 illustrates a characteristic correlation diagram of the base electrode width, a breakdown withstanding property, and a base-contact resistance, where the emitter finger length L of the HBT is 30 μm. As can be seen from FIG. 5, when the base electrode width is 1 μm or less, the transistor has a parasitic base resistance of as high as 20Ω, and the breakdown withstanding performance is high, so that a base ballast resistance for preventing thermal runaway is no longer required. Therefore, when a power-amplification HBT is configured to have a structure in which a bipolar transistor is considered as one cell and a plurality of cells are connected in parallel, an area of the configuration can be reduced by an amount corresponding to the external base resistance (base ballast resistance) 130 required for the conventional configuration (FIG. 11A, etc.).
Note that, when a large number of cells are required to obtain high output characteristics of a power amplifier, HBT cells having a structure in which two or more base mesas are provided and the base electrode 12 and the collector electrode 13 are used in common, may be fabricated. FIG. 6A illustrates an exemplary structure of the bipolar transistor. Despite a long base finger length, one base mesa portion has a base resistance of about 20Ω, so that non-uniformity is suppressed in two base mesa portions in a new unit cell. According to the structure of the present invention, cells can be easily connected, and a new cell can be configured. FIG. 6B illustrates an exemplary configuration of a power-amplification HBT in which this bipolar transistor is considered as one cell and a plurality of cells are connected in parallel.
(Method for Fabricating Bipolar Transistor)
Next, a method for fabricating the bipolar transistor of the embodiment of the present invention will be described.
FIG. 7 is a diagram for describing steps A to E of fabricating the bipolar transistor of the embodiment of the present invention of FIG. 1B.
An emitter portion is a layer including the n type GaAs emitter layer 14 and the n type InGaP emitter ledge layer 15. A layer which contacts the emitter electrode 11 made of WSi requires ohmic contact. Therefore, a thin layer of InGaAs is provided at an uppermost layer of the emitter. The p type GaAs base layer 16 (base portion) is provided under the emitter portion. The n type GaAs collector layer 17 is provided under the p type GaAs base layer 16. An n+ type GaAs sub-collector layer 18 (called sub-collector layer) which is doped at a high concentration is provided under the n type GaAs collector layer 17. This epitaxial layer is subjected to an etching process to form an emitter mesa layer and a base mesa layer, thereby forming three terminal electrodes of the transistor on the semiconductor layer. In this manner, the transistor is fabricated.
For the HBT, selective etching of GaAs and InGaP can be used in the etching step. The collector electrode 13 is made of an alloy of Ni/AuGe/Au, and the base electrode 12 is made of Ti/Pt/Au.
Initially, the n type GaAs emitter layer 14 is etched while masking the WSi emitter electrode 11 formed on an emitter region, to expose the n type InGaP emitter ledge layer 15 (step A). In this case, selective etching of GaAs and InGaP is used. Next, the n type InGaP emitter ledge layer 15, the p type GaAs base layer 16, and the n type GaAs collector layer 17 are etched to expose the n+ type GaAs sub-collector layer 18 (step B). The step B is a step of forming the base mesa layer. The smaller the base mesa width W1, the smaller the base-collector capacitance, i.e., the more excellent the radio frequency characteristics.
Here, a function of the heterojunction emitter ledge layer will be briefly described. A surface of the p type base layer exposed by etching and removing the emitter portion has a number of surface states, and surface recombination in the states causes crystal deterioration. To take measures against this problem, such large a base layer surface surrounding a required area of the emitter layer as possible is protected by depositing another stable layer (i.e., an emitter ledge layer). This structure employing the emitter ledge layer is also called a girdling structure.
The n type InGaP emitter ledge layer 15 is etched within an emitter mesa interval W4 to expose the p type GaAs base layer 16 (step C). This etching is selective etching, thereby forming an opening having a ledge opening width W2. When the high-precision narrow emitter ledge opening width W2 is formed in the narrow emitter mesa interval W4 to increase a radio frequency performance, a high-precision photolithography technique and a high-precision etching technique are required, i.e., a high-cost fabrication method is required.
Next, the base electrode 12 having a width of 1 μm or less and made of Ti/Pt/Au is formed using deposition lift-off (step D). Next, the collector electrode 13 made of AuGeNi/Au is formed on the n+ type GaAs sub-collector layer 18 using deposition lift-off, followed by heating at about 400° C. into an alloy (step E).
In the HBT having excellent radio frequency characteristics, in order to improve a function thereof in a radio frequency band, it is necessary to narrow the base mesa width W1, secure the ledge opening width W2 in the narrow base mesa width W1, and form a base electrode having a width of 1 μm or less. However, the fabrication cost is increased as described above.
Therefore, a simplified version of this fabrication method and an HBT structure fabricated with this simplified method are illustrated in FIG. 8. In the HBT structure of FIG. 8, a ledge opening is not originally provided, and a base electrode 82 penetrates through the n type InGaP emitter ledge layer 15 which is typically in a heterojunction with the p type GaAs base layer 16, to contact the p type GaAs base layer 16. In the HBT structure, a step of etching the n type InGaP emitter ledge layer 15 to form a small opening is not required, resulting in a simple fabrication method. After the base electrode 82 is deposited and formed on the n type InGaP emitter ledge layer 15, the base electrode 82 is thermally diffused into the n type InGaP emitter ledge layer 15 by heating, so that the base electrode 82 contacts the p type GaAs base layer 16. In this structure, a ledge opening width is not present, and the base width W3 is narrow, so that the base mesa width W1 can be caused to be smaller than that of any structure, and the base-collector capacitance is also small, resulting in an improvement in gain and efficiency and satisfactory radio frequency characteristics.
Note that the collector electrode 13 is made of an alloy of Ni/AuGe/Au, and the base electrode 82 is made of Pt/Ti/Pt/Au where Pt is introduced into a lowermost layer.
Initially, the n type GaAs emitter layer 14 is etched while masking the WSi emitter electrode 11 formed on the emitter region, to expose the n type InGaP emitter ledge layer 15 (step A). In this case, selective etching of GaAs and InGaP is used. Next, the n type InGaP emitter ledge layer 15, the p type GaAs base layer 16, and the n type GaAs collector layer 17 are etched to expose the n+ type GaAs sub-collector layer 18 (step B). The step B is a step of forming the base mesa layer. The smaller the base mesa width W1, the smaller the base-collector capacitance, i.e., the more excellent the radio frequency characteristics. Steps A and B are the same as those of FIG. 7.
After a base mesa is formed, the base electrode 82 made of Pt/Ti/Pt/Au is formed on n type InGaP emitter ledge layer 15 using deposition lift-off (step F). Thereafter, the collector electrode 13 made of AuGeNi/Au is formed using deposition lift-off, followed by heating at about 400° C. into an alloy to form the collector electrode 13 (step G). The heating at about 400° C. not only allows the collector electrode 13 to change into an alloy, but also causes Pt in the lowermost layer of the Pt/Ti/Pt/Au base electrode 82 on the n type InGaP emitter ledge layer 15 to be thermally diffused into the n type InGaP emitter ledge layer 15 (since Pt has a high thermal diffusion coefficient), to contact the p type GaAs base layer 16, resulting in an ohmic connection.
In this structure, the improvement of radio frequency performance does not require a high-performance fabrication method for forming the high-precision narrow emitter ledge opening width W2 in the narrow emitter mesa interval W4, resulting in low cost. In addition, since W1>W4>W3 is required, the emitter mesa interval W4 can be caused to be narrower for the same base width W3, and as a result, the base mesa width W1 can be narrowed. Thereby, the base-collector capacitance can be further reduced, thereby making it possible to improve performance in a radio frequency band.
(Configuration of Power Amplifier)
Next, a power amplifier employing the bipolar transistor of the embodiment of the present invention will be described.
FIG. 9A is a diagram illustrating an exemplary configuration of a power amplifier in which a plurality of the bipolar transistors of the embodiment of the present invention of FIG. 1B are connected in parallel. FIG. 9B is an equivalent circuit diagram illustrating the power amplifier of FIG. 9A. In the exemplary configuration of the power amplifier of FIGS. 9A and 9B, four bipolar transistors are connected in parallel.
The power amplifier is composed of a plurality of bipolar transistors Q, a capacitance C, and a resistance R. The base electrodes of the plurality of bipolar transistors Q are connected in common via the capacitance C to a radio frequency signal input (RF input) terminal and via the resistance R to a bias supply (DC input) terminal. The capacitance C is a capacitance for passing a radio frequency signal. The resistance R is a suppression resistance for preventing an excessive amount of base current from flowing. The emitter electrodes of the plurality of bipolar transistors Q are grounded via a common conductor and a via hole. The collector electrodes of the plurality of bipolar transistors Q are connected in common to a radio frequency signal output (RF output) terminal.
Since the power amplifier has the structure in which a plurality of the bipolar transistors of FIG. 1B are connected in parallel, the base-collector capacitance is small, so that the gain and the efficiency are improved, resulting in satisfactory radio frequency characteristics. In addition, the breakdown withstanding property is high, so that a base ballast resistance for preventing thermal runaway is no longer required. In this case, therefore, when a power-amplification HBT in which a bipolar transistor is considered as one cell and a plurality of cells are connected in parallel is configured, the area of the configuration can be reduced by an amount corresponding to the external base resistance (base ballast resistance) 130 which is required for the conventional configuration (FIG. 11A, etc.).
As described above, according to the bipolar transistor of the embodiment of the present invention, there is an excellent uniform operation in a cell, and the base-collector capacitance can be reduced, thereby obtaining excellent radio frequency characteristics with low cost. In the case of a multi-cell power amplifier, a power amplifier having a small size (without an external base resistance) and an excellent breakdown withstanding property, can be achieved.
While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.

Claims (1)

1. A heterojunction bipolar transistor which is formed on a semiconductor substrate and has an emitter layer which is in a heterojunction with a base layer, the heterojunction bipolar transistor comprising:
a base electrode;
two emitter electrodes disposed sandwiching the base electrode;
two emitter semiconductor layers disposed under the two emitter electrodes, respectively; and
two collector electrodes disposed sandwiching the base electrode and the two emitter semiconductor layers,
wherein the base electrode is incompletely surrounded by the two emitter semiconductor layers,
wherein a wire of the base electrode is led from a portion of the base electrode which is not surrounded by the two emitter semiconductor layers without passing on or above the two emitter semiconductor layers.
US11/484,753 2005-07-13 2006-07-12 Bipolar transistor and power amplifier Active 2026-08-16 US7566920B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2005204606A JP2007027269A (en) 2005-07-13 2005-07-13 Bipolar transistor and power amplifier
JP2005-204606 2005-07-13
JP2005221213A JP2007036138A (en) 2005-07-29 2005-07-29 Bipolar transistor and power amplifier
JP2005-221213 2005-07-29

Publications (2)

Publication Number Publication Date
US20070012949A1 US20070012949A1 (en) 2007-01-18
US7566920B2 true US7566920B2 (en) 2009-07-28

Family

ID=37660890

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/484,753 Active 2026-08-16 US7566920B2 (en) 2005-07-13 2006-07-12 Bipolar transistor and power amplifier

Country Status (1)

Country Link
US (1) US7566920B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200006536A1 (en) * 2014-11-27 2020-01-02 Murata Manufacturing Co., Ltd. Compound semiconductor device
US20210367066A1 (en) * 2014-11-27 2021-11-25 Murata Manufacturing Co., Ltd. Compound semiconductor device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4849029B2 (en) * 2007-07-23 2011-12-28 三菱電機株式会社 Power amplifier
US9847407B2 (en) 2011-11-16 2017-12-19 Skyworks Solutions, Inc. Devices and methods related to a gallium arsenide Schottky diode having low turn-on voltage
US9461153B2 (en) 2011-11-16 2016-10-04 Skyworks Solutions, Inc. Devices and methods related to a barrier for metallization of a gallium based semiconductor
US8928411B2 (en) * 2012-12-31 2015-01-06 Silicon Image, Inc. Integration of signal sampling within transistor amplifier stage
US20160020307A1 (en) 2014-07-16 2016-01-21 Win Semiconductors Corp. Heterojunction Bipolar Transistor
TWI577014B (en) * 2014-07-16 2017-04-01 穩懋半導體股份有限公司 Heterojunction bipolar transistor
US20190181251A1 (en) * 2017-12-07 2019-06-13 Qualcomm Incorporated Mesh structure for heterojunction bipolar transistors for rf applications
US10622465B2 (en) 2017-12-20 2020-04-14 Qualcomm Incorporated Heterojunction bipolar transistor (HBT)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151009A (en) * 1978-01-13 1979-04-24 Bell Telephone Laboratories, Incorporated Fabrication of high speed transistors by compensation implant near collector-base junction
US5036016A (en) * 1989-02-21 1991-07-30 Bipolar Integrated Technology, Inc. VLSI bipolar transistor process
JPH06342803A (en) 1992-05-29 1994-12-13 Texas Instr Inc <Ti> Transistor
JPH07202168A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Semiconductor device and manufacture thereof
US5608353A (en) 1995-03-29 1997-03-04 Rf Micro Devices, Inc. HBT power amplifier
JP2001196865A (en) 1999-10-29 2001-07-19 Hitachi Ltd Wireless communication apparatus and semiconductor device
US20010010388A1 (en) * 1999-12-28 2001-08-02 Manabu Yanagihara Bipolar transistor and method of fabricating the same
CN1318898A (en) 2000-03-28 2001-10-24 株式会社东芝 High-frequency power amplifier with bipolar transistor
JP2002110904A (en) 2000-09-29 2002-04-12 Sharp Corp Semiconductor device
US20050116319A1 (en) * 2003-11-28 2005-06-02 Sharp Kabushiki Kaisha Bipolar transistor

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151009A (en) * 1978-01-13 1979-04-24 Bell Telephone Laboratories, Incorporated Fabrication of high speed transistors by compensation implant near collector-base junction
US5036016A (en) * 1989-02-21 1991-07-30 Bipolar Integrated Technology, Inc. VLSI bipolar transistor process
JPH06342803A (en) 1992-05-29 1994-12-13 Texas Instr Inc <Ti> Transistor
JPH07202168A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Semiconductor device and manufacture thereof
US5608353A (en) 1995-03-29 1997-03-04 Rf Micro Devices, Inc. HBT power amplifier
US5629648A (en) 1995-03-29 1997-05-13 Rf Micro Devices, Inc. HBT power amplifier
JP2001196865A (en) 1999-10-29 2001-07-19 Hitachi Ltd Wireless communication apparatus and semiconductor device
US20010010388A1 (en) * 1999-12-28 2001-08-02 Manabu Yanagihara Bipolar transistor and method of fabricating the same
CN1318898A (en) 2000-03-28 2001-10-24 株式会社东芝 High-frequency power amplifier with bipolar transistor
US20010052820A1 (en) 2000-03-28 2001-12-20 Kabushiki Kaisha Toshiba High frequency power amplifier having a bipolar transistor
US6448859B2 (en) * 2000-03-28 2002-09-10 Kabushiki Kaisha Toshiba High frequency power amplifier having a bipolar transistor
JP2002110904A (en) 2000-09-29 2002-04-12 Sharp Corp Semiconductor device
US20050116319A1 (en) * 2003-11-28 2005-06-02 Sharp Kabushiki Kaisha Bipolar transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Chinese Office Action issued in Chinese Patent Application No. CN 2006101015669, dated Mar. 13, 2009.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200006536A1 (en) * 2014-11-27 2020-01-02 Murata Manufacturing Co., Ltd. Compound semiconductor device
US10868155B2 (en) * 2014-11-27 2020-12-15 Murata Manufacturing Co., Ltd. Compound semiconductor device
US20210367066A1 (en) * 2014-11-27 2021-11-25 Murata Manufacturing Co., Ltd. Compound semiconductor device
US11508834B2 (en) 2014-11-27 2022-11-22 Murata Manufacturing Co., Ltd. Compound semiconductor device
US11869957B2 (en) * 2014-11-27 2024-01-09 Murata Manufacturing Co., Ltd. Compound semiconductor device

Also Published As

Publication number Publication date
US20070012949A1 (en) 2007-01-18

Similar Documents

Publication Publication Date Title
US7566920B2 (en) Bipolar transistor and power amplifier
JP4977313B2 (en) Heterojunction bipolar transistor
US20060157825A1 (en) Semiconductor device and manufacturing the same
US6403991B1 (en) Semiconductor device and method for fabricating the same
US20060108665A1 (en) Semiconductor device, manufacturing method of the same, and electronic device
US10236237B2 (en) Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method
US10297680B2 (en) Bipolar transistor and method for producing the same
JP2007027269A (en) Bipolar transistor and power amplifier
TW201911525A (en) Semiconductor device
US20060138459A1 (en) Semiconductor device, manufacturing method of the same and electronic device
US6577200B2 (en) High-frequency semiconductor device
JP2007036138A (en) Bipolar transistor and power amplifier
US6593604B2 (en) Heterojunction bipolar transistor, manufacturing method therefor, and communication device therewith
CN111223921B (en) bipolar transistor
JP5543936B2 (en) Method of manufacturing heterojunction bipolar transistor and power amplifier using heterojunction bipolar transistor
JP4494739B2 (en) Bipolar transistor and manufacturing method thereof
JP3719985B2 (en) Heterojunction bipolar transistor
JP2005159112A (en) Semiconductor device and manufacturing method thereof
JP2005101402A (en) Semiconductor device and method for manufacturing same
JP2006278541A (en) Compound semiconductor device and its fabrication process
KR20020031722A (en) Structure and method for heterojunction bipola transistor
JP2005101134A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWASHIMA, KATSUHIKO;MAEDA, MASAHIRO;MURAYAMA, KEIICHI;AND OTHERS;REEL/FRAME:018666/0561;SIGNING DATES FROM 20060620 TO 20060626

AS Assignment

Owner name: PANASONIC CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:021897/0671

Effective date: 20081001

Owner name: PANASONIC CORPORATION,JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:021897/0671

Effective date: 20081001

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PANASONIC CORPORATION;REEL/FRAME:052755/0917

Effective date: 20200521

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12