JP5543936B2 - Method of manufacturing heterojunction bipolar transistor and power amplifier using heterojunction bipolar transistor - Google Patents

Description

  The present invention relates to a heterojunction bipolar transistor having high reliability, a method for manufacturing the same, and a power amplifier using the same.

  In recent years, with rapid growth in demand for mobile communication devices, research and development of power amplifiers used in communication devices has been actively conducted. As semiconductor transistors used for power amplifiers for mobile communication devices, heterojunction bipolar transistors (hereinafter abbreviated as HBT (Heterojunction Bipolar Transistor)), field effect transistors (hereinafter abbreviated as FET), SiMOS (Metal-Oxide-). Semiconductor) FETs are available. Among them, the HBT has excellent linearity of input / output characteristics, operates only with a positive power supply, does not require a negative power supply generation circuit / part, has a high output power density, and requires a small chip area. It has features such as space saving and low cost. For this reason, it is mainly used as a transistor for power amplifiers for mobile communication devices.

  However, in the HBT, there is an unstable operation phenomenon caused by heat called thermal runaway, so a stabilization resistor called a so-called ballast resistor is used to stabilize the operation. As a means for realizing this, a technique using an AlGaAs ballast resistor layer on an InGaP emitter layer is shown in republished patent WO 98/53502, Table 1 (Patent Document 1).

WO98 / 53502 (Table 1)

  In the conventional technology, for example, the technology as disclosed in the above-mentioned WO 98/53502 has a difficulty in reliability of energization of the device. That is, in the HBT having the AlGaAs ballast resistor layer, the characteristic deterioration during energization is remarkable. On the other hand, when such a ballast layer is not used, of course, the phenomenon of unstable operation due to heat occurs as described above.

  In view of such a background, a first object of the present invention is to provide an HBT having both thermal stability and reliability against energization in an HBT having InGaP as an emitter layer. A second object of the present invention is to provide a method for manufacturing an HBT that can achieve both thermal stability and reliability against energization in an HBT having InGaP as an emitter layer. Furthermore, a third object of the present invention is to provide a power amplifier using an HBT having InGaP as an emitter layer and capable of satisfying both thermal stability and reliability for energization.

  The first object of the present invention is to insert a GaAs layer between an InGaP emitter layer and an AlGaAs ballast resistor layer in an HBT having InGaP as an emitter layer, and diffused holes reversely injected from the base layer to the AlGaAs ballast resistor layer. , Achieved by suppressing reaching. More specifically, the thickness of the GaAs layer inserted between the InGaP emitter layer and the AlGaAs ballast resistor layer is such that the depletion layer formed between the emitter and the base under the actual operating conditions of the HBT does not reach the AlGaAs ballast resistor layer. Set to. In other words, this is achieved by setting the thickness of the GaAs layer inserted between the InGaP emitter layer and the AlGaAs ballast resistor layer to be larger than the width of the depletion layer formed between the emitter and the base under the actual operating conditions of the HBT.

  In the present invention, an InGaAsP is preferable as an emitter for a GaAs-based HBT, and an AlGaAs ballast resistance layer is preferable for obtaining ballast characteristics, while using a GaAs layer as a buffer layer. As described above, it is possible to obtain an HBT satisfying both sides of the thermal stability of the HBT characteristic and the reliability against energization.

The specific thickness of the GaAs layer varies depending on conditions such as the emitter / base voltage and the donor concentration of the GaAs layer when the HBT is actually operated, but the emitter / base voltage is 1.2 V or more. A range of about 2 nm to about 500 nm is used. The donor concentration is in the range of about 5 × 10 ¹⁶ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ . The actual operating condition of an HBT having an InGaP emitter layer and a GaAs base layer is generally an emitter / base voltage of 1.2 V or more. The total of the GaAs layer thickness and the InGaP emitter layer under the actual operating conditions of the HBT is, for example, that the donor concentration in the GaAs layer is 5 × 10 ¹⁶ cm ⁻³ , 5 × 10 ¹⁷ cm ⁻³ , 5 × 10 ¹⁸ cm ^{−. In} case of ³ , 70 nm, 27 nm and 20 nm are sufficient, respectively.

  The second object of the present invention is achieved by sequentially forming the emitter electrode, the emitter mesa, the base electrode, the base mesa, and the collector electrode. A more specific example of the process is as follows.

  A step of sequentially laminating at least a collector semiconductor layer, a base semiconductor layer, an InGaP emitter semiconductor layer, a GaAs semiconductor layer, and an AlGaAs ballast resistor semiconductor layer on the semi-insulating substrate, the AlGaAs ballast resistor semiconductor; A step of forming an emitter electrode of a desired shape above the layer, a step of forming an emitter region by processing the AlGaAs ballast resistor semiconductor layer and the GaAs semiconductor layer into a mesa shape, the InGaP emitter semiconductor layer, and a base semiconductor layer Forming a base region by processing the substrate into a mesa shape, forming a base electrode in the base region, forming a collector region by processing the collector semiconductor layer into a mesa shape, and collecting a collector electrode in the collector region Forming a step.

  A third object of the present invention is to provide a power amplifier having an amplifier circuit formed by connecting at least one basic HBT in parallel and connected in multiple stages, and has an AlGaAs ballast resistor layer on the top of the InGaP emitter layer as the basic HBT. In addition, a GaAs semiconductor layer is inserted between the InGaP emitter layer and the AlGaAs ballast resistor layer, and the thickness of the GaAs layer is set to be larger than the width of the depletion layer formed between the emitter and the base under the actual operating conditions of the HBT. This is achieved by using the HBT.

  According to the present invention, it is possible to provide an HBT that achieves both thermal stability and reliability against energization. According to another aspect of the present invention, it is possible to provide a method for manufacturing an HBT that achieves both thermal stability and reliability against energization. Furthermore, according to the present invention, it is possible to provide a power amplifier that achieves both thermal stability and reliability against energization.

FIG. 1 is a plan view showing an example of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 3A is a plan view showing an example of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 3B is a cross-sectional view showing an example of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 4A is a cross-sectional view of an apparatus showing a bipolar transistor manufacturing method according to an embodiment of the present invention in the order of steps. FIG. 4B is a cross-sectional view of the device illustrating the bipolar transistor manufacturing method according to the embodiment of the present invention in the order of steps. FIG. 4C is a cross-sectional view of an apparatus showing a method of manufacturing a bipolar transistor according to one embodiment of the present invention in the order of steps. FIG. 5A is a cross-sectional view of an apparatus showing, in the order of steps, steps subsequent to FIG. 4C of the method for manufacturing a bipolar transistor according to one embodiment of the present invention. FIG. 5B is a cross-sectional view of an apparatus showing a bipolar transistor manufacturing method according to an embodiment of the present invention in the order of steps. It is sectional drawing of the apparatus which shows the process following C to process order. FIG. 5C is a cross-sectional view of an apparatus showing a bipolar transistor manufacturing method according to an embodiment of the present invention in the order of steps. FIG. 6A is a cross-sectional view of the device illustrating the process subsequent to FIG. 5C in the bipolar transistor manufacturing method according to the embodiment of the present invention in the order of steps. FIG. 6B is a cross-sectional view of the device illustrating the bipolar transistor manufacturing method according to the embodiment of the present invention in the order of steps. It is sectional drawing of the apparatus which shows the process following C to process order. FIG. 6C is a cross-sectional view of an apparatus illustrating a bipolar transistor manufacturing method according to an embodiment of the present invention in the order of steps. FIG. 7 is a circuit diagram showing an example of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 8A is a plan view showing an example of a protection circuit device used in a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 8B is a cross-sectional view showing an example of a protection circuit device used in the heterojunction bipolar transistor according to one embodiment of the present invention. FIG. 9A is a plan view showing an example of a protection circuit device used in a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 9B is a plan view showing an example of a protection circuit device used in the heterojunction bipolar transistor according to one embodiment of the present invention. FIG. 10A is a plan view showing an example of a protection circuit device used in a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 10B is a cross-sectional view showing an example of a protection circuit device used in the heterojunction bipolar transistor according to one embodiment of the present invention. FIG. 11 is a block diagram showing a power amplifier according to an embodiment of the present invention. FIG. 12 is a cross-sectional view illustrating a typical power amplifier module implementation. FIG. 13 is a plan view showing a typical power amplifier module implementation. FIG. 14 is a circuit diagram illustrating an example of a first amplifier circuit of a power amplifier according to an embodiment of the present invention. FIG. 15 is a circuit diagram showing an example of a second amplifier circuit of the power amplifier according to the embodiment of the present invention. FIG. 16 is a circuit diagram showing an example of a heterojunction bipolar transistor used in a power amplifier according to an embodiment of the present invention. FIG. 17 is a characteristic diagram showing the nondestructive operation region limit of the heterojunction bipolar transistor in DC operation. FIG. 18 is a cross-sectional view of an HBT having an AlGaAs ballast resistor layer for comparison characteristics examination. FIG. 18 is a cross-sectional view of an HBT that does not have an AlGaAs ballast resistor layer for comparison characteristics examination. FIG. 20A is a cross-sectional view of an apparatus in a bipolar transistor manufacturing method according to an embodiment of the present invention. FIG. 20B is a cross-sectional view of the apparatus in the bipolar transistor manufacturing method according to the embodiment of the present invention.

  Hereinafter, a heterojunction bipolar transistor, a manufacturing method thereof, and a power amplifier using the same will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, the same reference numerals are given to the same functions, and the repeated explanation thereof is omitted.

<Embodiment 1> An HBT according to a first embodiment of the present invention will be described with reference to the drawings. The present embodiment explains the basic principle of the present invention, and each component has a schematic shape. FIG. 1 is a plan view of the HBT of the present invention, and FIG. 2 is a cross-sectional view along AA ′ in FIG. The emitter area is 108 μm ² .

  In the present invention, the other main components of the emitter layer, the GaAs layer, and the ballast resistor layer described so far are sufficient to use general ones. For example, a semi-insulating semiconductor substrate such as a GaAs substrate, a GaAs layer as a base layer, and a GaAs layer as a collector layer are generally used as a substrate.

An n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm) 2 is formed on the semi-insulating GaAs substrate 1. An n-type GaAs collector layer (Si concentration 1 × 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm) 3, a p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³⁾ , and a film are formed on the subcollector layer 2. 150 nm) 4 and n-type InGaP emitter layers (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 30 nm) 5 are formed. A base electrode 12 is disposed via the emitter layer 5.

On the other hand, the emitter layer 5 includes an n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm) 6, an n-type AlGaAs ballast resistor layer (AlAs molar ratio 0.33, Si concentration 1 × 10 ¹⁷ cm). ^-3 , film thickness 120 nm) 7, n-type GaAs contact layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ , film thickness 50 nm) 8, n-type InGaAs contact layer (InAs molar ratio 0.5, Si concentration 1 × 10 ¹⁹⁾ cm ⁻³ , film thickness 50 nm) 9 is further provided. An emitter electrode 13 is provided on the contact layer 9. On the other hand, a collector electrode 11 is formed on the subcollector layer 2 so as to face both side portions of the collector layer 3. As seen in FIG. 1, the planar configuration is such that the collector region surrounds the emitter region.

  Specific examples of the collector electrode 11, the base electrode 12, and the emitter electrode 13 are shown as follows: collector electrode 11 formed by stacking AuGe (film thickness 60 nm) / Ni (film thickness 10 nm) / Au (film thickness 200 nm). A base electrode 12 and a WSi (Si molar ratio 0.3, film thickness 0.3 μm) emitter electrode 13 formed by stacking Ti (film thickness 50 nm) / Pt (film thickness 50 nm) / Au (film thickness 200 nm). Further, reference numerals 14, 15, and 16 in FIG. 1 are collector wiring, base wiring, and emitter wiring, respectively, and reference numerals 17, 18, and 19 are metal pads for electrical connection with the outside of the HBT.

  The AlGaAs ballast resistor layer needs to operate as a resistor, and the thickness thereof needs to be 10 nm or more so as not to exhibit a quantum mechanical tunnel effect. The thickness of the AlGaAs ballast resistor layer does not exhibit a quantum mechanical tunnel effect, and is determined according to a request for characteristics as a resistor. The value can be about 200 nm. The n-type GaAs layer 6 serves as a so-called spacer layer between the emitter layer 5 and the n-type AlGaAs ballast resistor layer. In this embodiment, the AlAs molar ratio of the AlGaAs ballast resistor layer is 0.33. However, it may be zero or more.

When 20 HBTs shown in this example were subjected to a current-carrying test for 300 hours under the conditions of a collector current density of 40 kA / cm ² and a junction temperature of 210 ° C., there was no deteriorated HBT and reliability for good current-carrying was confirmed.

  Further, FIG. 17 shows the nondestructive operation region limit in the direct current operation, which is one index of the thermal stability of the HBT shown in this embodiment. In FIG. 17, the vertical axis represents the nondestructive collector current, and the horizontal axis represents the nondestructive collector voltage. For comparison, the results for an HBT without an AlGaAs ballast resistor layer are also shown. From this result, it was confirmed that the HBT having the AlGaAs ballast resistance shown in this example was superior in fracture resistance, that is, excellent in thermal stability, compared to the HBT without the AlGaAs ballast resistance layer. .

  From the above results, it was confirmed that the HBT shown in the present example was an HBT capable of achieving both thermal stability and reliability against energization.

<Example 2>
An HBT according to a second embodiment of the present invention will be described with reference to the drawings. The present embodiment explains the basic principle of the present invention, and each component has a schematic shape. FIG. 3A shows a planar structure of the HBT of the present invention, and FIG. 3B shows a cross-sectional structure along BB ′ in FIG. 3A. This example is an example of a high power multi-finger HBT configured by connecting basic HBTs in parallel. The emitter area of the basic HBT is 108 μm ² .

An n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm) 2 is formed on the semi-insulating GaAs substrate 1. An n-type GaAs collector layer (Si concentration 1 × 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm) 3, a p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³⁾ , and a film are formed on the subcollector layer 2. 150 nm) 4 and n-type InGaP emitter layers (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 30 nm) 5 are formed. A base electrode 12 is disposed via the emitter layer 5.

On the other hand, the emitter layer 5 includes an n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm) 6, an n-type AlGaAs ballast resistor layer (AlAs molar ratio 0.33, Si concentration 1 × 10 ¹⁷ cm). ^-3 , film thickness 120 nm) 7, n-type GaAs contact layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ , film thickness 50 nm) 8, n-type InGaAs contact layer (InAs molar ratio 0.5, Si concentration 1 × 10 ¹⁹⁾ cm ⁻³ , film thickness 50 nm) 9 is further provided. An emitter electrode 13 is provided on the contact layer 9. On the other hand, a collector electrode 11 is formed on the subcollector layer 2 so as to face both side portions of the collector layer 3.

  Specific examples of the collector electrode 11, the base electrode 12, and the emitter electrode 13 are shown as follows: collector electrode 11 formed by stacking AuGe (film thickness 60 nm) / Ni (film thickness 10 nm) / Au (film thickness 200 nm). A base electrode 12 and a WSi (Si molar ratio 0.3, film thickness 0.3 μm) emitter electrode 13 formed by stacking Ti (film thickness 50 nm) / Pt (film thickness 50 nm) / Au (film thickness 200 nm). Further, reference numerals 14, 15, and 16 in FIG. 1 are collector wiring, base wiring, and emitter wiring, respectively, and reference numerals 17, 18, and 19 are metal pads for electrical connection with the outside of the HBT.

  Since this example is a high-power multi-finger HBT, basic HBTs 70, 71, and 72 are exemplified. The basic HBTs 70, 71, and 72 are connected in parallel, and the emitter electrode 13 is commonly connected to the metal pad 17 for electrical connection with the outside of the HBT. The basic HBT itself is the same as that shown in the first embodiment.

  The AlGaAs resistance layer needs to operate as a resistor, and the thickness thereof needs to be 10 nm or more so as not to exhibit a quantum mechanical tunnel effect. In this embodiment, the AlAs molar ratio of the AlGaAs ballast resistor layer is 0.33. However, it may be zero or more.

  <Embodiment 3> Using this example, a typical method for manufacturing an HBT will be described with reference to the drawings. The present embodiment explains the basic principle of the present invention, and each component has a schematic shape. 4A to 6C are cross-sectional views of an apparatus for explaining the method of manufacturing the HBT of the present invention according to the manufacturing process. This example is an example of a high power multi-finger HBT configured by connecting basic HBTs in parallel.

On the semi-insulating GaAs substrate 1, an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm) 2, an n-type GaAs collector layer (Si concentration 1 × 10 ¹⁶ cm ⁻³⁾ , 1.0 μm thick) 3, p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , 150 nm thick) 4, n-type InGaP emitter layer (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³⁾ , Film thickness 30 nm) 5, n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm) 6, n-type AlGaAs ballast resistor layer (AlAs molar ratio 0.33, Si concentration 1 × 10 ¹ cm ^{− 3,} film thickness 120 nm) 7, n-type GaAs contact layer (Si concentration 1 × ¹⁰ 19 ^{cm -3,} thickness 50 nm) 8, n-type InGaAs contact layer (InAs molar ratio 0.5, Si concentration 1 × 10 ⁹ cm ^-3, film thickness 50 nm) 9, is grown by metal organic vapor phase epitaxy (Figure 4A).

Thereafter, WSi (Si molar ratio 0.3, film thickness 0.3 μm) 13 is deposited on the entire surface of the wafer by using a high frequency sputtering method (FIG. 4B). The WSi layer 13 is processed by photolithography and dry etching using CF ₄ to form the emitter electrode 13 (FIG. 4C).

  Thereafter, the n-type InGaAs contact layer 9, the n-type GaAs contact layer 8, the n-type AlGaAs ballast resistor layer 7, and the n-type GaAs layer 6 are processed into desired shapes to form an emitter region (FIG. 5A). Examples of processing methods are as follows. The n-type InGaAs contact layer 9, the n-type GaAs contact layer 8, and the n-type are formed by wet etching using photolithography and an etching solution (a composition example of the etching solution, phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40). Unnecessary regions of the AlGaAs ballast resistor layer 7 and the n-type GaAs layer 6 are removed.

  Thereafter, a Ti (thickness 50 nm) / Pt (thickness 50 nm) / Au (thickness 200 nm) base electrode 12 is formed on the base layer 4 through the emitter layer 5 using a conventional lift-off method ( FIG. 5B).

  Thereafter, the desired regions of the n-type InGaP emitter layer 5, the p-type GaAs base layer 4, and the n-type GaAs collector layer 3 are removed by photolithography and wet etching to expose the n-type GaAs subcollector layer 2. A base region is formed (FIG. 5C). The etching solution is as follows. Hydrochloric acid is used as an etchant when the n-type InGaP emitter layer 5 is etched, and the composition of the etchant when etching the p-type GaAs base layer 4 and the n-type GaAs collector layer 3 is phosphoric acid: hydrogen peroxide. Water: water = 1: 2: 40.

  Thereafter, the collector electrode 11 is formed by a usual lift-off method and alloyed at 350 ° C. for 30 minutes (FIG. 6A). The collector electrode 11 is a laminate of AuGe (film thickness 60 nm) / Ni (film thickness 10 nm) / Au (film thickness 200 nm).

  Finally, an isolation groove 10 is formed (FIG. 6B). Further, a wiring for connecting the emitter electrodes between the basic HBTs, the base electrodes, and the collector electrodes is formed (FIG. 6C). Thus, the HBT is completed.

  The step of determining the emitter area is a step of removing the n-type InGaAs contact layer 9, the n-type GaAs contact layer 8, the n-type AlGaAs ballast resistor layer 7, and the n-type GaAs layer 6 by photolithography and wet etching in FIG. 5A. . In this embodiment, the case of phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40 is described as the wet etching solution. However, as the other etching solution, phosphoric acid: hydrogen peroxide solution: ethylene glycol = 25. : 6: 50, hydrofluoric acid: hydrogen peroxide solution: water = 1: 2: 4, etc. may be used. In this case, since the etching shape varies depending on the etching solution used, it is necessary to adjust the photomask dimension and wet etching time in order to produce the emitter area as designed. 20A and 20B show detailed cross-sectional shapes on the (00-1) crystal plane. FIG. 20A shows an example in which phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40 is used as the wet etching solution, and constriction is seen in the mesa shape. On the other hand, FIG. 20B shows an example in which phosphoric acid: hydrogen peroxide solution: ethylene glycol = 25: 6: 50 or hydrofluoric acid: hydrogen peroxide solution: water = 1: 2: 4 is used as the wet etching solution. It is. In this example, a mesa-shaped structure with no constriction can be obtained, so that it is difficult to be affected by stress such as stress. Therefore, it is possible to further improve the reliability as compared with the HBT shown in FIG. 20A.

  According to the manufacturing method of this example, it is possible to manufacture an HBT that can achieve both the thermal stability of the HBT characteristics and the reliability against energization.

<Example 4>
FIG. 7 shows an equivalent circuit diagram of an example of the HBT of the present invention. In this example, an electrostatic breakdown preventing circuit 22 is connected in parallel to an HBT 21 in which a plurality of unit HBTs are connected in parallel. The present embodiment explains the basic principle of the present invention, and each component has a schematic shape.

The unit HBT constituting the HBT 21 is sufficient to use the HBT exemplified in the above-described embodiment. That is, the unit HBT includes at least a semi-insulating GaAs substrate, an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm), and an n-type GaAs collector layer (Si concentration 1 × 10). ¹⁶ cm ⁻³ , film thickness 1.0 μm), p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , film thickness 150 nm), n-type InGaP emitter layer (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷⁾ cm ⁻³ , film thickness 30 nm), n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm), n-type AlGaAs ballast resistor layer (AlAs molar ratio 0.33, Si concentration 1 × 10 ¹⁷ cm) ^-3, film thickness 120 nm), n-type GaAs contact layer (Si concentration 1 × ¹⁰ 19 ^{cm -3,} thickness 50 nm), n-type InGaAs contact layer (InAs molar ratio 0.5 Si concentration 1 × ¹⁰ 19 ^{cm -3,} a HBT provided with the film thickness 50 nm). As illustrated in the HBT 21 in FIG. 7, the base, emitter, and collector of each unit HBT are connected to each other and connected in parallel.

  The circuit denoted by reference numeral 22 is a protection circuit for preventing the HBT 21 from being destroyed when an excessive voltage such as static electricity is applied to the HBT 21, and is formed by connecting a plurality of diodes in series, and the collector and emitter of the HBT 21. Connected in parallel. The protection circuit 22 is formed on the same semi-insulating GaAs substrate as the HBT 21.

The planar structure of the protection circuit 22 is shown in FIG. 8A, and the cross-sectional structure along CC ′ of FIG. 8A is shown in FIG. 8B. In the present embodiment, a pn junction between the base and the collector of the HBT 21 is used as a diode. Here, reference numerals 1, 2, 3, 4, and 5 denote a semi-insulating GaAs substrate, an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm), and an n-type GaAs collector layer, respectively. (Si concentration 1 × 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm), p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , film thickness 150 nm), n-type InGa emitter layer (InP molar ratio 0. 5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 30 nm). Reference numerals 11, 12, 16, and 18 are collector electrodes formed by stacking AuGe (film thickness 60 nm) / Ni (film thickness 10 nm) / Au (film thickness 200 nm), Ti (film thickness 50 nm) / Pt (film), respectively. A base electrode formed by stacking 50 nm) / Au (thickness 200 nm), a wiring for connecting each diode in series, and a metal pad for electrical connection with the HBT 21. Further, reference numeral 10 denotes an isolation groove for electrically separating each diode. Although the case where the HBT 21 and the protection circuit 22 are connected by a bonding wire is shown in the present embodiment, they may be directly electrically connected via the wiring 16.

  In the present embodiment, the diode constituting the protection circuit 22 is electrically turned on at about 1.2 V per stage. Therefore, for example, when the protection circuit 22 in which 10 stages of diodes are connected in series is used, the protection circuit 22 is turned on when a voltage of 12 V is applied between the collector and the emitter of the HBT 21 to prevent the HBT 21 from being destroyed.

In the above-described embodiment, the diode constituting the protection circuit 22 is a diode using the pn junction between the base and the collector of the HBT 21. However, a pn junction between the base and the emitter may be used. FIG. 9A shows a planar structure of the protection circuit 22 in that case, and FIG. 9B shows a cross-sectional structure along DD ′ of FIG. 9A. Here, reference numerals 1, 2, 3, 4, 5, 6, 7, 8, and 9 respectively denote a semi-insulating GaAs substrate, an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0). .6 μm), n-type GaAs collector layer (Si concentration 1 × 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm), p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , film thickness 150 nm), n-type InGaP emitter layer (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 30 nm), n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm), n-type AlGaAs ballast Resistance layer (AlAs molar ratio 0.33, Si concentration 1 × 10 ¹⁷ cm ⁻³ , film thickness 120 nm), n-type GaAs contact layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ , film thickness 50 nm), n-type InGaAs contact layer (InAs molar ratio 0.5, Si concentration 1 × 10 ¹⁹ cm ⁻³ , film thickness 50 nm). Reference numerals 12, 13, 16, and 18 are base electrodes formed by laminating Ti (film thickness 50 nm) / Pt (film thickness 50 nm) / Au (film thickness 200 nm), WSi (Si molar ratio 0.3, film) Thickness 0.3 μm) Emitter electrode, wiring for connecting each diode in series, and metal pad for electrical connection with HBT 21. Further, reference numeral 10 denotes an isolation groove for electrically separating each diode. Although the case where the HBT 21 and the protection circuit 22 are connected by a bonding wire is shown in the present embodiment, they may be directly electrically connected via the wiring 16.

  In the present embodiment, the diode constituting the protection circuit 22 is electrically turned on at about 1.2 V per stage. Therefore, for example, when the protection circuit 22 in which 10 stages of diodes are connected in series is used, the protection circuit 22 is turned on when a voltage of 12 V is applied between the collector and the emitter of the HBT 21 to prevent the HBT 21 from being destroyed.

Furthermore, a plan view of another embodiment of the protection circuit 22 is shown in FIG. 10A, and a cross-sectional structure along EE ′ in FIG. 10A is shown in FIG. 10B. Here, reference numerals 1, 2, 3, 4, 5, 6, 7, 8, and 9 respectively denote a semi-insulating GaAs substrate, an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0). .6 μm), n-type GaAs collector layer (Si concentration 1 × 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm), p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , film thickness 150 nm), n-type InGaP emitter layer (InP molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 30 nm), n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm), n-type AlGaAs ballast resistor layer (AlAs mole ratio 0.33, Si concentration 1 × ¹⁰ 17 ^{cm -3,} film thickness 120 nm), n-type GaAs contact layer (Si concentration 1 × ¹⁰ 19 ^{cm -3,} thickness 50 nm), n-type InGaAs contact (InAs molar ratio 0.5, Si concentration 1 × ¹⁰ 19 ^{cm -3,} thickness 50 nm) is. Reference numerals 12, 13, 16, and 18 are base electrodes formed by laminating Ti (film thickness 50 nm) / Pt (film thickness 50 nm) / Au (film thickness 200 nm), WSi (Si molar ratio 0.3, film) Thickness 0.3 μm) Emitter electrode, wiring for connecting each diode in series, and metal pad for electrical connection with HBT 21. Although the case where the HBT 21 and the protection circuit 22 are connected by a bonding wire is shown in the present embodiment, they may be directly electrically connected via the wiring 16.

<Example 5>
A power amplifier according to a fifth embodiment of the present invention will be described with reference to the drawings. The present embodiment explains the basic principle of the present invention, and each component has a schematic shape. FIG. 11 is a block diagram 23 of the power amplifier showing the present embodiment. This example is a two-stage power amplifier. In the figure, 24 and 25 are a first amplifier circuit and a second amplifier circuit, respectively, and numerals 26a, 26b and 26c are an input matching circuit, an interstage matching circuit and an output matching circuit, respectively. The amplified high frequency signal is input to the power amplifier from the terminal 27, amplified through the matching circuits 26 a, 26 b and 26 c, and the amplifier circuits 24 and 25, and then output from the terminal 28.

  12 and 13 are a cross-sectional view and a plan view, respectively, showing a typical power amplifier module mounting form. The semiconductor element 51 and the passive element 52 are mounted on the mounting substrate 60. Reference numeral 54 denotes a conductor layer, which constitutes an electrical signal connection with the semiconductor element 51. In this example, a plurality of mounting boards 60, 61, and 62 are stacked and used. The semiconductor element 51 is the power amplifier described above.

Circuit diagrams of the first amplifier circuit 24 and the second amplifier circuit 25 are shown in FIGS. 14 and 15, respectively. Each of them is composed of multi-finger HBTs formed by connecting 10 parallel and 60 parallel basic HBTs having an emitter area of 108 μm ² .

Here, the basic HBT has an n-type GaAs subcollector layer (Si concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 0.6 μm), an n-type GaAs collector layer (Si concentration 1 ×) on at least a semi-insulating GaAs substrate. 10 ¹⁶ cm ⁻³ , film thickness 1.0 μm), p-type GaAs base layer (C concentration 4 × 10 ¹⁹ cm ⁻³ , film thickness 150 nm), n-type InGaP emitter layer (InP molar ratio 0.5, Si concentration 3) × 10 ¹⁷ cm ⁻³ , film thickness 30 nm), n-type GaAs layer (Si concentration 3 × 10 ¹⁷ cm ⁻³ , film thickness 90 nm), n-type AlGaAs ballast resistor layer (AlAs molar ratio 0.33, Si concentration 1 ×) 10 ¹⁷ cm ⁻³ , film thickness 120 nm), n-type GaAs contact layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ , film thickness 50 nm), n-type InGaAs contact layer (InAs molar ratio 0. 5, HBT having a Si concentration of 1 × 10 ¹⁹ cm ⁻³ and a film thickness of 50 nm. 14 and 15, the base, emitter, and collector of each unit HBT are connected to each other and connected in parallel.

  The second amplifier circuit 25 may be an amplifier circuit as shown in the circuit diagram of FIG. That is, when an excessive voltage such as static electricity is applied to the HBT 21, a protection circuit for preventing the HBT 21 from being destroyed is connected in parallel between the collector and the emitter of the HBT 21. The protection circuit 22 is formed on the same semi-insulating GaAs substrate as the HBT 21.

  <Characteristic Comparison between Present Invention and Conventional Structure> In order to quantitatively grasp the importance of the reliability of the GaAs layer inserted between the InGaP emitter layer and the AlGaAs ballast resistor layer in the present invention, as shown in FIGS. An HBT having a cross-sectional structure was manufactured and its reliability was compared. FIG. 18 shows a structure simulating the HBT shown in, for example, WO 98/53502, Table 1 (Patent Document 1). On a semi-insulating GaAs substrate 1, an n-type GaAs subcollector layer 2, an n-type GaAs collector layer 3, a p-type GaAs base layer 4, an n-type InGaP emitter layer 5, an n-type AlGaAs ballast resistor layer 7, n It has a layer structure in which a type GaAs contact layer 8 and an n type InGaAs contact layer 9 are sequentially laminated. In FIG. 18, reference numerals 11, 12, and 13 denote a collector electrode, a base electrode, and an emitter electrode, respectively. FIG. 19 shows a structure that does not include an AlGaAs ballast resistor layer fabricated for comparison. On a semi-insulating GaAs substrate 1, an n-type GaAs subcollector layer 2, an n-type GaAs collector layer 3, a p-type GaAs base layer 4, an n-type InGaP emitter layer 5, an n-type GaAs layer 20, and an n-type GaAs. It has a layer structure in which a contact layer 8 and an n-type InGaAs contact layer 9 are sequentially stacked. In FIG. 2b, 11, 12, and 13 are a collector electrode, a base electrode, and an emitter electrode, respectively.

The HBT as shown in FIGS. 18 and 19 was subjected to a current test for 300 hours under the same conditions of a collector current density of 40 kA / cm ² and a junction temperature of 210 ° C., and had an AlGaAs ballast resistance layer directly on the InGaP emitter layer. In the HBT shown in FIG. 18, all 20 HBTs tested were deteriorated. On the other hand, in the comparative HBT that does not include the AlGaAs ballast resistor layer shown in FIG. 19, the energization test was performed on 20 HBTs, but there was no deteriorated HBT.

  The reason why the device life of the HBT having the AlGaAs ballast resistance layer directly on the InGaP emitter layer is short is considered as follows with respect to the result of the reliability comparison. A deep donor impurity level called DX center exists in the AlGaAs layer and acts as a non-radiative recombination center. The positively injected holes from the p-type GaAs base layer to the n-type InGaP emitter layer side reach the AlGaAs ballast resistor layer by diffusion. Here, it is determined that the diffused holes recombine with the electrons through the DX center, and lattice defects are propagated by the energy released at this time, leading to device deterioration.

1: semi-insulating GaAs substrate, 2: n-type GaAs subcollector layer, 3: n-type GaAs collector layer, 4: p-type GaAs base layer, 5: n-type InGaP emitter layer, 6: n-type GaAs layer, 7: n-type AlGaAs ballast resistor layer, 8: n-type GaAs contact layer, 9: n-type InGaAs contact layer, 10: isolation groove, 11: collector electrode, 12: base electrode, 13: emitter electrode, 14: collector wiring, 15 : Base wiring, 16: Emitter wiring, 17: Pad, 18: Pad, 19: Pad, 20: n-type GaAs layer, 21: HBT equivalent circuit, 22: Protection element equivalent circuit, 23: Power amplifier circuit block diagram, 24 : First amplifier circuit, 25: second amplifier circuit, 26a: input matching circuit, 26b: interstage matching circuit, 26c: output matching circuit, 27: high frequency Power terminal, 28: high-frequency output terminal, 51: semiconductor element, 52: passive element, 54: conductive layer, 60: mounting board, 61: mounting board, 62: mounting board.

Claims (4)

A power amplifier having a multistage connection of amplifier circuits configured by connecting at least one heterojunction bipolar transistor in parallel, and the bipolar transistor includes an InGaP emitter layer and the InGaP emitter of the InGaP emitter layer At least a structure in which a GaAs layer and an AlGaAs ballast resistor layer are sequentially formed on the side opposite to the base layer forming a heterojunction with the layer, and between the InGaP emitter layer and the AlGaAs ballast resistor layer, A power amplifier comprising: a GaAs layer, wherein the GaAs layer is thicker than a depletion layer formed at a heterojunction between the emitter layer and the base layer . 2. The power amplifier according to claim 1, further comprising a voltage limiting protection circuit electrically connected in parallel between an emitter and a collector of the heterojunction bipolar transistor connected in parallel . The InGaP emitter layer and the AlGaAs ballast resistor layer and the power amplifier according to any one of claims 1 to 2, characterized in that there is no direct contact. A step of sequentially laminating at least a subcollector semiconductor layer, a collector semiconductor layer, a base semiconductor layer, an InGaP emitter semiconductor layer, a GaAs semiconductor layer, and an AlGaAs ballast resistor semiconductor layer on the semi-insulating substrate;
Forming an emitter electrode of a desired shape on the AlGaAs ballast resistor semiconductor layer;
Processing the AlGaAs ballast resistor semiconductor layer and the GaAs semiconductor layer into a mesa shape to expose the InGaP emitter semiconductor layer;
Forming a base electrode that penetrates through the exposed InGaP emitter semiconductor layer and reaches the base semiconductor layer;
Processing the InGaP emitter semiconductor layer, the base semiconductor layer, and the collector semiconductor layer into a mesa shape to expose the subcollector semiconductor layer;
Forming a collector electrode on the exposed subcollector semiconductor layer;
The method of manufacturing a heterojunction bipolar transistor, wherein the GaAs semiconductor layer is thicker than a depletion layer formed at a heterojunction between the emitter semiconductor layer and the base semiconductor layer .

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