JP2015185649A - Semiconductor device and power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and power amplifier capable of improving current drive capability while ensuring a low-voltage operation.SOLUTION: The semiconductor device with a bipolar transistor BT is configured so that an n-type collector layer 4 is a two-layer structure of a first collector layer 4a of n-type GaAs including gallium arsenide (GaAs) and a second collector layer 4b (GaN molar ratio: 0.018) of n-type GaAsN including nitriding gallium arsenide (GaAsN), and is formed with a p-type Ge base layer 5 including germanium (Ge) to be in contact with the second collector layer 4b of n-type GaAsN.

Description

  The present invention relates to a semiconductor device and a power amplifier, and particularly to a semiconductor device including a heterojunction bipolar transistor and a power amplifier to which such a semiconductor device is applied.

  In recent years, heterojunction bipolar transistors have been used as transistors constituting power amplifier modules such as portable terminals. This type of bipolar transistor is called HBT (Hetero junction Bipolar Transistor). One of the characteristics required for this bipolar transistor is low voltage operation. In order to operate at a low voltage, it is required to reduce the energy band gap of the base layer. Germanium (Ge) is a semiconductor material that reduces the energy band gap.

  Therefore, as an example of a semiconductor device in which germanium (Ge) is applied to the base layer, a semiconductor device described in Patent Document 1 will be described. As shown in FIG. 27, in the bipolar transistor BT, an n-type GaAs subcollector layer 102 is formed so as to be in contact with the semi-insulating GaAs substrate 101.

  An n-type GaAs collector layer 103 is formed so as to be in contact with the n-type GaAs subcollector layer 102. A p-type Ge base layer 104 is formed in contact with the n-type GaAs collector layer 103. An n-type InGaP emitter layer 105 is formed so as to be in contact with the p-type Ge base layer 104.

  An n-type InGaP contact layer 106 is formed so as to be in contact with the n-type InGaP emitter layer 105, and an n-type GaAs emitter contact layer 107 is formed so as to be in contact with the n-type InGaP contact layer 106. An n-type InGaAs emitter contact layer 108 is formed in contact with the n-type GaAs emitter contact layer 107.

  An emitter electrode 113 is formed so as to be in contact with the n-type InGaAs emitter contact layer 108. A base electrode 112 is formed so as to be in contact with the p-type Ge base layer 104. A collector electrode 111 is formed in contact with the n-type GaAs subcollector layer 102. The semiconductor device according to the background art is configured as described above.

JP 2003-243406 A

However, the conventional semiconductor device has the following problems.
The p-type Ge base layer 104 is formed in contact with the n-type GaAs collector layer 103. Here, the energy band gap of germanium (Ge) constituting the p-type Ge base layer 104 is about 0.7 eV, whereas the energy band of gallium arsenide (GaAs) constituting the n-type GaAs collector layer 103. The gap is about 1.4 eV.

  For this reason, at the junction between the p-type Ge base layer 104 and the n-type GaAs collector layer 103, an energy band gap (about 1.4 eV) of gallium arsenide (GaAs) and an energy band gap of germanium (Ge) (about about Due to the difference from 0.7 eV), an energy barrier appears.

  In the bipolar transistor, electrons injected from the n-type InGaP emitter layer 105 into the p-type Ge base layer 104 move in the p-type Ge base layer 104 toward the n-type GaAs collector layer 103 by diffusion.

  However, when electrons reach the junction between the p-type Ge base layer 104 and the n-type GaAs collector layer 103, injection of electrons into the n-type GaAs collector layer 103 is suppressed by the energy barrier described above. For this reason, a sufficient collector current cannot be obtained, and there is a risk that improvement of the current driving capability as a bipolar transistor may be hindered.

  The present invention has been made to solve the above problems, and one object is to provide a semiconductor device capable of improving the current driving capability while ensuring low voltage operation, and the other object is An object of the present invention is to provide a power amplifier to which such a semiconductor device is applied.

  The semiconductor device according to the present invention is a semiconductor device including a heterojunction bipolar transistor. The bipolar transistor has a collector layer, a base layer, and an emitter layer. The base layer is formed on the collector layer and includes germanium (Ge). The emitter layer is formed on the base layer. The collector layer includes a first collector layer containing gallium arsenide (GaAs) and a second collector layer containing gallium arsenide (GaAsN) containing gallium nitride (GaN). The second collector layer and the base layer are formed in contact with each other.

  According to the semiconductor device of the present invention, the second collector layer containing gallium nitride (GaAsN) containing gallium nitride (GaN) and the base layer containing germanium (Ge) are formed in contact with each other. . Thus, a sufficient collector current can be obtained while ensuring a low voltage operation, and the current driving capability can be improved.

  The molar ratio of gallium nitride (GaN) in the second collector layer is preferably set to 0.018 or more at least in a portion in contact with the base layer.

  Thereby, the energy barrier of the junction part of a base layer and a collector layer can be eliminated reliably.

  The molar ratio of gallium nitride (GaN) in the second collector layer is preferably set so that the molar ratio in the first portion in contact with the base layer is higher than the molar ratio in the second portion in contact with the first collector layer.

  Furthermore, the molar ratio in the second portion is set to 0, and the second collector layer is more preferably formed with a profile in which the molar ratio gradually decreases from the first portion to the second portion.

  Thereby, the feedback capacity between the base and the collector can be suppressed, and the high frequency characteristics can be improved.

When the molar ratio of gallium nitride (GaN) in the second collector layer is X, the thickness of the second collector layer is an allowance calculated by the following equation: d (nm) = 1.792 · X- ^1.141 It is preferable that the thickness be set to a thickness d or less.

  As a result, misfit dislocations can be prevented from occurring in the second collector layer.

  The bipolar transistor is preferably formed on the surface of the substrate, and the surface of the substrate preferably has an off angle inclined at least 2 degrees in the <011> direction with respect to the crystal plane {100} of the substrate.

  As a result, the occurrence of a crystal defect region called an anti-phase domain can be suppressed, and the energization reliability of the bipolar transistor can be ensured.

  Specifically, the emitter layer is preferably formed of either indium gallium phosphide (InGaP) or aluminum gallium arsenide (AlGaAs).

  It is preferable that a plurality of bipolar transistors are provided, and the plurality of bipolar transistors are electrically connected in parallel.

Thereby, large power can be handled as a semiconductor device.
The power amplifier according to the present invention is a power amplifier in which the above-described semiconductor device is mounted.

  According to the power amplifier of the present invention, it is possible to cope with a large power.

It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view taken along a cross-sectional line II-II shown in FIG. 1 in the same embodiment. It is a figure which shows typically the energy band of the bipolar transistor of the semiconductor device which concerns on a comparative example. FIG. 3 is a diagram schematically showing a profile of a molar ratio of GaN in an n-type GaAsN second collector layer of the bipolar transistor shown in FIGS. 1 and 2 and an energy band of the bipolar transistor in the same embodiment. In the same embodiment, it is a graph which shows the relationship between the molar ratio of GaN, and allowable maximum film thickness. In the same embodiment, it is a fragmentary sectional view which shows typically the structure of the semi-insulating GaAs substrate as an inclination board | substrate. It is a top view of the semiconductor device provided with the bipolar transistor based on Embodiment 2 of this invention. FIG. 8 is a cross sectional view taken along a cross sectional line VIII-VIII shown in FIG. 7 in the same embodiment. FIG. 9 is a diagram schematically showing a profile of a molar ratio of GaN in the n-type GaAsN second collector layer of the bipolar transistor shown in FIGS. 7 and 8 in the same embodiment. FIG. 9 is a diagram schematically showing a profile of a molar ratio of GaN in an n-type GaAsN second collector layer of the bipolar transistor shown in FIGS. 7 and 8 and an energy band of the bipolar transistor in the same embodiment. In the same embodiment, it is a figure showing typically the modification of the profile of the molar ratio of GaN in the n type GaAsN 2nd collector layer of a bipolar transistor. In the same embodiment, it is a figure showing typically other modifications of the profile of the molar ratio of GaN in the n type GaAsN second collector layer of a bipolar transistor. It is a circuit diagram which shows the connection aspect of the bipolar transistor in the semiconductor device provided with the several bipolar transistor based on Embodiment 3 of this invention. In the same embodiment, it is a top view of the semiconductor device provided with the some bipolar transistor. FIG. 15 is a cross-sectional view taken along a cross-sectional line XV-XV shown in FIG. 14 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device provided with the several bipolar transistor based on Embodiment 4 of this invention. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. It is a block diagram which shows the structure of the power amplifier with which the semiconductor device provided with the several bipolar transistor based on Embodiment 5 of this invention was applied. 4 is a partial cross-sectional view schematically showing a semiconductor device mounted on a power amplifier and its peripheral portion in the embodiment. FIG. It is sectional drawing which shows the semiconductor device provided with the bipolar transistor based on background art.

Embodiment 1
Here, a first example of a semiconductor device provided with a collector layer having a two-layer structure as a collector layer of a bipolar transistor will be described.

As shown in FIGS. 1 and 2, an undoped GaAs buffer layer 2 (film thickness: 0.1 μm) is formed so as to be in contact with the surface of the semi-insulating GaAs substrate 1. Note that, as the semi-insulating GaAs substrate 1, an inclined substrate is used in which the substrate surface is inclined at a predetermined angle from the crystal plane, as will be described later. An n-type GaAs subcollector layer 3 (Si doping concentration: 5 × 10 ¹⁸ cm ⁻³ , film thickness: 0.6 μm) is formed so as to be in contact with the undoped GaAs buffer layer 2.

An n-type collector layer 4 is formed in contact with the n-type GaAs subcollector layer 3. The n-type collector layer 4 includes an n-type GaAs first collector layer 4a (Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 1.0 μm) containing gallium arsenide (GaAs), and gallium arsenide (GaAsN). And a n-type GaAsN second collector layer 4b (GaN molar ratio: 0.018, Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 100 nm). The n-type GaAs first collector layer 4a is formed in contact with the n-type GaAs sub-collector layer 3, and the n-type GaAsN second collector layer 4b is formed in contact with the n-type GaAs first collector layer 4a. .

A p-type Ge base layer 5 (Ga doping concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 150 nm) containing germanium (Ge) is formed in contact with the n-type GaAsN second collector layer 4b. An n-type InGaP emitter layer 6 containing indium gallium phosphide (InGaP) so as to be in contact with the p-type Ge base layer 5 (InP molar ratio: 0.48, Si doping concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 30 nm) ) Is formed.

An n-type GaAs contact layer 8 (Si doping concentration: 5 × 10 ¹⁸ cm ⁻³ , film thickness: 50 nm) is formed so as to be in contact with the n-type InGaP emitter layer 6. An n-type InGaAs contact layer 9 (InAs molar ratio: 0.5, Si doping concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) is formed so as to be in contact with the n-type GaAs contact layer 8. The emitter size is 3 μm × 20 μm, which is a rectangular emitter.

  An emitter electrode 13 is disposed in contact with the n-type InGaAs contact layer 9. A collector electrode 11 is disposed in contact with the n-type GaAs subcollector layer 3. A base electrode 12 is disposed in contact with the p-type Ge base layer 5 via the emitter layer 6. The collector electrode 11 is formed by stacking AuGe (film thickness: 60 nm) / Ni (film thickness: 10 nm) / Au (film thickness: 200 nm). The base electrode 12 is formed by stacking Ti (film thickness: 50 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm). The emitter electrode 13 is formed of WSi (Si molar ratio: 0.3, film thickness: 0.3 μm).

  Metal pads 17, 18, and 19 are formed on the periphery of the semi-insulating GaAs substrate 1 for electrical connection with the outside of the bipolar transistor BT. The collector electrode 11 and the metal pad 19 are electrically connected by the collector wiring 14. The base electrode 12 and the metal pad 18 are electrically connected by the base wiring 15. The emitter electrode 13 and the metal pad 17 are electrically connected by the emitter wiring 16.

  As for each layer constituting the bipolar transistor BT, for example, the n-type GaAsN second collector layer 4b is expressed as an n-type GaAsN second collector layer 4b containing gallium arsenide (GaAsN). This does not mean that the second collector layer is formed only from gallium arsenide nitride (GaAsN), and the second collector layer is formed substantially from gallium arsenide nitride (GaAsN), It means that impurities for setting to a predetermined conductivity type, impurities in the manufacturing process, and the like are included. The same applies to the other n-type GaAs first collector layer 4a, p-type Ge base layer 5, n-type InGaP emitter layer 6, and the like.

  In the semiconductor device including the bipolar transistor BT described above, since the n-type collector layer 4 includes the n-type GaAsN second collector layer 4b, the current driving capability can be improved while ensuring a low voltage operation. This will be described with reference to a semiconductor device shown in FIG. 27 as a comparative example, in relation to the semiconductor device according to the comparative example.

  In the semiconductor device according to the comparative example, it has been described that an energy barrier appears at the junction between the base layer and the collector layer. The energy band (potential energy) is schematically shown in FIG. As shown in FIG. 3, at the junction (junction CJ) between the p-type Ge base layer 104 and the n-type GaAs collector layer 103, the energy band gap (1.4 eV) of gallium arsenide (GaAs) and germanium (Ge) The energy barrier 200 appears due to the difference from the energy band gap (0.7 eV).

Therefore, electrons (e ⁻ ) injected from the n-type InGaP emitter layer 105 into the p-type Ge base layer 104 and reaching the junction CJ are injected into the n-type GaAs collector layer 103 by the energy barrier 200 described above. Will be hindered. As a result, the semiconductor device according to the comparative example cannot obtain a sufficient collector current.

  In contrast to the semiconductor device according to the comparative example, in the semiconductor device including the bipolar transistor according to the present embodiment, the n-type collector layer 4 includes the n-type GaAs first collector layer 4a and the n-type GaAsN second collector layer 4b. The n-type GaAsN second collector layer 4b is formed in contact with the n-type GaAs first collector layer 4a. The molar ratio of GaN (gallium nitride) in the n-type GaAsN second collector layer 4b is set to 0.018.

Here, FIG. 4 schematically shows the profile of the molar ratio of GaN (upper side) and the energy band (potential energy) (lower side) of the bipolar transistor. As shown in FIG. 4, the molar ratio of GaN in the n-type GaAsN second collector layer 4b is set to a constant value in the thickness direction of the n-type GaAsN second collector layer 4b. (GaAs _1-x N _x : x = 0.018).

  Thus, by using a layer in which nitrogen (N) is added to the n-type GaAs layer as the collector layer, the potential energy at the conduction band edge Ec is such that the conduction band edge of the n-type GaAs layer to which nitrogen (N) is not added. It will be lower than the potential energy of Ec.

  As a result, the energy barrier disappears at the junction (junction portion J1) between the p-type Ge base layer 5 and the n-type collector layer 4, and is injected from the n-type InGaP emitter layer 6 into the p-type Ge base layer 5 and joined to the junction portion J1. The electrons that have reached are efficiently injected into the n-type collector layer 4. Moreover, the p-type Ge base layer 5 having a relatively small energy band gap is formed as the base layer. As a result, a sufficient collector current can be obtained while ensuring a low voltage operation, and the current driving capability can be improved.

  In Patent Document 1 that discloses a semiconductor device as a comparative example, in addition to the semiconductor device shown in FIG. 27, n that becomes a part of the collector layer between the p-type Ge base layer and the n-type GaAs collector layer. A semiconductor device (semiconductor device C) in which a type Ge layer is interposed has been proposed. In such a bipolar transistor of the semiconductor device C, the junction between the emitter layer and the base layer is a heterojunction, and the junction between the collector layer and the base layer is a homojunction between the n-type Ge layer and the p-type Ge layer. A single heterojunction bipolar transistor is obtained.

  On the other hand, in the bipolar transistor of the semiconductor device according to the present embodiment, the junction between the emitter layer and the base layer is a heterojunction between the n-type InGaP emitter layer 6 and the p-type Ge base layer 5, and the collector layer and the base layer This junction is a double heterojunction bipolar transistor which is a heterojunction between the n-type GaAsN second collector layer 4b and the p-type Ge base layer 5.

  In the double heterojunction bipolar transistor and the single heterojunction bipolar transistor, the offset voltage of the double heterojunction bipolar transistor is lower than the offset voltage of the single heterojunction bipolar transistor.

  That is, in the graph showing the relationship between the collector-emitter voltage and the collector current, the graph corresponding to the double heterojunction bipolar transistor has a higher collector-emitter voltage than the graph corresponding to the single heterojunction bipolar transistor. It will rise from a low voltage.

  For this reason, for the same collector-emitter voltage, a bipolar transistor with a double heterojunction has a higher collector current in a low voltage region than a bipolar transistor with a single heterojunction. On the other hand, for the same collector current, a bipolar transistor having a double heterojunction has a lower collector-emitter voltage than a bipolar transistor having a single heterojunction.

  Therefore, in the double heterojunction bipolar transistor described above, the current drive capability (collector current) can be improved and the on-voltage (collector-emitter) can be improved as compared with the single heterojunction bipolar transistor described in Patent Document 1. Voltage).

  Further, the above-described semiconductor device can ensure a higher breakdown voltage than the semiconductor device C proposed in Patent Document 1 from the viewpoint of breakdown voltage.

  In a heterojunction bipolar transistor used in a power amplifier, the breakdown voltage between the base and the collector is the breakdown voltage of the bipolar transistor, and this breakdown voltage is determined by the energy band gap on the collector side.

  In the semiconductor device according to the present embodiment, the n-type GaAsN second collector layer 4b is in contact with the p-type Ge base layer. On the other hand, in the semiconductor device C proposed in the prior art document 1, the n-type Ge layer is in contact with the p-type base layer as a part of the collector layer. Among gallium arsenide (GaAsN) and germanium (Ge), gallium arsenide (GaAsN) has a larger energy band gap than germanium (Ge). Therefore, the bipolar transistor described above can obtain a higher breakdown voltage than the bipolar transistor proposed in Patent Document 1.

  In the semiconductor device described above, the case where the molar ratio of GaN in the n-type GaAsN second collector layer 4b is set to 0.018 has been described as an example. The value of this molar ratio is based on the energy band gap (about 0.7 eV) of the p-type Ge base layer 5 and the energy band gap (about 1.4 eV) of the n-type GaAs first collector layer 4a. The potential energy (potential energy EFC) of the conduction band edge Ec in the portion of the n-type collector layer 4 in contact with the Ge base layer 5 is the same as the potential energy (potential energy EB) of the conduction band edge Ec in the p-type Ge base layer 5. It is a value set to be

  In the bipolar transistor BT, if the potential energy EFC is the same as or lower than the potential energy EB, electrons reaching the junction portion J1 can be efficiently injected into the n-type collector layer 4. Therefore, the molar ratio of GaN in the n-type collector layer 4 should be set to 0.018 or more in at least the junction portion J1 with the p-type Ge base layer 5.

  By the way, since the lattice constant of the n-type GaAsN second collector layer 4b containing gallium nitride (GaN) is different from the lattice constant of the underlying n-type GaAs first collector layer 4a, the film of the n-type GaAsN second collector layer 4b. If the thickness is greater than a predetermined thickness, misfit dislocations may occur. As the film thickness of the n-type GaAsN second collector layer 4b, the film thickness (allowable film thickness) that does not cause such misfit dislocations needs to be determined depending on the molar ratio of GaN.

The allowable film thickness d is expressed by the following relational expression d (nm) <1.792 · X- ^1.141 , where X is the molar ratio of GaN.
It is calculated | required by inventors' evaluation to satisfy | fill. FIG. 5 shows the relationship (graph) between the allowable film thickness d and the molar ratio X of GaN. In order to prevent misfit dislocations from occurring in the n-type GaAsN second collector layer 4b, the film thickness of the n-type GaAsN second collector layer 4b is a film thickness in a region below the graph with respect to the molar ratio of GaN. Must be set to

  In the semiconductor device described above, an inclined substrate having the substrate surface inclined from the crystal plane is used as the semi-insulating GaAs substrate 1. Next, the inclined substrate will be described.

  In the bipolar transistor BT, predetermined layers such as a subcollector layer, a collector layer, a base layer, an emitter layer, and a contact layer are formed by an epitaxial growth method. In particular, the n-type InGaP layer that becomes the n-type InGaP emitter layer 6 is formed in contact with the p-type Ge layer that becomes the p-type Ge base layer. Here, the p-type Ge layer is a nonpolar crystal composed of only group IV atoms. On the other hand, the n-type InGaP layer is a polar crystal composed of group III atoms and group V atoms.

  For this reason, in the first stage of epitaxial growth, two types of regions, a region where gallium (Ga) is bonded and a region where phosphorus (P) is bonded, are generated on the surface of the p-type Ge layer. This causes a crystal defect region called an antiphase domain. Such a crystal defect becomes a factor of reducing the energization reliability of the bipolar transistor.

  In the semiconductor device described above, as shown in FIG. 6, as the semi-insulating GaAs substrate 1, the substrate surface 1a is set at 2 degrees (θ) or more, preferably 4 degrees from the crystal plane {100} to the <011> direction. A GaAs substrate tilted as described above is used. As a result, the occurrence of a crystal defect region called an anti-phase domain can be suppressed, and the energization reliability of the bipolar transistor can be ensured.

Embodiment 2
Here, a second example of a semiconductor device provided with a collector layer having a two-layer structure as a collector layer of a bipolar transistor will be described.

As shown in FIGS. 7 and 8, in the bipolar transistor BT of the semiconductor device according to the present embodiment, the n-type collector layer 4 includes an n-type GaAs first collector layer 4a (Si doping concentration: 1 × 10 ¹⁶ cm ^{−). 3} and a film thickness: 1.0 μm) and an n-type GaAsN second collector layer 4b (Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 100 nm). In the second embodiment, the n-type GaAsN second collector layer 4b has a profile in which the molar ratio of GaN changes in the thickness direction. Since other configurations are similar to those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device according to the present embodiment, the feedback capacity between the base and the collector can be reduced by changing the molar ratio of GaN in the n-type GaAsN second collector layer 4b with respect to the thickness direction. This will be described.

  In the n-type GaAsN second collector layer 4b of the semiconductor device according to the first embodiment, the molar ratio of GaN is set to a constant value in the thickness direction. For this reason, as shown in FIG. 4, the potential energy of the conduction band edge Ec is uniformly lowered, and in the n-type GaAsN second collector layer 4b, the energy barrier of the junction portion J1 with the p-type Ge base layer 5 is obtained. On the other hand, a potential energy well is formed at the junction (junction portion J2) with the n-type GaAs first collector layer 4a.

  When a potential energy well is generated, it is assumed that electrons injected into the p-type Ge base layer 5 are trapped in the potential energy well when injected into the n-type collector layer 4. When electrons are trapped, the feedback capacitance between the base and the emitter increases, and it is assumed that the high frequency characteristics cannot be sufficiently improved.

  In the n-type GaAsN second collector layer 4b of the semiconductor device according to the present embodiment, as shown in FIG. 9, the molar ratio of GaN changes with respect to the thickness direction. The junction portion J1 is set to 0.018, and the junction portion J2 with the n-type GaAs first collector layer 4a is set to 0. The GaN molar ratio is linearly changed between the junction portion J1 and the junction portion J2.

  As a result, in the n-type GaAsN second collector layer 4b, the reduction amount of the potential energy at the conduction band edge Ec can be changed in the thickness direction. As a result, as shown in FIG. 10, the energy barrier can be eliminated at the junction portion J1, and the potential energy well can be eliminated at the junction portion J2.

  As described above, in the semiconductor device according to the present embodiment, since the energy barrier at the junction portion J1 is eliminated, a sufficient collector current can be obtained while ensuring a low voltage operation as in the case of the semiconductor device according to the first embodiment. And the current drive capability can be improved. Further, since the potential energy well in the junction J2 can be eliminated, the feedback capacitance between the base and the collector can be suppressed, the high frequency characteristics can be improved, and the power gain (gain) can be sufficiently increased. it can.

  In the n-type GaAsN second collector layer 4b in the bipolar transistor described above, a GaN layer is formed between the junction J1 with the p-type Ge base layer 5 and the junction J2 with the n-type GaAs first collector layer 4a. The case where the molar ratio was changed linearly was explained. The profile of the molar ratio is not limited to such a linearly changing profile, and any profile in which the molar ratio gradually decreases from the joint portion J1 to the joint portion J2 may be used. For example, as shown in FIG. 11, it may be a profile like a curve that is convex upward. Further, as shown in FIG. 12, the profile may be a curve that is convex downward.

  Further, in the bipolar transistor described above, similarly to the bipolar transistor described above, the GaN molar ratio is set as the film thickness of the n-type GaAsN second collector layer 4b in order to prevent misfit dislocations due to crystal lattice mismatch. On the other hand, it is necessary to set the film thickness in the region below the graph shown in FIG. Further, as the semi-insulating GaAs substrate 1, the substrate surface 1a is inclined by 2 degrees (θ) or more, preferably 4 degrees or more with respect to the <011> direction from the crystal plane {100}, similarly to the bipolar transistor described above. A GaAs substrate is used (see FIG. 6).

Embodiment 3
Here, as a third example of a semiconductor device including a bipolar transistor, a semiconductor device including a plurality of semiconductor devices according to the first example will be described.

  In a power amplifier module of a mobile terminal in which relatively large power is handled, the power amplifier module is configured by a plurality of HBTs connected in parallel. In this case, as shown in FIG. 13, the plurality of bipolar transistors BT are connected in parallel in such a manner that their emitters, bases and collectors are electrically connected to each other.

  Next, the bipolar transistor of the semiconductor device according to the first example is used as a unit bipolar transistor, and a semiconductor device including a plurality of bipolar transistors will be specifically described.

As shown in FIGS. 14 and 15, in each of the plurality of bipolar transistors BT, an n-type collector layer 4 is formed so as to be in contact with the n-type GaAs subcollector layer 3. The n-type collector layer 4 includes an n-type GaAs first collector layer 4a (Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 1.0 μm) and an n-type GaAsN second collector layer 4b (GaN molar ratio: 0.018, Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 100 nm).

The n-type GaAs first collector layer 4a is formed in contact with the n-type GaAs sub-collector layer 3, and the n-type GaAsN second collector layer 4b is formed in contact with the n-type GaAs first collector layer 4a. . A p-type Ge base layer 5 (Ga doping concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 150 nm) is formed in contact with the n-type GaAsN second collector layer 4b.

  Metal pads 17, 18, and 19 are formed on the periphery of the semi-insulating GaAs substrate 1 for electrical connection with the outside of the bipolar transistor BT. Each collector electrode 11 of the plurality of bipolar transistors BT is electrically connected to a metal pad 19 by a collector wiring 14. Each base electrode 12 of the plurality of bipolar transistors BT is electrically connected to a metal pad 18 by a base wiring 15.

  Each emitter electrode 13 of the plurality of bipolar transistors BT is electrically connected to a metal pad 17 by an emitter wiring 16. Since other configurations are similar to those of the semiconductor device shown in FIGS. 1 and 2, the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

  In the semiconductor device including a plurality of bipolar transistors as described above, a large amount of power can be handled as a semiconductor device by connecting a plurality of bipolar transistors in parallel to a BT.

  In each of the bipolar transistors BT, the n-type collector layer 4 has a two-layer structure of an n-type GaAs first collector layer 4a and an n-type GaAsN second collector layer 4b, and the n-type GaAsN second collector layer 4b. Is formed in contact with the n-type GaAs first collector layer 4a. The molar ratio of GaN in the n-type GaAsN second collector layer 4b is set to 0.018.

  As a result, as described in the first embodiment, there is no energy barrier at the junction J1 between the p-type Ge base layer 5 and the n-type collector layer 4, and the n-type InGaP emitter layer 6 changes to the p-type Ge base layer 5. The electrons that have been injected and reach the junction portion J1 are efficiently injected into the n-type collector layer 4. Moreover, the p-type Ge base layer 5 having a relatively small energy band gap is formed as the base layer. As a result, a sufficient collector current can be obtained while ensuring a low voltage operation, and the current driving capability can be improved.

  The bipolar transistor BT of the semiconductor device described in the first embodiment has been described as an example of each of the plurality of bipolar transistors BT in the semiconductor device described above, but the bipolar transistor of the semiconductor device described in the second embodiment is taken as an example. BT may be applied. In this case, the feedback capacitance between the base and the collector can be further suppressed, the high frequency characteristics can be improved, and the power gain (gain) can be sufficiently increased.

Embodiment 4
Here, an example of a method for manufacturing the semiconductor device described in Embodiment 3 will be described.

  First, as a semi-insulating GaAs substrate, a GaAs substrate having a substrate surface inclined by, for example, about 4 degrees with respect to the <011> direction from the crystal plane {100} is prepared. Next, predetermined layers such as a sub-collector layer, a collector layer, a base layer, an emitter layer, and a contact layer are formed on the surface of the semi-insulating GaAs substrate by metal organic chemical vapor deposition (MOCVD). It is formed by an epitaxial growth method such as Vapor Deposition.

As shown in FIG. 16, an undoped GaAs layer 2 a (film thickness: 0.1 μm) serving as an undoped GaAs buffer layer is formed so as to be in contact with the surface of the semi-insulating GaAs substrate 1. An n-type GaAs layer 3a (Si doping concentration: 5 × 10 ¹⁸ cm ⁻³ , film thickness: 0.6 μm) serving as an n-type GaAs subcollector layer is formed in contact with the undoped GaAs layer 2a. An n-type GaAs layer 4aa (Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 1.0 μm) serving as an n-type GaAs first collector layer is formed in contact with the n-type GaAs layer 3a.

An n-type GaAsN layer 4bb serving as an n-type GaAsN second collector layer (GaN molar ratio: 0.018, Si doping concentration: 1 × 10 ¹⁶ cm ⁻³ , film thickness: 100 nm) in contact with the n-type GaAs layer 4aa Is formed. Here, the GaN molar ratio in the thickness direction of the n-type GaAsN layer 4bb is set to a constant value (0.018) by setting the amount of nitrogen (N) contained in the organometallic gas to a constant amount. .

A p-type Ge layer 5a (Ga doping concentration: 4 × 10 ¹⁹ cm ⁻³ , film thickness: 150 nm) serving as a p-type Ge base layer is formed in contact with the n-type GaAsN layer 4bb. An n-type InGaP layer 6a (InP molar ratio: 0.48, Si doping concentration: 3 × 10 ¹⁷ cm ⁻³ , film thickness: 30 nm) to be an n-type InGaP emitter layer is formed so as to be in contact with the p-type Ge layer 5a. Is done.

An n-type GaAs layer 8a (Si doping concentration: 5 × 10 ¹⁸ cm ⁻³ , film thickness: 50 nm) serving as an n-type GaAs contact layer is formed in contact with the n-type InGaP layer 6a. An n-type InGaAs layer 9a (InAs molar ratio: 0.5, Si doping concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 50 nm) serving as an n-type InGaAs contact layer is formed so as to be in contact with the n-type GaAs layer 8a. Is done.

Next, as shown in FIG. 17, a tungsten silicide (WSi) film (Si molar ratio: 0.3, film thickness: 0.3 μm) 13a is formed on the entire surface of the n-type InGaAs layer 9a by high frequency sputtering. Is deposited. Next, by performing a predetermined photolithography process and a dry etching process using a gas containing CF ₄ , the emitter electrodes 13 of the plurality of bipolar transistors are formed as shown in FIG.

  Next, by performing predetermined photolithography processing and wet etching processing on the n-type InGaAs layer 9a and the n-type GaAs layer 8a, as shown in FIG. 19, the n-type InGaAs contact layer 9 and the emitter region are formed. An n-type GaAs contact layer 8 is formed. Here, for example, a chemical solution in which phosphoric acid, hydrogen peroxide solution and water are mixed is used as the wet etching solution, and the composition ratio thereof is, for example, phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40. Set to

  Next, as shown in FIG. 20, the base electrode 12 is formed by vapor deposition and lift-off so as to penetrate the n-type InGaP layer 6a in contact with the p-type Ge layer 5a. The base electrode 12 has a laminated structure of Ti (film thickness: 50 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm).

  Next, by performing a predetermined photolithography process and a wet etching process, as shown in FIG. 21, the n-type InGaP emitter layer 6, the p-type Ge base layer 5, the n-type GaAsN of each of the plurality of bipolar transistors. A second collector layer 4b and an n-type GaAs first collector layer 4a are formed.

  Here, hydrochloric acid is used as an etchant for etching the n-type InGaP layer 6a. As an etchant for etching the p-type Ge layer 5, the n-type GaAsN layer 4bb, and the n-type GaAs layer 4aa, a chemical solution in which phosphoric acid, hydrogen peroxide solution, and water are mixed is used. , Phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40.

  Next, as shown in FIG. 22, the collector electrodes 11 of the plurality of bipolar transistors are formed by the vapor deposition method and the lift-off method. Thereafter, alloying is performed at a temperature of 350 ° C. for 30 minutes. The collector electrode 11 is made of a laminate of AuGe (film thickness: 60 nm) / Ni (film thickness: 10 nm) / Au (film thickness: 200 nm). Thereby, each of the plurality of bipolar transistors BT is formed.

  Next, by performing a predetermined wet etching process, the isolation groove 10 is formed as shown in FIG. Here, as the wet etching solution, a chemical solution in which phosphoric acid, hydrogen peroxide solution and water are mixed is used, and the composition ratio is set to, for example, phosphoric acid: hydrogen peroxide solution: water = 1: 2: 40. Is done. Next, metal pads 17, 18, 19 (see FIG. 14) are formed in predetermined regions in the semi-insulating GaAs substrate 1.

  Next, as shown in FIG. 24, an emitter wiring 16 that electrically connects each emitter electrode 13 of the bipolar transistor BT and the metal pad 17 is formed. Base wiring 15 for electrically connecting base electrode 12 and metal pad 18 is formed. A collector wiring 14 that electrically connects the collector electrode 11 and the metal pad 19 is formed. As a result, a main part of the semiconductor device including a plurality of bipolar transistors is formed.

  In the semiconductor device manufacturing method described above, a semiconductor device capable of handling high power can be manufactured by connecting a plurality of bipolar transistors BT in parallel.

  In each of the bipolar transistors BT, the n-type collector layer 4 has a two-layer structure of an n-type GaAs first collector layer 4a and an n-type GaAsN second collector layer 4b, and an n-type GaAsN second collector layer. 4b is formed in contact with the n-type GaAs first collector layer 4a. The molar ratio of GaN in the n-type GaAsN second collector layer 4b is set to 0.018.

  As a result, as described in the first embodiment, there is no energy barrier at the junction J1 between the p-type Ge base layer 5 and the n-type collector layer 4, and the n-type InGaP emitter layer 6 changes to the p-type Ge base layer 5. The electrons that have been injected and reach the junction portion J1 are efficiently injected into the n-type collector layer 4. Moreover, the p-type Ge base layer 5 having a relatively small energy band gap is formed as the base layer. As a result, a sufficient collector current can be obtained while ensuring a low voltage operation, and the current driving capability can be improved.

  In the above-described semiconductor device manufacturing method, the semiconductor device manufacturing method including a plurality of bipolar transistors of the semiconductor device according to the first example has been described. However, the semiconductor device including a plurality of bipolar transistors of the semiconductor device according to the second example. The device can be similarly formed. In particular, in this case, when the n-type GaAsN layer 4bb serving as the n-type GaAsN second collector layer is formed, the amount of nitrogen (N) contained in the organometallic gas is changed with time, whereby the n-type GaAsN layer The GaN molar ratio in the thickness direction of 4 bb can be adjusted. As a result, as described in the second embodiment, the feedback capacitance between the base and the collector can be suppressed, the high frequency characteristics can be improved, and the power gain (gain) can be sufficiently increased.

Embodiment 5
Here, a power amplifier in which the semiconductor device described in Embodiment 3 is mounted will be described.

  FIG. 25 shows a block diagram of a circuit of the power amplifier (module) 30. As shown in FIG. 25, the power amplifier 30 includes a two-stage amplifier circuit including a first amplifier circuit 34 and a second amplifier circuit 35. A semiconductor device in which a plurality of bipolar transistors are connected in parallel is applied to each of the first amplifier circuit 34 and the second amplifier circuit 35.

  In the power amplifier 30, the high frequency signal input from the high frequency input terminal 32 is amplified through the first amplification circuit 34 and the second amplification circuit 35, and the amplified high frequency signal is output from the high frequency output terminal 33.

  In order to achieve impedance matching, an input matching circuit 36 is provided between the high-frequency input terminal 32 and the first amplifier circuit 34, and interstage matching is provided between the first amplifier circuit 34 and the second amplifier circuit 35. A circuit 37 is provided, and an output matching circuit 38 is provided between the second amplifier circuit 35 and the high frequency output terminal 33.

  Next, a structure around the bipolar transistor of the semiconductor device applied to the first amplifier circuit 34 and the second amplifier circuit 35 will be briefly described. As shown in FIG. 26, in the power amplifier 30, a plurality of mounting boards 41, 42, and 43 are stacked. A bipolar transistor BT is formed on the mounting substrate 42.

  Further, passive elements 48 and 49 such as capacitors and inductors are formed on the mounting substrate 43 so as to achieve impedance matching. Furthermore, predetermined conductive layers 44, 45, 46, 47 for electrically connecting the bipolar transistor BT and the passive elements 48, 49 are formed on the mounting boards 41, 42, 43. In FIG. 26, a plurality of bipolar transistors are represented by one bipolar transistor BT.

  In the power amplifier 30 described above, a semiconductor device in which a plurality of bipolar transistors are connected in parallel is applied to each of the first amplifier circuit 34 and the second amplifier circuit 35. Accordingly, as described in Embodiment 3, a large amount of power can be handled as a semiconductor device.

  In each of the bipolar transistors BT, the n-type collector layer 4 has a two-layer structure of an n-type GaAs first collector layer 4a and an n-type GaAsN second collector layer 4b, and a p-type Ge as a base layer. A base layer 5 is formed (see FIG. 15). Thereby, as already explained, a sufficient collector current can be obtained while ensuring a low voltage operation, and the current driving capability can be improved.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a semiconductor device including a heterojunction bipolar transistor.

  BT heterojunction bipolar transistor, 1 semi-insulating GaAs substrate, 1a substrate surface, 2 undoped GaAs buffer layer, 3 n-type GaAs subcollector layer, 4 n-type collector layer, 4a n-type GaAs first collector layer, 4b n Type GaAsN second collector layer, 5 p type Ge base layer, 6 n type InGaP emitter layer, 8 n type GaAs contact layer, 9 n type InGaAs contact layer, 10 isolation groove, 11 collector electrode, 12 base electrode, 13 emitter Electrode, 14 Collector wiring, 15 Base wiring, 16 Emitter wiring, 17, 18, 19 Metal pad, 2a Undoped GaAs layer, 3a n-type GaAs layer, 4aa n-type GaAs layer, 4bb n-type GaAsN layer, 5a p-type Ge layer 6a n-type InGaP layer, 8a n-type G As layer, 9a n-type InGaAs layer, 13a tungsten silicide film, 30 power amplifier, 31 power amplifier circuit block, 32 high frequency input terminal, 33 high frequency output terminal, 34 first amplifier circuit, 35 second amplifier circuit, 36 input matching circuit , 37 Interstage matching circuit, 38 Output matching circuit, 41, 42, 43 Mounting board, 44, 45, 46, 47 Conductor layer, 48, 49 Passive element, 200 Energy barrier.

Claims (9)

A semiconductor device including a heterojunction bipolar transistor,
The bipolar transistor is:
A collector layer;
A base layer comprising germanium (Ge) formed on the collector layer;
An emitter layer formed on the base layer;
The collector layer is
A first collector layer comprising gallium arsenide (GaAs);
A second collector layer comprising gallium arsenide (GaAsN) containing gallium nitride (GaN),
A semiconductor device, wherein the second collector layer and the base layer are formed in contact with each other.   The semiconductor device according to claim 1, wherein a molar ratio of the gallium nitride (GaN) in the second collector layer is set to 0.018 or more at least in a portion in contact with the base layer.   The molar ratio of the gallium nitride (GaN) in the second collector layer was set such that the molar ratio in the first portion in contact with the base layer was higher than the molar ratio in the second portion in contact with the first collector layer. The semiconductor device according to claim 1. The molar ratio in the second part is set to 0;
The semiconductor device according to claim 3, wherein the second collector layer is formed with a profile in which the molar ratio gradually decreases from the first portion to the second portion. When the molar ratio of the gallium nitride (GaN) in the second collector layer is X,
The thickness of the second collector layer is given by the following formula:
d (nm) = 1.792 · X ^-1.141
The semiconductor device according to claim 1, wherein the semiconductor device is set to a thickness equal to or less than a thickness d calculated by: The bipolar transistor is formed on a surface of a substrate;
The semiconductor device according to claim 1, wherein the surface of the substrate has an off-angle inclined at least 2 degrees in the <011> direction with respect to the crystal plane {100} of the substrate.   The semiconductor device according to claim 1, wherein the emitter layer is formed of any one of indium gallium phosphide (InGaP) and aluminum gallium arsenide (AlGaAs). A plurality of the bipolar transistors;
The semiconductor device according to claim 1, wherein the plurality of bipolar transistors are electrically connected in parallel.   A power amplifier on which the semiconductor device according to claim 1 is mounted.

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