US7286071B1 - System for displaying images - Google Patents

System for displaying images Download PDF

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Publication number
US7286071B1
US7286071B1 US11/464,237 US46423706A US7286071B1 US 7286071 B1 US7286071 B1 US 7286071B1 US 46423706 A US46423706 A US 46423706A US 7286071 B1 US7286071 B1 US 7286071B1
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Prior art keywords
voltage
capacitor
significant bits
switch
bit
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Expired - Fee Related
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US11/464,237
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English (en)
Inventor
Fu-Yuan Hsueh
Keiichi Sano
Cheng-Ho Yu
Wei-Cheng Lin
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Innolux Corp
IPO Displays Corp
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IPO Displays Corp
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Priority to US11/464,237 priority Critical patent/US7286071B1/en
Assigned to TPO DISPLAYS CORP. reassignment TPO DISPLAYS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSUEH, FU-YUAN, LIN, WEI-CHENG, SANO, KEIICHI, YU, CHENG-HO
Priority to TW096127291A priority patent/TWI365432B/zh
Priority to JP2007211347A priority patent/JP2008046639A/ja
Priority to CN2007101436022A priority patent/CN101127184B/zh
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Publication of US7286071B1 publication Critical patent/US7286071B1/en
Assigned to CHIMEI INNOLUX CORPORATION reassignment CHIMEI INNOLUX CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: TPO DISPLAYS CORP.
Assigned to Innolux Corporation reassignment Innolux Corporation CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CHIMEI INNOLUX CORPORATION
Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree

Definitions

  • the invention relates to display panels.
  • LCDs Liquid crystal displays
  • LCDs are used in a variety of applications, including calculators, watches, color televisions, computer monitors, and many other electronic devices.
  • Active-matrix LCDs are a well known type of LCDs.
  • each picture element (or pixel) is addressed using a matrix of thin film transistors (TFTs) and one or more capacitors.
  • TFTs thin film transistors
  • the pixels are arranged and wired in an array having a plurality of rows and columns.
  • the switching TFTs of a specific row are switched “on” (i.e., charged with a voltage), and then data voltage is sent to the corresponding column. Since other intersecting rows are turned off, only the capacitor at the specific pixel receives the data voltage charge.
  • the liquid crystal cell of the pixel changes its polarization, and thus, the amount of light reflected from or passing through the pixel changes.
  • the magnitude of the applied voltage determines the amount of light reflected from or passing through the pixel.
  • “System-on-glass” LCDs that allow integration of various LCD driving circuits and functions require no external integrated circuits (ICs), providing low cost, compact and highly reliable displays.
  • the integrated driving circuits of such an LCD comprise a scan driver selecting a row of pixels and a data driver writing display data into each pixel in the selected row.
  • data drivers require digital-to-analog converters (DACs) to generate analog voltages serving as display data and driving corresponding pixels.
  • DACs in data driver require a larger layout area for high resolution applicant.
  • Embodiments of a system for displaying images are provided, in which a digital-to-analog converter comprises first and second conversion stages.
  • the first conversion stage selects first and second voltages of a plurality of reference voltages according to m most significant bits of a k bit input signal.
  • the second conversion stage precharges an output load to the first voltage selected by the first conversion stage and converting n least significant bits of the k bit input signal to a voltage between the first and second voltages.
  • the second conversion stage comprises first and second switching capacitor units connected in series, in which the first switching capacitor unit, according to a first bit of the n least significant bits, selectively charges a first capacitor to the first voltage or the second voltage and then the second switching capacitor unit performs a first charge sharing between the first capacitor and a second capacitor.
  • the first switching capacitor unit according to a second bit of the n least significant bits, selectively charges the first capacitor to the first voltage or the second voltage again and then the second switching capacitor unit performs a second charge sharing between the first capacitor and the second capacitor.
  • the invention also provides another embodiment of a system for displaying images, in which a digital-to-analog converter comprises first and second conversion stages.
  • the first conversion stage selects first and second voltages of a plurality of reference voltages according to m most significant bits of a k bit input signal, in which the first voltage is smaller that the second voltage.
  • the second conversion stage converts n least significant bits of the k bit input signal to a voltage between the first and second voltages
  • the second conversion stage comprises first and second capacitors coupled between a first node and a first power voltage and a second node and the first power voltage respectively, first switch coupled between the first voltage and the first node, second switch coupled between the second voltage and the first node, third switch coupled between the first node and the second node, and fourth switch coupled between the first voltage and the second node.
  • the first and the fourth switches are turned on to precharge the first and second capacitors to the first voltage.
  • the first and second switches are selectively turned on according to a first bit of the n least significant bits, charging the first capacitor and then the third switch is turned on such that a first charge sharing is performed between the first and the second capacitor.
  • the first and second switches are selectively turned on according to a second bit of the n least significant bits, charging the first capacitor again and then the third switch is turned on such that a second charge sharing is performed between the first and the second capacitor.
  • the invention also provides another embodiment of a system for displaying images, in which a digital-to-analog converter comprises first and second conversion stages.
  • the first conversion stage selects first and second voltages of a plurality of reference voltages according to m most significant bits of a k bit input signal.
  • the second conversion stage converting n least significant bits of the k bit input signal to a voltage between the first and second voltages, wherein the second conversion stage comprises first and second switching capacitor units and a controller.
  • the first switching capacitor unit comprises first and second switches and a first capacitor
  • the second switching capacitor unit connected to the first switching capacitor unit in series and comprises third switches and a second capacitor, and the first and second switching capacitor units precharge an output load to the first voltage during a first period.
  • the controller selectively outputs the first and second voltages to the first switching capacitor unit according to the n least significant bits.
  • the controller selectively outputs the first voltage or the second voltage according to a first bit of the n least significant bits such that the first switching capacitor unit charges a first capacitor accordingly and the second switching capacitor unit performs a first charge sharing between the first capacitor and the second capacitor.
  • the controller selectively outputs the first voltage or the second voltage again according to a second bit of the n least significant bits such that the first switching capacitor unit charges a first capacitor accordingly and the second switching capacitor unit performs a second charge sharing between the first capacitor and the second capacitor.
  • FIG. 1 shows an embodiment of a digital-to-analog converter
  • FIG. 2 shows an embodiment of a first conversion stage
  • FIG. 3 shows an embodiment of a second conversion stage
  • FIG. 4A ⁇ 4D show control timing chart of the second conversion stage under different least significant bits
  • FIG. 5 shows the relationship between resolution and height of digital-to-analog converters
  • FIG. 6 shows another embodiment of a second conversion stage
  • FIG. 7 shows an embodiment of a system for displaying images
  • FIG. 8 shows another embodiment of a system for displaying images.
  • FIG. 1 shows an embodiment of a digital-to-analog converter for a data driver in a system for display images.
  • the digital-to-analog converter (DAC) 100 comprises a reference voltage generation unit 10 and two cascaded conversion stages 20 and 30 .
  • the reference voltage generation unit 10 generates a plurality of reference voltages V 1 , V 2 , . . . , V 2 m .
  • the reference voltage generation unit 10 comprises a resistor string composed of a plurality of resistors R.
  • the first conversion stage 20 receives m most significant bits (MSBs) of a k bit parallel input signal and selects a pair of voltages from the reference voltages V 1 , V 2 , . . . , V 2 m provided by the reference voltage generation unit 10 , serving as voltages VH and VL and supplying to the second conversion stage 20 .
  • the first conversion stage 20 can be a R-matrix digital-to-analog converter shown in FIG. 2 , the R-matrix DAC comprises a plurality of transistors arranged in a matrix, and turns on two adjacent columns of transistors according to the m most significant bits (MSBs), such that two of the reference voltages V 1 , V 2 , . . . , V 2 m provided by the reference voltage generation unit 10 are selected to serves as reference voltages VH and VL.
  • the two reference voltages selected by the first conversion stage 20 have consecutive values.
  • the second conversion stage 30 receives n least significant bits (LSBs) of the k bit input signal, and performs a n-bit linear conversion in the voltage range defined by the reference voltages VH and VL to obtain an output voltage VOUT.
  • LSBs least significant bits
  • the second conversion stage 30 precharges the load C LOAD to the voltage VL provided by the first conversion stage in a precharge period, and performs charge sharing to obtain the output voltage VOUT after the precharge period according to the reference voltages VH and VL and the n least significant bits (LSBs).
  • FIG. 3 shows an embodiment of a second conversion stage.
  • the second conversion stage 30 is a switching capacitor digital-to-analog converter performing a linear DAC conversion.
  • the second conversion stage 30 comprises two switching capacitor units SCU 1 and SCU 2 connected in series, but the invention is not limited thereto, and it also can comprises three or more switching capacitor units.
  • each switching capacitor unit SCU 1 and SCU 2 comprises two switches and a capacitor.
  • the switch S 1 is coupled between the reference voltage VL and a node N 1
  • the switch S 2 is coupled between the reference voltage VH and the node N 1
  • the capacitor C 1 is coupled between the node N 1 and the power voltage GND.
  • the switch S 4 is coupled between the reference voltage VL and a node N 2
  • the switch S 3 is coupled between the nodes N 1 and N 2
  • the capacitor C 2 is coupled between the node N 2 and the power voltage GND.
  • the switches S 1 ⁇ S 4 are controlled by a timing controller 110 shown in FIG. 7 .
  • the switching capacitor unit SCU 1 selectively charges a capacitor C 1 to the voltage VL or the voltage VH and then the switching capacitor unit SCU 2 performs a first charge sharing between the capacitors C 1 and capacitor C 2 .
  • the switching capacitor units SCU 1 according to a second bit of the least significant bits, selectively charges the capacitor C 1 to the voltage VL or the voltage VH again and then the switching capacitor unit SCU 2 performs a second charge sharing between the capacitors C 1 and C 2 .
  • the voltage VC 2 is served as the output voltage VOUT.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on such that the capacitor C 1 is coupled to the reference voltage VL (22 mV) because the first bit of the least significant bits is 0.
  • the voltage VC 1 at the node N 1 is maintained at 22 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switch S 1 is turned on again such that the capacitor C 1 is coupled to the reference voltage VL (22 mV) again because the second bit of the least significant bits is 0.
  • the voltage VC 1 at the node N 1 is still maintained at 22 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is still maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 2 is turned on such that the capacitor C 1 is coupled to the reference voltage VH (23 mV) because the first bit of the least significant bits is 1.
  • the voltage VC 1 at the node N 1 is charged to 23 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switch S 1 is turned on again such that the capacitor C 1 is coupled to the reference voltage VL (22 mV) again because the second bit of the least significant bits is 0.
  • the voltage VC 1 at the node N 1 is decreased to 22 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is still maintained at 22.25 mV because the voltages VC 1 is 22 mV and the voltage VC 2 is 22.5 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on such that the capacitor C 1 is coupled to the reference voltage VL (22 mV) because the first bit of the least significant bits is 0.
  • the voltage VC 1 at the node N 1 is maintained at 22 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switch S 2 is turned on such that the capacitor C 1 is coupled to the reference voltage VH (23 mV) because the second bit of the least significant bits is 1.
  • VH 23 mV
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltages VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 2 is turned on such that the capacitor C 1 is coupled to the reference voltage VH (23 mV) because the first bit of the least significant bits is 1.
  • the voltage VC 1 at the node N 1 is charged to 23 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switch S 2 is turned on again such that the capacitor C 1 is coupled to the reference voltage VH (23 mV) again because the second bit of the least significant bits is 1.
  • VH 23 mV
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.75 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22.5 mV.
  • the second conversion stage 30 outputs 22 mV, 22.25 mV, 22.5 mV and 22.75 mV respectively, when the least significant bits are 00, 01, 10 and 11. Namely, the second conversion stage 30 can generate 2n kinds of voltages VC 2 , serving as the output voltage VOUT output to the load C LOAD , according to n least significant bits.
  • FIG. 5 shows the relationship between resolution and height of digital-to-analog converters.
  • the curve CV 1 shows the relationship between resolution and height of conventional R-digital-to-analog converter and the curve CV 2 shows the relationship between resolution and height of two stages digital-to-analog converter of the invention.
  • resolution means bit number of the k bit input signal comprising m most significant bits and n least significant bits. For example, n and m are both 2 when k is 4, m is 4 and n is 2 when k is 6, and m is 6 and n is 2 when k is 8, or m and n are both 4 when k is 8.
  • the height of the conventional R-matrix DAC is almost 8 times that of the two stages DAC in the invention.
  • the digital-to-analog converter can save more layout area as the bit number of the k bit input signal is increased.
  • FIG. 6 shows another embodiment of a second conversion stage.
  • the second conversion stage 30 ′′ is similar to the conversion stage 30 shown in FIG. 3 exception that a controller 32 .
  • the controller 32 is coupled between the reference voltages VL and VH from the first conversion stage 20 and the switching capacitor unit SCU 1 , and selectively outputs the reference voltages VL and VH to the switching capacitor unit SCU 1 according to the n least significant bits (LSBs).
  • LSBs least significant bits
  • the switches S 1 and S 4 are turned on during time t 0 ⁇ t 1
  • the switch S 2 is turned on during time t 1 ⁇ t 2
  • the switch S 3 is turned on during time t 2 ⁇ t 3
  • the switch S 2 is turned on again during time t 3 ⁇ t 4
  • the switch S 3 is turned on again during time t 4 ⁇ t 5 .
  • the reference voltages VL and VH from the first conversion stage 20 are 22 mV and 23 mV respectively.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on, and the controller 32 outputs the reference voltage VL because the first bit of the least significant bits is 0, such that the capacitor C 1 is coupled to the reference voltage VL (22 mV).
  • the voltage VC 1 at the node N 1 is charged to 22 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switch S 2 is turned on again, and the controller outputs the reference voltage VL because the second bit of the least significant bits is 1, such that the capacitor C 1 is charged by the reference voltage VL (22 mV) again.
  • the voltage VC 1 at the node N 1 is still maintained at 22 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is still maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on, and the controller 32 outputs the reference voltage VH because the first bit of the least significant bits is 1, such that the capacitor C 1 is coupled to the reference voltage VH (23 mV).
  • the voltage VC 1 at the node N 1 is charged to 23 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switch S 2 is turned on again, and the controller outputs the reference voltage VL because the second bit of the least significant bits is 1, such that the capacitor C 1 is coupled to the reference voltage VL (22 mV).
  • the voltage VC 1 at the node N 1 is decreased to 22 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is decreased to 22.25 mV because the voltage VC 1 is 22 mV and the voltage VC 2 is 22.5 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on, and the controller 32 outputs the reference voltage VL because the first bit of the least significant bits is 0, such that the capacitor C 1 is coupled to the reference voltage VL (22 mV).
  • the voltage VC 1 at the node N 1 is charged to 22 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is maintained at 22 mV because the voltages VC 1 and VC 2 are both 22 mV.
  • the switch S 2 is turned on again, and the controller outputs the reference voltage VH because the second bit of the least significant bits is 1, such that the capacitor C 1 is coupled to the reference voltage VH (23 mV).
  • the voltage VC 1 at the node N 1 is increased to 23 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switches S 1 and S 4 are turned on to precharge the capacitors C 1 and C 2 to the reference voltage VL (22 mV).
  • the switch S 1 is turned on, and the controller 32 outputs the reference voltage VH because the first bit of the least significant bits is 1, such that the capacitor C 1 is coupled to the reference voltage VH (23 mV).
  • the voltage VC 1 at the node N 1 is charged to 23 mV.
  • the switch S 3 is turned on such that a first charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.5 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22 mV.
  • the switch S 2 is turned on again, and the controller outputs the reference voltage VH because the second bit of the least significant bits is 1, such that the capacitor C 1 is coupled to the reference voltage VH (23 mV).
  • the voltage VC 1 at the node N 1 is maintained at 23 mV.
  • the switch S 3 is turned on again such that a second charge sharing is performed between the capacitors C 1 and C 2 .
  • the voltage VC 2 at the node N 2 is increased to 22.75 mV because the voltage VC 1 is 23 mV and the voltage VC 2 is 22.5 mV.
  • FIG. 7 shows an embodiment of a system for displaying images that implemented as a display panel.
  • display panel 200 comprises a gate driver 120 , a data driver 130 , a pixel array 140 and a timing controller 420 , in which data driver 130 comprises a plurality of digital-to-analog converters such as the described signal driving circuit 100 .
  • the pixel array 140 is operatively coupled to the scan driver 120 and the data driver 130 .
  • the gate driver 120 outputs a plurality of driving pulses in turn to scan display array 140
  • the data driver 130 provides data signals to drive the display array 140 .
  • the timing controller 120 provides clock signals and data signals to the gate driver 120 and the data driver 130 .
  • the switches S 1 ⁇ S 4 and the controller 32 shown in FIG. 3 and FIG. 6 are controlled by the timing controller 110 .
  • FIG. 8 schematically shows another embodiment of a system for displaying images, implemented here as an electronic device 300 , comprising a display panel, such as display panel 200 , which can be a plasma display panel, an organic light emitting display panel, or a cathode ray tube display panel in other embodiments, but is not limited thereto.
  • the electronic device 300 may be a digital camera, a portable DVD, a television, a car display, a PDA, notebook computer, tablet computer, cellular phone, or a display device, etc.
  • the electronic device 300 includes a housing 210 , the display panel 200 and a DC/DC converter 220 .
  • the DC/DC converter 220 is operatively coupled to the display panel 200 and provides an output voltage powering the display panel 200 to display images.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Analogue/Digital Conversion (AREA)
  • Control Of El Displays (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
US11/464,237 2006-08-14 2006-08-14 System for displaying images Expired - Fee Related US7286071B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/464,237 US7286071B1 (en) 2006-08-14 2006-08-14 System for displaying images
TW096127291A TWI365432B (en) 2006-08-14 2007-07-26 Systems for displaying images
JP2007211347A JP2008046639A (ja) 2006-08-14 2007-08-14 イメージ表示システム
CN2007101436022A CN101127184B (zh) 2006-08-14 2007-08-14 数字模拟转换器以及包括数字模拟转换器的影像显示系统

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080309538A1 (en) * 2005-11-05 2008-12-18 Chang Il-Kwon Digital/analog converting driver and method
US20110199248A1 (en) * 2010-02-12 2011-08-18 Silicon Works Co., Ltd Digital-To-Analog Converter Of Data Driver And Converting Method Thereof
CN103700343A (zh) * 2013-12-20 2014-04-02 四川虹视显示技术有限公司 Amoled像素驱动电路及方法
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
CN109565243A (zh) * 2016-08-05 2019-04-02 香港大学 高效率的开关电容器电源和方法
US11323127B2 (en) * 2018-05-09 2022-05-03 Boe Technology Group Co., Ltd. Digital-to-analog conversion circuit and method, and display device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102436791B (zh) * 2012-01-18 2013-11-06 旭曜科技股份有限公司 用于显示面板的控制装置及控制方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6556162B2 (en) * 2000-05-09 2003-04-29 Sharp Kabushiki Kaisha Digital-to-analog converter and active matrix liquid crystal display

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3852721B2 (ja) * 1997-07-31 2006-12-06 旭化成マイクロシステム株式会社 Ｄ／ａ変換器およびデルタシグマ型ｄ／ａ変換器
GB9724739D0 (en) * 1997-11-25 1998-01-21 Philips Electronics Nv Digital to analogue converter and method of operating the same
US6130635A (en) * 1998-08-03 2000-10-10 Motorola Inc. Method of converting an analog signal in an A/D converter utilizing RDAC precharging
JP3564347B2 (ja) * 1999-02-19 2004-09-08 株式会社東芝 表示装置の駆動回路及び液晶表示装置
CN1251167C (zh) * 2000-09-11 2006-04-12 皇家菲利浦电子有限公司 矩阵显示装置
KR100506005B1 (ko) * 2002-12-31 2005-08-04 엘지.필립스 엘시디 주식회사 평판표시장치
KR100588745B1 (ko) * 2004-07-30 2006-06-12 매그나칩 반도체 유한회사 액정표시장치의 소스 드라이버
JP4676183B2 (ja) * 2004-09-24 2011-04-27 パナソニック株式会社 階調電圧生成装置，液晶駆動装置，液晶表示装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6556162B2 (en) * 2000-05-09 2003-04-29 Sharp Kabushiki Kaisha Digital-to-analog converter and active matrix liquid crystal display

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080309538A1 (en) * 2005-11-05 2008-12-18 Chang Il-Kwon Digital/analog converting driver and method
US7609191B2 (en) * 2005-11-05 2009-10-27 Samsung Electronics Co., Ltd. Digital/analog converting driver and method
US20110199248A1 (en) * 2010-02-12 2011-08-18 Silicon Works Co., Ltd Digital-To-Analog Converter Of Data Driver And Converting Method Thereof
US8325075B2 (en) * 2010-02-12 2012-12-04 Silicon Works Co., Ltd. Digital-to-analog converter of data driver and converting method thereof
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
CN103700343A (zh) * 2013-12-20 2014-04-02 四川虹视显示技术有限公司 Amoled像素驱动电路及方法
CN103700343B (zh) * 2013-12-20 2017-01-04 四川虹视显示技术有限公司 Amoled像素驱动电路及方法
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
CN109565243A (zh) * 2016-08-05 2019-04-02 香港大学 高效率的开关电容器电源和方法
US11323127B2 (en) * 2018-05-09 2022-05-03 Boe Technology Group Co., Ltd. Digital-to-analog conversion circuit and method, and display device

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CN101127184A (zh) 2008-02-20

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