US6978362B2 - Reset arrangement for a microcontroller - Google Patents

Reset arrangement for a microcontroller Download PDF

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Publication number
US6978362B2
US6978362B2 US10/135,351 US13535102A US6978362B2 US 6978362 B2 US6978362 B2 US 6978362B2 US 13535102 A US13535102 A US 13535102A US 6978362 B2 US6978362 B2 US 6978362B2
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Prior art keywords
reset
microcontroller
arrangement
reset signal
res
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US20020166044A1 (en
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Matthias Muth
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Samsung Electronics Co Ltd
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Koninklijke Philips Electronics NV
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NXP B.V.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • the invention relates to a reset arrangement for a microcontroller and/or one or more hardware circuits.
  • the object of such a reset arrangement is to reset the microcontroller and/or the hardware circuits after a system cold start and/or after a cold or hot start.
  • a system cold start is concerned when the reset arrangement and the microcontroller are currentless and must be powered for the first time.
  • a hot start is concerned when the microcontroller has already been fed with a power supply voltage and the microcontroller is to be reset.
  • this object is solved by the characteristic features defined in claim 1 .
  • a reset arrangement for a microcontroller and/or one or more hardware circuits wherein the reset arrangement
  • the reset arrangement After a system cold start, i.e. when the power supply voltage is switched on for the first time after a powerless state, the reset arrangement supplies a first reset signal.
  • the duration of this reset signal is chosen to be such that a microcontroller and/or other hardware circuits are reliably reset.
  • the duration of this first reset signal may be adapted, for example, to different possible types of microcontrollers and different types of hardware circuits with which the reset arrangement can be combined.
  • the duration of this first reset signal may also be chosen to be relatively long so as to comply with all possible requirements.
  • the reset arrangement When the system cold start is successful, the reset arrangement is programmed with a second reset signal by means of the microcontroller, i.e. the reset arrangement receives a second reset signal whose duration is adapted to the requirements of the microcontroller and/or the hardware circuits which are also to be reset.
  • This second reset signal can therefore be individually adapted to the microcontroller and the actual circuits and may therefore be shorter or even clearly shorter than the first reset signal.
  • the reset arrangement utilizes the second, programmed reset signal with the possibly shorter duration for these hot starts and the required reset procedures.
  • this has the advantage that a shorter reset procedure is possible for cold and hot starts as compared with system cold starts.
  • the duration of this reset procedure is only as long as is required for the actually provided microcontroller and the possible hardware circuits to be reset.
  • the reset arrangement since the length of the reset procedure performed upon a cold or a hot start is programmable, i.e. selectable, the reset arrangement may be used in the same construction for different types of microcontrollers and possibly different hardware circuits which are also to be reset, without the reset arrangement itself requiring any adaptation.
  • the adaptation to these circuits is rather realized by the adapted length of the second programmed reset signal.
  • the reset arrangement is provided on a system chip.
  • analog circuit components and components for power supply required for use with a microcontroller are integrated in such a system chip. This provides the possibility of monitoring the microcontroller completely independently by means of such a system chip.
  • the integration of this arrangement in such a system chip is advantageous because the system chip itself already initiates, for example, switching of the power supply voltage and the relevant information is provided anyway.
  • the second programmed reset signal has a shorter duration than the first reset signal. As already mentioned above, this is generally the case and particularly advantageous because the cold or hot start can be chosen to be shorter in this way than the cold start. Nevertheless, due to the adapted duration of the second programmed reset signal, an optimized procedure takes place for the microcontroller and/or the hardware.
  • safety mechanisms may be advantageously provided, which perform a reset with the first length of the reset signal when a reset with the length of the second reset signal fails.
  • a reset with the second duration of the reset signal fails, a further reset with the mostly longer duration of the first reset signal can therefore be performed for the sake of safety.
  • the microcontroller is switched to a currentless state by switching off the power supply voltage and is set in this way to a low-power error mode. This is sensible because it can be assumed in such a case that there is an error in the microcontroller. Unnecessary current consumption is avoided because the microcontroller is now currentless.
  • the microcontroller After a reset procedure, the microcontroller must normally release the reset lines after a predetermined period of time, i.e. the potential provided on the reset line for a reset must be replaced by the “free state” of the reset line again after this predetermined period of time. If this is not the case, either the microcontroller has not ended the reset procedure in accordance with the prescriptions or the reset line itself is clamped at a different potential. In both cases, there is an erroneous state which can be advantageously monitored by the reset arrangement as defined in claim 6 and which state is ended by the reset arrangement in that it switches the microcontroller to a currentless state and thus minimizes the current consumption.
  • the reset arrangement may be advantageously constituted in such a way that it is always capable of setting the microcontroller to a low-power mode, even without any errors in the operative state. This may be advantageous when the microcontroller can be put out of operation for a foreseeable period of time.
  • the microcontroller is triggered by the reset arrangement waking up the microcontroller from its low-power mode after the occurrence of an internal or external wake-up event.
  • waking up may take place in this manner both when switching to the low-power mode as defined in claim 7 and in the states in which the microcontroller was set to a low-power error mode after the occurrence of an error.
  • FIG. 1 is a block diagram of a reset arrangement according to the invention in a system chip, and of a microcontroller to be reset, and
  • FIG. 2 is a flow chart of the reset arrangement shown in FIG. 1 .
  • FIG. 1 is a block diagram of a system chip 1 comprising a reset arrangement according to the invention (not shown in FIG. 1 ).
  • a part of the system chip 1 is indicated within the broken-line square. This part comprises a power supply circuit 2 which supplies a power supply voltage VCC to a microcontroller 3 , which is also shown diagrammatically in the Figure and is capable of switching this power supply voltage.
  • the part of the system chip 1 comprising the power supply circuit 2 is shown in broken lines because the power supply circuit 2 may also be arranged outside the system chip 1 .
  • the power supply voltage of the overall system shown in FIG. 1 may be realized, for example, by means of a battery which supplies a power supply voltage BAT to the system chip 1 and the power supply circuit 2 .
  • the power supply circuit 2 may, for example, control this voltage but particularly also switch it on and off.
  • the power supply voltage VCC mentioned hereinbefore is applied, inter alia, to the microcontroller 3 but may also be applied to further hardware components which are not shown in FIG. 1 .
  • the power supply circuit 2 is controlled by means of the system chip 1 and the reset arrangement according to the invention, provided in this chip.
  • a reset line Res is provided by means of which the reset arrangement is capable of triggering the microcontroller 3 .
  • the state of the reset line Res is monitored by the reset arrangement provided in the system chip 1 .
  • a control connection of one or several bits wide is provided, which is denoted by Con in the Figure and allows a reciprocal control between the system chip 1 and the reset arrangement in this chip, on the one hand, and the microcontroller 3 , on the other hand.
  • the reset arrangement in the system chip 1 has the object of resetting the microcontroller 3 . Basically, this may be necessary under two circumstances. On the one hand, there may be a system cold start. In a system cold start, the microcontroller 3 initially does not receive any power supply voltage VCC, i.e. the microcontroller 3 is voltageless and inactive. After the power supply voltage VCC is supplied for the first time by means of the power supply circuit 2 , the microcontroller 3 may be in an undefined state. Therefore, a reset procedure is required after supply of the power supply voltage.
  • the reset arrangement in the system chip 1 supplies a reset signal on the reset line Res in this case, which reset signal has a first length which is dimensioned in such a way that, independent of the type of the microcontroller 3 , a safe reset procedure takes place in any case, because, at this instant, it is not yet known to the system chip 1 which type of microcontroller 3 or other hardware is connected.
  • the duration of this first reset signal is thus dimensioned to be relatively long so as to guarantee a safe reset of the microcontroller 3 under all circumstances.
  • cold starts may take place in which the power supply VCC is switched on again after it was previously switched off, for example, for the purpose of saving current. Furthermore, however, reset procedures may be required or desirable also in the operating phase in which the microcontroller 3 already receives the power supply voltage VCC. This situation relates to hot starts.
  • the reset arrangement uses a second, programmed reset signal of a shorter duration which is also supplied to the microcontroller 3 via the reset line Res and whose length is individually adapted to the requirements of the microcontroller 3 and possibly further circuit elements, which are not shown in FIG. 1 but are also to be reset.
  • the microcontroller 3 supplies a signal via the control lines CON after a successful system cold start, which signal is received by the reset arrangement in the system chip 1 and indicates the duration of a second, programmed reset signal. After this programming procedure, each cold or hot start is performed—as elucidated above—with this optimized length of the second, programmed reset signal.
  • the microcontroller 3 can be set to a low-power mode by switching off the power supply voltage VCC. This saves energy. If the microcontroller 3 is to be reactivated from this state, the reset arrangement according to the invention in the system chip 1 receives an external wake-up signal via a line WU. When this signal appears, the reset arrangement supplies a corresponding signal to the power supply circuit 2 which thereupon switches on the power supply voltage VCC again. Furthermore, the reset arrangement performs a system cold start reset, i.e. a reset by means of the first reset signal, because there were apparently previous reset failures.
  • a system cold start reset i.e. a reset by means of the first reset signal
  • the arrow A in FIG. 2 indicates the system state in which the overall system or at least the microcontroller 3 was initially in a powerless state but in which now the power supply voltages BAT and VCC are switched on. As is indicated by the state Res 1 in FIG. 2 , the microcontroller is then reset by means of the first reset signal.
  • the length of the second reset signal is supplied to the reset arrangement, as is indicated by arrow B.
  • Subsequent reset procedures in which cold or hot starts are concerned are then performed by means of the second reset. This is indicated by the second state Res 2 in FIG. 2 .
  • the microcontroller 3 of FIG. 1 releases the reset line after a predetermined period of time. If, for example, a high potential is provided for a reset signal on the reset line, the reset line must change to the low potential again after this predetermined period of time.
  • the reset arrangement in the chip 1 of FIG. 1 sets the microcontroller 3 to a low-power error mode with VCC switched off, which is denoted by the block LPM 2 in the Figure.
  • the monitoring of these two states and the transition to this mode is indicated by means of the arrow F in FIG. 2 .
  • the system can be woken up from the low-power error mode LPM 2 by means of the reset arrangement according to the invention.
  • a wake-up signal is supplied to the reset arrangement via the wake-up line WU of the circuit of FIG. 1 , which reset arrangement triggers a switch-on of the power supply voltage by means of the power supply circuit 2 and triggers a system cold start reset with the duration of the first reset signal.
  • the reset arrangement according to the invention is also used for this purpose; as required, for example, by means of control software, the microcontroller 3 may supply a corresponding signal via the control connection CON to the reset arrangement in the system chip 1 , whereupon this arrangement switches the power supply circuit 2 in such a way that the power supply voltage VCC of the microcontroller 3 is switched off.
  • This is indicated in FIG. 2 by the arrow D and the block LPM 1 which is the low-power mode.
  • This low-power mode is also triggered by a signal on the line WU of the circuit of FIG. 1 so that the power supply voltage VCC is switched on again and connected to a reset signal having the duration of the second programmed reset signal. This is indicated by arrow E in FIG. 2 .
  • the arrangement according to the invention may also be adapted individually to the actual conditions by the variable length of the second programmed reset signal. Moreover, it is possible to monitor the reset procedure and, dependent on the error condition, it can reset the microcontroller either with the programmed reset signal of the second duration or reset it again but this time with a reset signal of the first duration. Moreover, it is possible to set the microcontroller to the low-power mode even when the error condition is not eliminated after a further reset procedure with the first length of the reset signal.
  • the reset arrangement according to the invention also provides an optimum monitoring of this microcontroller and a saving of energy in the case of an error that cannot be eliminated, which saving of energy is obtained by setting the microcontroller 3 to a low-power mode LPM 2 .

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Microcomputers (AREA)
  • Retry When Errors Occur (AREA)
US10/135,351 2001-05-05 2002-04-30 Reset arrangement for a microcontroller Expired - Lifetime US6978362B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10121935.0 2001-05-05
DE10121935A DE10121935A1 (de) 2001-05-05 2001-05-05 Rücksetz-Anordnung für einen Mikrokontroller

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US20020166044A1 US20020166044A1 (en) 2002-11-07
US6978362B2 true US6978362B2 (en) 2005-12-20

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EP (1) EP1255182A3 (enExample)
JP (1) JP4090782B2 (enExample)
DE (1) DE10121935A1 (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080155291A1 (en) * 2006-12-26 2008-06-26 Holtek Semiconductor Inc. Method for resetting micro controller
US20090204834A1 (en) * 2008-02-11 2009-08-13 Nvidia Corporation System and method for using inputs as wake signals
US20090256534A1 (en) * 2008-04-14 2009-10-15 Twisthink, L.L.C. Power supply control method and apparatus
US9104423B2 (en) 2012-05-16 2015-08-11 Nvidia Corporation Method and system for advance wakeup from low-power sleep states
US9395799B2 (en) 2012-08-09 2016-07-19 Nvidia Corporation Power management techniques for USB interfaces
US9474022B2 (en) 2012-11-30 2016-10-18 Nvidia Corporation Saving power in a mobile terminal
US9760150B2 (en) 2012-11-27 2017-09-12 Nvidia Corporation Low-power states for a computer system with integrated baseband

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10252583B3 (de) * 2002-11-12 2004-04-01 Siemens Ag Anordnung und Verfahren zur Fehlerüberwachung von Grafiktreiberbausteinen
US7702885B2 (en) * 2006-03-02 2010-04-20 Atmel Corporation Firmware extendable commands including a test mode command for a microcontroller-based flash memory controller
US7483316B2 (en) * 2007-04-24 2009-01-27 Macronix International Co., Ltd. Method and apparatus for refreshing programmable resistive memory
US10126724B2 (en) * 2016-03-07 2018-11-13 Haier Us Appliance Solutions, Inc. Low power management system
TWI591538B (zh) * 2017-01-18 2017-07-11 新唐科技股份有限公司 微控制器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233613A (en) * 1988-03-29 1993-08-03 Advanced Micro Devices, Inc. Reliable watchdog timer
US5463336A (en) * 1994-01-27 1995-10-31 Rockwell International Corporation Supply sensing power-on reset circuit
US5513319A (en) * 1993-07-02 1996-04-30 Dell Usa, L.P. Watchdog timer for computer system reset
US5528749A (en) * 1994-08-05 1996-06-18 Thomson Consumer Electronics, Inc. Automatic instrument turn off/on for error correction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233613A (en) * 1988-03-29 1993-08-03 Advanced Micro Devices, Inc. Reliable watchdog timer
US5513319A (en) * 1993-07-02 1996-04-30 Dell Usa, L.P. Watchdog timer for computer system reset
US5463336A (en) * 1994-01-27 1995-10-31 Rockwell International Corporation Supply sensing power-on reset circuit
US5528749A (en) * 1994-08-05 1996-06-18 Thomson Consumer Electronics, Inc. Automatic instrument turn off/on for error correction

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080155291A1 (en) * 2006-12-26 2008-06-26 Holtek Semiconductor Inc. Method for resetting micro controller
US20090204834A1 (en) * 2008-02-11 2009-08-13 Nvidia Corporation System and method for using inputs as wake signals
US20090256534A1 (en) * 2008-04-14 2009-10-15 Twisthink, L.L.C. Power supply control method and apparatus
US9104423B2 (en) 2012-05-16 2015-08-11 Nvidia Corporation Method and system for advance wakeup from low-power sleep states
US9395799B2 (en) 2012-08-09 2016-07-19 Nvidia Corporation Power management techniques for USB interfaces
US9760150B2 (en) 2012-11-27 2017-09-12 Nvidia Corporation Low-power states for a computer system with integrated baseband
US9474022B2 (en) 2012-11-30 2016-10-18 Nvidia Corporation Saving power in a mobile terminal

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Publication number Publication date
DE10121935A1 (de) 2002-11-07
JP4090782B2 (ja) 2008-05-28
JP2003029881A (ja) 2003-01-31
EP1255182A2 (de) 2002-11-06
US20020166044A1 (en) 2002-11-07
EP1255182A3 (de) 2009-06-24

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