US6281046B1 - Method of forming an integrated circuit package at a wafer level - Google Patents

Method of forming an integrated circuit package at a wafer level Download PDF

Info

Publication number
US6281046B1
US6281046B1 US09/558,396 US55839600A US6281046B1 US 6281046 B1 US6281046 B1 US 6281046B1 US 55839600 A US55839600 A US 55839600A US 6281046 B1 US6281046 B1 US 6281046B1
Authority
US
United States
Prior art keywords
wafer
bonding pads
interposer substrate
underfill
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US09/558,396
Inventor
Ken M. Lam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to US09/558,396 priority Critical patent/US6281046B1/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAM, KEN M.
Priority to HK03105947.0A priority patent/HK1053746B/en
Priority to AU2001249879A priority patent/AU2001249879A1/en
Priority to JP2001579352A priority patent/JP2003532294A/en
Priority to PCT/US2001/011035 priority patent/WO2001082361A2/en
Priority to CA002402082A priority patent/CA2402082A1/en
Priority to KR1020027013911A priority patent/KR20040004761A/en
Priority to CNB018084257A priority patent/CN1181524C/en
Priority to EP01923160A priority patent/EP1279193A2/en
Priority to MYPI20011821A priority patent/MY134243A/en
Priority to TW090109512A priority patent/TW503486B/en
Publication of US6281046B1 publication Critical patent/US6281046B1/en
Application granted granted Critical
Priority to NO20024196A priority patent/NO20024196L/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates generally to integrated circuit packages, and more specifically to a method of forming a ball-grid array integrated package at a wafer level.
  • the footprint of an integrated circuit package on a circuit board is the area of the board occupied by the package. It is generally desired to minimize the footprint and to place packages close together.
  • the ball-grid array (BGA) package has emerged as one of the more popular package types because it provides high density, minimum footprint, and shorter electrical paths, which means that it has better performance than previous types of semiconductor packages.
  • FIG. 10 A typical BGA package is shown in FIG. 10 .
  • an integrated circuit chip 122 is mounted by means of a bonding layer on an upper surface of a base 112 made of a substrate material.
  • Metal bonding wires or wirebond leads 120 electrically connect a plurality of metal chip pads 126 formed on the upper surface of the chip 122 with wire bonding pads 128 formed on the upper surface of the base 112 .
  • the base 112 includes plated through-hole vias 118 and metal traces 114 to connect the circuitry from the upper surface to the lower surface of the base 112 .
  • a plurality of solder balls 116 are placed on the bottom surface of the base 112 and are electrically connected to the metal traces 114 of the base.
  • the solder balls 116 can be arranged in a uniform full matrix array over the entire bottom surface, in a staggered full array, or around the perimeter of the bottom surface in multiple rows. The solder balls are then used to mechanically and electrically secure the chip package onto a printed circuit board in the end-use product.
  • the BGA packages of the prior art provide a great improvement over earlier types of packages in terms of high density and high I/O capability, it is always desired to make the IC package even smaller to further decrease the amount of space needed on a printed circuit board to accommodate the package. Because the wirebond leads are of a predetermined length and require a minimum spacing between adjacent bonding sites to provide sufficient room for the bonding tool, the substrate base must be larger than the chip and it is not possible to fabricate a more compact package. Ideally, it is desired to make a package in which the substrate base does not have to be any larger than the size of the chip.
  • Some examples of packaging methods in the prior art that are conducted at the wafer level include: U.S. Pat. No. 5,604,160 to Warfield, which discloses using a cap wafer to package semiconductor devices on a device wafer; U.S. Pat. No. 5,798,557 to Salatino et al., which describes a wafer level hermetically packaged integrated circuit having a protective cover wafer bonded to a semiconductor device substrate wafer; and U.S. Pat. No.
  • the above objects have been achieved in a method of forming an integrated circuit package on the wafer level using a flip chip design with a single wafer.
  • the integrated circuit package is formed by first providing a product silicon wafer having a plurality of microelectric circuits fabricated thereon and having a plurality of standard aluminum bonding pads exposed. The aluminum bonding pads are re-metallized to be solderable. Then, a plurality of solder bumps are deposited on the bonding pad sites. Then, a layer of underfill-flux material is deposited onto the wafer surface, over the solder bumps.
  • a pre-fabricated interposer substrate, having metallized through-holes, is aligned to the wafer and then the assembly is reflowed, or cured, to secure the interposer substrate to the layer of underfill-flux material, and to form the electrical connection between the circuitry on the substrate and the bonding pads on the silicon wafer.
  • Solder balls are then placed on the metal pad openings on the interposer substrate and are then reflowed forming a BGA structure.
  • the wafer is then diced and the individual BGA packages are formed. The BGA package is ready for the next level assembly.
  • the integrated circuit package of the present invention is smaller than BGA packages of the prior art in that the additional space usually required because of the use of wirebonding leads is not necessary.
  • the whole wafer can be packaged all at one time which is more efficient than packaging each die individually and allows for parallel testing of the packaged dice while still in wafer form.
  • the method of the present invention is easy to implement because, since the solder bumps are defined first, there is no need to be concerned with keeping the bonding pads clean for later addition of solder during the step of adding the adhesive (underfill-flux) layer. Also, since the solder bumps are already in place, it makes it easier to align the solder bumps to the plated through-holes of the interposer substrate.
  • FIG. 1 is a perspective view of a silicon wafer having a plurality of chips formed on a top surface.
  • FIG. 2 is a cross-sectional view of a section 2 — 2 of the silicon wafer shown in FIG. 1 with the bonding pads re-metallized.
  • FIGS. 3-7 are cross-sectional views of the silicon wafer of FIG. 1 showing the various process steps used in forming the IC package of the present invention.
  • FIG. 8 is a cross-sectional view of the silicon wafer of FIG. 1, showing the finalized wafer assembly for the IC package of the present invention.
  • FIG. 9 is a cross-sectional view of the finalized IC package of the present invention.
  • FIG. 10 is a cross-sectional view of a ball-grid array package as known in the prior art.
  • a silicon wafer 21 has a plurality of microcircuits fabricated thereon.
  • the microcircuits are arranged into a matrix of individual chips or dice 24 , 25 .
  • a plurality of aluminum bonding pads 23 are arranged around the perimeter of each of the chips.
  • the wafer 21 is usually diced at this point into individual chips, and each of the individual chip is then packaged.
  • the chips are formed on the wafer but are not diced until the packaging operation on the wafer has been completed, thus the packaging of the chip is conducted at the wafer level.
  • the first step in the packaging process is to re-metallize the aluminum bonding pads 23 in order to make the bonding pads solderable.
  • Aluminum which is commonly used for the wirebond pads of IC's, is a less than ideal metal for use in solder connections due to the fact that the aluminum tends to oxidize which creates solder wetting problems.
  • the aluminum bonding pads need to be wetable by solder or have a low ohmic contact resistance for application of a conductive adhesive. Therefore, the bonding pads need to be re-metallized.
  • One process for re-metallizing the bonding pads is to use electroless nickel-gold plating.
  • a layer of zinc 17 is deposited on the aluminum bonding pads 23 , then a layer of electroless nickel plating 18 is deposited on the layer of zinc.
  • the zinc layer 17 acts as an adhesion layer between the nickel plating 18 and the aluminum bond pads 23 .
  • a layer of electroless gold plating 19 is deposited on top of the electroless nickel plating 18 to form a nickel-gold plating in order to make the bonding pads 23 conducive to soldering.
  • another thin film metallization scheme can be carried out to re-metallize the bonding pads.
  • solder bumps 30 are deposited on the wirebond pad sites 23 .
  • This can be carried out by a screen or stencil printing process.
  • the surface of the wafer 21 is screened off and the solder paste is deposited onto the bonding pads 23 by a pneumatic squeegee so that the solder paste is deposited on the wafer all at one time.
  • the solder paste can also be deposited on the bonding pads by the use of automatic dispensing equipment or by solder preform placement.
  • the solder can be electrolytically plated or evaporated onto the wafer.
  • the wafer is processed through solder reflow equipment, such as a solder reflow furnace, to form the solder bumps 30 .
  • Another alternative is to use an electrically conductive adhesive, in lieu of the solder paste.
  • the adhesive can be made of an underfill-flux material.
  • the underfill-flux material has two functions. Firstly, it acts as a flux to clean metallic oxide from the solder and the soldering surface. Secondly, the underfill-flux material acts as an adhesive and a sealant.
  • the adhesive layer 27 can be applied through a screen printing process in which the underfill-flux material is pushed through the openings of a stencil or a mesh screen. The screen is mounted onto a screen printer and is precisely positioned with respect to the wafer.
  • a certain amount of the underfill-flux material is dispensed along one edge of the screen and a pneumatic squeegee presses down on the screen as it sweeps across it, sheering the material at a constant pressure.
  • the material acquires higher flowability above certain shear stresses, which allows it to go through the screen and fill the gaps left by the wire mesh of the screen.
  • the area above the bonding pads 23 does not need to be blocked because the solder bumps are already defined and because the underfill-flux material also acts as a solder flux.
  • the screen is removed and a uniform layer of the material is formed on top of the wafer.
  • a B-staged underfill-flux preform can be used to bond the wafer 21 to the backside of an interposer substrate layer.
  • the underfill-flux layer when cured, acts as an encapsulant, providing environmental protection for the wafer.
  • the underfill-flux also acts as a buffer layer for the wafer 21 from external stresses, such as a thermal coefficient of expansion mismatch between the wafer and the package solder balls used for mounting the IC package, or a mismatch between the wafer and an end-use printed circuit board on which the IC package would be mounted.
  • an interposer substrate layer 31 with plated through-holes is then aligned to the solder bumps 30 over the underfill-flux layer 27 and will be secured to the underfill-flux layer 27 and solder bumps 30 to form a wafer/interposer assembly 39 .
  • the interposer substrate 31 is a preformed substrate consisting of metal circuitry 34 and a dielectric base 32 .
  • the metal circuitry 34 typically consists of copper traces formed throughout the substrate.
  • the interposer substrate 31 can also include solder resist coatings to help define solder wetable areas on the copper metal circuitry.
  • the metal circuitry 34 can be formed on a single layer or on multiple layers of the interposer substrate 31 .
  • the copper metal circuitry can be nickel-gold plated or coated by an organic material which is used to preserve the copper from oxidation.
  • the dielectric base material 32 is typically made of a polyamide base substrate. Alternatively, BT resin and other epoxy-glass substrates can also be used as the dielectric base material 32 .
  • a key feature of the interposer substrate 31 is a plurality of openings 38 on the metal circuitry 34 .
  • the metal circuitry 34 generally serves as interconnect circuitry, as the traces can be routed throughout the substrate to interconnect the circuits from the various bonding pads 23 to the Input/Output (I/O) interconnects which will be added to the wafer/interposer assembly 39 through the plurality of openings 38 , as described later with reference to FIG. 8 .
  • the interposer substrate 31 can be approximately the same size as the wafer 21 and is aligned to the wafer 21 such that the through-holes 36 line up with the bonding pads 23 .
  • a sufficient amount of copper must be present in the through-holes 36 to provide adequate connection for solder or for a conductive adhesive.
  • a circular copper ring around the through-holes 36 or a copper strip across the through-holes 36 can be used to facilitate this requirement.
  • the interposer substrate 31 is then adhered to the wafer 21 by the underfill-flux material 27 and the wafer/interposer assembly 39 is then cured.
  • the interposer is aligned and bonded to the wafer.
  • an epoxy coating material 42 can be used to protect the solder connections.
  • Application of the epoxy coating material 42 would also be by the screen or stencil printing process described above and the protective coating would then be cured.
  • the next step is to place package solder balls on the wafer/interposer assembly.
  • the package solder balls serve as the I/O interconnects for the final IC package and will be used to secure the completed IC package to an end-use printed circuit board.
  • the solder balls 50 are placed on the plurality of openings 38 through a mechanical transfer of pre-formed solder balls and then are reflowed onto the metallized openings.
  • the solder balls 50 can be formed by screen or stencil printing solder paste. The solder is then reflowed to form the package solder balls.
  • solder balls 50 are applied in whatever type of pattern is desired, such as in a uniform full matrix over the entire surface.
  • the wafer/interposer assembly 39 contains finished dice arranged in a matrix format. This allows for parallel testing, which can be conducted at the wafer level and can provide savings in testing time and cost. Then the wafer/interposer assembly 39 is diced, or singulated, such as along line 60 , to form individual chip-size BGA packages 70 , 72 . A common technique for the singulation is to use a wafer saw with diamond or resinoid saw blades. With reference to FIG. 9, the finished BGA package 70 can then be mounted on the end-use printed circuit board in the same manner as prior art BGA packages.
  • the BGA package 70 of the present invention has the same footprint as the individual silicon die, as no extra space is needed to accommodate wirebond leads or larger substrate bases. In this way, the integrated circuit package of the present invention provides the advantages of a smaller package size and the convenience of packaging at the wafer level.

Landscapes

  • Wire Bonding (AREA)

Abstract

A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps, or conductive adhesive, is deposited on the metallized wirebond pads on the top surface of a silicon wafer. An underfill-flux material is deposited over the wafer and the solder bumps. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized through-holes which are aligned with the solder bumps. The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to U.S. patent application Ser. No. 09/460,902, filed Dec. 14, 1999.
TECHNICAL FIELD
The invention relates generally to integrated circuit packages, and more specifically to a method of forming a ball-grid array integrated package at a wafer level.
BACKGROUND ART
The footprint of an integrated circuit package on a circuit board is the area of the board occupied by the package. It is generally desired to minimize the footprint and to place packages close together. In recent years, the ball-grid array (BGA) package has emerged as one of the more popular package types because it provides high density, minimum footprint, and shorter electrical paths, which means that it has better performance than previous types of semiconductor packages.
A typical BGA package is shown in FIG. 10. In the BGA package 110, an integrated circuit chip 122 is mounted by means of a bonding layer on an upper surface of a base 112 made of a substrate material. Metal bonding wires or wirebond leads 120 electrically connect a plurality of metal chip pads 126 formed on the upper surface of the chip 122 with wire bonding pads 128 formed on the upper surface of the base 112. The base 112 includes plated through-hole vias 118 and metal traces 114 to connect the circuitry from the upper surface to the lower surface of the base 112. A plurality of solder balls 116 are placed on the bottom surface of the base 112 and are electrically connected to the metal traces 114 of the base. The solder balls 116 can be arranged in a uniform full matrix array over the entire bottom surface, in a staggered full array, or around the perimeter of the bottom surface in multiple rows. The solder balls are then used to mechanically and electrically secure the chip package onto a printed circuit board in the end-use product.
While the BGA packages of the prior art provide a great improvement over earlier types of packages in terms of high density and high I/O capability, it is always desired to make the IC package even smaller to further decrease the amount of space needed on a printed circuit board to accommodate the package. Because the wirebond leads are of a predetermined length and require a minimum spacing between adjacent bonding sites to provide sufficient room for the bonding tool, the substrate base must be larger than the chip and it is not possible to fabricate a more compact package. Ideally, it is desired to make a package in which the substrate base does not have to be any larger than the size of the chip.
In the prior art, as described above, it is common to fabricate a package for each individual die. Others have realized that it would be advantageous to be able to form the IC package at the wafer level, that is, after the individual chips have been formed on the wafer but before the wafer has been diced into individual chips. This allows for easier mass production of chip packages and for several chip packages, arranged in a matrix format on the wafer, to be manufactured and tested all at one time. This can reduce time and cost in the process of packaging and testing IC chips.
Some examples of packaging methods in the prior art that are conducted at the wafer level include: U.S. Pat. No. 5,604,160 to Warfield, which discloses using a cap wafer to package semiconductor devices on a device wafer; U.S. Pat. No. 5,798,557 to Salatino et al., which describes a wafer level hermetically packaged integrated circuit having a protective cover wafer bonded to a semiconductor device substrate wafer; and U.S. Pat. No. 5,851,845 to Wood et al., which discloses a method of forming a semiconductor package by providing a wafer containing a plurality of dice, thinning a backside of the wafer by polishing or etching, attaching the thinned wafer to a substrate, and then dicing the wafer.
It is the object of the present invention to provide a ball-grid array IC package that has a minimum size such that the IC package takes up no more space than the area of the IC chip.
It is a further object of the invention to provide a method of forming such an IC package at the wafer level in order to take advantage of the greater efficiency in mass production and the ability to conduct parallel testing of the IC packages.
SUMMARY OF THE INVENTION
The above objects have been achieved in a method of forming an integrated circuit package on the wafer level using a flip chip design with a single wafer. The integrated circuit package is formed by first providing a product silicon wafer having a plurality of microelectric circuits fabricated thereon and having a plurality of standard aluminum bonding pads exposed. The aluminum bonding pads are re-metallized to be solderable. Then, a plurality of solder bumps are deposited on the bonding pad sites. Then, a layer of underfill-flux material is deposited onto the wafer surface, over the solder bumps. A pre-fabricated interposer substrate, having metallized through-holes, is aligned to the wafer and then the assembly is reflowed, or cured, to secure the interposer substrate to the layer of underfill-flux material, and to form the electrical connection between the circuitry on the substrate and the bonding pads on the silicon wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are then reflowed forming a BGA structure. The wafer is then diced and the individual BGA packages are formed. The BGA package is ready for the next level assembly.
The integrated circuit package of the present invention is smaller than BGA packages of the prior art in that the additional space usually required because of the use of wirebonding leads is not necessary. The whole wafer can be packaged all at one time which is more efficient than packaging each die individually and allows for parallel testing of the packaged dice while still in wafer form. Additionally, the method of the present invention is easy to implement because, since the solder bumps are defined first, there is no need to be concerned with keeping the bonding pads clean for later addition of solder during the step of adding the adhesive (underfill-flux) layer. Also, since the solder bumps are already in place, it makes it easier to align the solder bumps to the plated through-holes of the interposer substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a silicon wafer having a plurality of chips formed on a top surface.
FIG. 2 is a cross-sectional view of a section 2—2 of the silicon wafer shown in FIG. 1 with the bonding pads re-metallized.
FIGS. 3-7 are cross-sectional views of the silicon wafer of FIG. 1 showing the various process steps used in forming the IC package of the present invention.
FIG. 8 is a cross-sectional view of the silicon wafer of FIG. 1, showing the finalized wafer assembly for the IC package of the present invention.
FIG. 9 is a cross-sectional view of the finalized IC package of the present invention.
FIG. 10 is a cross-sectional view of a ball-grid array package as known in the prior art.
BEST MODE FOR CARRYING OUT THE INVENTION
With reference to FIG. 1, a silicon wafer 21 has a plurality of microcircuits fabricated thereon. The microcircuits are arranged into a matrix of individual chips or dice 24, 25. A plurality of aluminum bonding pads 23 are arranged around the perimeter of each of the chips. In prior art packaging operations, the wafer 21 is usually diced at this point into individual chips, and each of the individual chip is then packaged. In the present invention, the chips are formed on the wafer but are not diced until the packaging operation on the wafer has been completed, thus the packaging of the chip is conducted at the wafer level.
With reference to FIG. 2, a section 2—2 of the wafer 21 is shown, with the aluminum bonding pads 23 being exposed on a top surface of the wafer 21. The first step in the packaging process, is to re-metallize the aluminum bonding pads 23 in order to make the bonding pads solderable. Aluminum, which is commonly used for the wirebond pads of IC's, is a less than ideal metal for use in solder connections due to the fact that the aluminum tends to oxidize which creates solder wetting problems. In the forming of the IC package of the present invention, the aluminum bonding pads need to be wetable by solder or have a low ohmic contact resistance for application of a conductive adhesive. Therefore, the bonding pads need to be re-metallized. One process for re-metallizing the bonding pads, that is inexpensive and convenient to implement, is to use electroless nickel-gold plating. First, a layer of zinc 17 is deposited on the aluminum bonding pads 23, then a layer of electroless nickel plating 18 is deposited on the layer of zinc. The zinc layer 17 acts as an adhesion layer between the nickel plating 18 and the aluminum bond pads 23. Then, a layer of electroless gold plating 19 is deposited on top of the electroless nickel plating 18 to form a nickel-gold plating in order to make the bonding pads 23 conducive to soldering. Alternatively, another thin film metallization scheme can be carried out to re-metallize the bonding pads.
Next, with reference to FIG. 3, a plurality of solder bumps 30 are deposited on the wirebond pad sites 23. This can be carried out by a screen or stencil printing process. The surface of the wafer 21 is screened off and the solder paste is deposited onto the bonding pads 23 by a pneumatic squeegee so that the solder paste is deposited on the wafer all at one time. The solder paste can also be deposited on the bonding pads by the use of automatic dispensing equipment or by solder preform placement. Alternatively, the solder can be electrolytically plated or evaporated onto the wafer. The wafer is processed through solder reflow equipment, such as a solder reflow furnace, to form the solder bumps 30. Another alternative is to use an electrically conductive adhesive, in lieu of the solder paste.
Next, referring to FIG. 4, a layer of adhesive 27 is deposited on the top surface of the wafer 21. The adhesive can be made of an underfill-flux material. The underfill-flux material has two functions. Firstly, it acts as a flux to clean metallic oxide from the solder and the soldering surface. Secondly, the underfill-flux material acts as an adhesive and a sealant. The adhesive layer 27 can be applied through a screen printing process in which the underfill-flux material is pushed through the openings of a stencil or a mesh screen. The screen is mounted onto a screen printer and is precisely positioned with respect to the wafer. A certain amount of the underfill-flux material is dispensed along one edge of the screen and a pneumatic squeegee presses down on the screen as it sweeps across it, sheering the material at a constant pressure. The material acquires higher flowability above certain shear stresses, which allows it to go through the screen and fill the gaps left by the wire mesh of the screen. The area above the bonding pads 23 does not need to be blocked because the solder bumps are already defined and because the underfill-flux material also acts as a solder flux. The screen is removed and a uniform layer of the material is formed on top of the wafer. Alternatively, a B-staged underfill-flux preform can be used to bond the wafer 21 to the backside of an interposer substrate layer. The underfill-flux layer, when cured, acts as an encapsulant, providing environmental protection for the wafer. The underfill-flux also acts as a buffer layer for the wafer 21 from external stresses, such as a thermal coefficient of expansion mismatch between the wafer and the package solder balls used for mounting the IC package, or a mismatch between the wafer and an end-use printed circuit board on which the IC package would be mounted.
With reference to FIG. 5, an interposer substrate layer 31 with plated through-holes is then aligned to the solder bumps 30 over the underfill-flux layer 27 and will be secured to the underfill-flux layer 27 and solder bumps 30 to form a wafer/interposer assembly 39. The interposer substrate 31 is a preformed substrate consisting of metal circuitry 34 and a dielectric base 32. The metal circuitry 34 typically consists of copper traces formed throughout the substrate. The interposer substrate 31 can also include solder resist coatings to help define solder wetable areas on the copper metal circuitry. The metal circuitry 34 can be formed on a single layer or on multiple layers of the interposer substrate 31. The copper metal circuitry can be nickel-gold plated or coated by an organic material which is used to preserve the copper from oxidation. The dielectric base material 32 is typically made of a polyamide base substrate. Alternatively, BT resin and other epoxy-glass substrates can also be used as the dielectric base material 32. A key feature of the interposer substrate 31 is a plurality of openings 38 on the metal circuitry 34. The metal circuitry 34 generally serves as interconnect circuitry, as the traces can be routed throughout the substrate to interconnect the circuits from the various bonding pads 23 to the Input/Output (I/O) interconnects which will be added to the wafer/interposer assembly 39 through the plurality of openings 38, as described later with reference to FIG. 8.
The interposer substrate 31 can be approximately the same size as the wafer 21 and is aligned to the wafer 21 such that the through-holes 36 line up with the bonding pads 23. A sufficient amount of copper must be present in the through-holes 36 to provide adequate connection for solder or for a conductive adhesive. A circular copper ring around the through-holes 36 or a copper strip across the through-holes 36 can be used to facilitate this requirement.
With reference to FIG. 6, the interposer substrate 31 is then adhered to the wafer 21 by the underfill-flux material 27 and the wafer/interposer assembly 39 is then cured. Thus, the interposer is aligned and bonded to the wafer.
Optionally, with reference to FIG. 7, an epoxy coating material 42 can be used to protect the solder connections. Application of the epoxy coating material 42 would also be by the screen or stencil printing process described above and the protective coating would then be cured.
The next step is to place package solder balls on the wafer/interposer assembly. The package solder balls serve as the I/O interconnects for the final IC package and will be used to secure the completed IC package to an end-use printed circuit board. With reference to FIG. 8, the solder balls 50 are placed on the plurality of openings 38 through a mechanical transfer of pre-formed solder balls and then are reflowed onto the metallized openings. Alternatively, the solder balls 50 can be formed by screen or stencil printing solder paste. The solder is then reflowed to form the package solder balls. An electrical and mechanical connection is made between the solder balls 50 and the metal circuitry 34 of the interposer substrate, and thus an electrical and mechanical connection is made between the solder balls 50 and the bonding pads 23 of the wafer 21. The solder balls 50 are applied in whatever type of pattern is desired, such as in a uniform full matrix over the entire surface.
At this point, electrical testing may be conducted on the wafer/interposer assembly 39 since the wafer assembly 39 contains finished dice arranged in a matrix format. This allows for parallel testing, which can be conducted at the wafer level and can provide savings in testing time and cost. Then the wafer/interposer assembly 39 is diced, or singulated, such as along line 60, to form individual chip-size BGA packages 70, 72. A common technique for the singulation is to use a wafer saw with diamond or resinoid saw blades. With reference to FIG. 9, the finished BGA package 70 can then be mounted on the end-use printed circuit board in the same manner as prior art BGA packages. The BGA package 70 of the present invention has the same footprint as the individual silicon die, as no extra space is needed to accommodate wirebond leads or larger substrate bases. In this way, the integrated circuit package of the present invention provides the advantages of a smaller package size and the convenience of packaging at the wafer level.

Claims (19)

What is claimed is:
1. A method of forming an integrated circuit chip package on a wafer level, comprising:
providing a silicon wafer having a plurality of bonding pads disposed on a first surface thereof;
depositing a conductive material on the plurality of bonding pads;
depositing an underfill-flux material on the first surface of the wafer;
securing an interposer substrate, composed of a dielectric material and a plurality of metallized traces, to the layer of underfill-flux material to form a wafer/interposer assembly, the interposer substrate including a plurality of metallized through-holes which are aligned to the plurality of bonding pads and including a plurality of openings on a surface of the interposer substrate over the plurality of metallized traces;
forming an electrical connection between the plurality of through-holes and the plurality of bonding pads;
attaching a plurality of I/O interconnects through the plurality of openings to the metallized traces of the interposer substrate; and
dicing the wafer/interposer assembly into a plurality of individual integrated circuit chip packages.
2. The method of claim 1 wherein the conductive material is a plurality of solder bumps formed on the plurality of bonding pads.
3. The method of claim 2 wherein the step of forming an electrical connection between the plurality of through-holes and the plurality of bonding pads includes reflowing the solder bumps to the interposer substrate.
4. The method of claim 1 wherein the conductive material is a conductive adhesive applied to the plurality of bonding pads.
5. The method of claim 4 wherein the step of forming an electrical connection between the plurality of through-holes and the plurality of bonding pads further comprises curing the conductive adhesive to the metallized openings of the interposer substrate.
6. The method of claim 1 wherein the step of securing the interposer substrate to the underfill-flux material includes curing the underfill-flux material.
7. The method of claim 1 wherein the plurality of I/O interconnects are a plurality of solder balls.
8. The method of claim 7 wherein the step of attaching the plurality of I/O interconnects through the plurality of openings to the metallized traces includes:
placing the plurality of solder balls on the plurality of openings; and
reflowing the plurality of solder balls to form a plurality of interconnections.
9. The method of claim 1 further comprising after the step of forming an electrical connection between the plurality of through-holes and the plurality of bonding pads, applying an epoxy coating over the through-holes.
10. The method of claim 1 further comprising after the step of providing a silicon wafer, re-metallizing the plurality of bonding pads.
11. The method of claim 10 wherein the step of re-metallizing the plurality of bonding pads includes:
depositing a layer of zinc on each of the bonding pads;
depositing a layer of electroless nickel plating on top of the layer of zinc on each of the bonding pads; and
depositing a layer of electroless gold plating over the layer of electroless nickel plating on each of the bonding pads.
12. A method of forming an integrated circuit chip package on a wafer level, comprising:
providing a silicon wafer having a plurality of bonding pads disposed on a first surface thereof;
depositing a plurality of solder bumps on the plurality of bonding pads;
depositing an underfill-flux material on the first surface of the wafer;
aligning an interposer substrate composed of a dielectric material and a plurality of metallized traces, to the solder bumps on the wafer, the interposer substrate including a plurality of metallized through-holes which are aligned to the plurality of solder bumps;
reflowing the solder bumps to the through-holes of the interposer substrate to form an electrical connection and securing the interposer substrate to the underfill-flux material to form a wafer/interposer assembly;
attaching a plurality of I/O interconnects through a plurality of openings on a surface of the interposer substrate to the metallized traces; and
dicing the wafer/interposer assembly into a plurality of individual integrated circuit chip packages.
13. The method of claim 12 wherein the step of securing the interposer substrate to the underfill-flux material includes curing the underfill-flux material.
14. The method of claim 12 wherein the plurality of I/O interconnects are a plurality of solder balls.
15. The method of claim 14 wherein the step of attaching the plurality of I/O interconnects through the plurality of openings to the metallized traces includes:
placing the plurality of solder balls on the plurality of openings; and
reflowing the plurality of solder balls to form a plurality of interconnections.
16. The method of claim 12 further comprising after the step of forming an electrical connection between the plurality of through-holes and the plurality of bonding pads, applying an epoxy coating over the through-holes.
17. The method of claim 12 further comprising after the step of providing a silicon wafer, re-metallizing the plurality of bonding pads.
18. The method of claim 17 wherein the step of re-metallizing the plurality of bonding pads includes:
depositing a layer of zinc on each of the bonding pads;
depositing a layer of electroless nickel plating on top of the layer of zinc on each of the bonding pads.
19. A method of forming an integrated circuit chip package on a wafer level, comprising:
providing a silicon wafer having a plurality of bonding pads disposed on a first surface thereof;
re-metallizing the plurality of bonding pads;
depositing a plurality of solder bumps on the plurality of bonding pads;
depositing an underfill-flux material on the first surface of the wafer,
aligning an interposer substrate, composed of a dielectric material and a plurality of metallized traces, to the solder bumps on the wafer, the interposer substrate including a plurality of metallized through-holes which are aligned to the plurality of solder bumps;
reflowing the solder bumps to the metallized through-holes of the interposer substrate to form an electrical connection and curing the underfill-flux material to secure the underfill-flux material to the interposer substrate to form a wafer/interposer assembly;
applying an epoxy coating over the through-holes;
attaching a plurality of I/O interconnects through a plurality of openings on a surface of the interposer substrate to the metallized traces; and
dicing the wafer/interposer assembly into a plurality of individual integrated circuit chip packages.
US09/558,396 2000-04-25 2000-04-25 Method of forming an integrated circuit package at a wafer level Expired - Fee Related US6281046B1 (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
US09/558,396 US6281046B1 (en) 2000-04-25 2000-04-25 Method of forming an integrated circuit package at a wafer level
KR1020027013911A KR20040004761A (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
EP01923160A EP1279193A2 (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
JP2001579352A JP2003532294A (en) 2000-04-25 2001-04-04 Method of forming integrated circuit package at wafer level
PCT/US2001/011035 WO2001082361A2 (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
CA002402082A CA2402082A1 (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
HK03105947.0A HK1053746B (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
CNB018084257A CN1181524C (en) 2000-04-25 2001-04-04 Method for forming an integrated circuit package on a wafer
AU2001249879A AU2001249879A1 (en) 2000-04-25 2001-04-04 Method of forming an integrated circuit package at a wafer level
MYPI20011821A MY134243A (en) 2000-04-25 2001-04-17 Method of forming an integrated circuit package at a wafer level
TW090109512A TW503486B (en) 2000-04-25 2001-04-20 Method of forming an integrated circuit package at a wafer level
NO20024196A NO20024196L (en) 2000-04-25 2002-09-03 Method of making an integrated circuit package on a silicone wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/558,396 US6281046B1 (en) 2000-04-25 2000-04-25 Method of forming an integrated circuit package at a wafer level

Publications (1)

Publication Number Publication Date
US6281046B1 true US6281046B1 (en) 2001-08-28

Family

ID=24229375

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/558,396 Expired - Fee Related US6281046B1 (en) 2000-04-25 2000-04-25 Method of forming an integrated circuit package at a wafer level

Country Status (11)

Country Link
US (1) US6281046B1 (en)
EP (1) EP1279193A2 (en)
JP (1) JP2003532294A (en)
KR (1) KR20040004761A (en)
CN (1) CN1181524C (en)
AU (1) AU2001249879A1 (en)
CA (1) CA2402082A1 (en)
MY (1) MY134243A (en)
NO (1) NO20024196L (en)
TW (1) TW503486B (en)
WO (1) WO2001082361A2 (en)

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413799B1 (en) * 1999-12-14 2002-07-02 Atmel Corporation Method of forming a ball-grid array package at a wafer level
US20020098623A1 (en) * 2000-08-31 2002-07-25 Salman Akram Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
US6445075B1 (en) 2001-01-26 2002-09-03 Amkor Technology, Inc. Semiconductor module package substrate
US20020164838A1 (en) * 2001-05-02 2002-11-07 Moon Ow Chee Flexible ball grid array chip scale packages and methods of fabrication
US6494361B1 (en) * 2001-01-26 2002-12-17 Amkor Technology, Inc. Semiconductor module package substrate fabrication method
US6506672B1 (en) * 1999-06-30 2003-01-14 University Of Maryland, College Park Re-metallized aluminum bond pad, and method for making the same
US6586276B2 (en) * 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US20030128044A1 (en) * 2000-12-15 2003-07-10 Pierce John L. Method for producing a wafer interposer for use in a wafer interposer assembly
WO2003060985A1 (en) * 2002-01-11 2003-07-24 Motorola, Inc., A Corporation Of The State Of Delaware Semiconductor package device and method
US20030162380A1 (en) * 2002-02-27 2003-08-28 Ho-Ming Tong Solder ball fabricating process
US20030164548A1 (en) * 2002-03-04 2003-09-04 Lee Teck Kheng Flip chip packaging using recessed interposer terminals
US20030164541A1 (en) * 2002-03-04 2003-09-04 Lee Teck Kheng Method and apparatus for dielectric filling of flip chip on interposer assembly
US20030178717A1 (en) * 2000-11-16 2003-09-25 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US6673653B2 (en) 2001-02-23 2004-01-06 Eaglestone Partners I, Llc Wafer-interposer using a ceramic substrate
US20040014317A1 (en) * 2000-09-25 2004-01-22 Hajime Sakamoto Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US6686657B1 (en) 2000-11-07 2004-02-03 Eaglestone Partners I, Llc Interposer for improved handling of semiconductor wafers and method of use of same
US20040021234A1 (en) * 2002-07-15 2004-02-05 Kazutaka Shibata Semiconductor device and manufacturing method thereof
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US6759741B2 (en) 2000-07-31 2004-07-06 Eaglestone Partners I, Llc Matched set of integrated circuit chips selected from a multi wafer-interposer
US20040155328A1 (en) * 2000-07-31 2004-08-12 Kline Jerry D. Wafer-interposer assembly
US20040188123A1 (en) * 2003-03-18 2004-09-30 Peterson Darin L. Microelectronic component assemblies having exposed contacts
US20040219715A1 (en) * 2002-05-17 2004-11-04 Samsung Electronics Co., Ltd. Bump formed on semiconductor device chip and method for manufacturing the bump
US20040219713A1 (en) * 2002-01-09 2004-11-04 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US6815712B1 (en) * 2000-10-02 2004-11-09 Eaglestone Partners I, Llc Method for selecting components for a matched set from a wafer-interposer assembly
US20040224437A1 (en) * 2001-08-21 2004-11-11 Micron Technology, Inc. Microelectronic devices including underfill apertures
US6825678B2 (en) 1999-11-16 2004-11-30 Eaglestone Partners I, Llc Wafer level interposer
US20050029550A1 (en) * 2002-03-04 2005-02-10 Lee Teck Kheng Semiconductor die packages with recessed interconnecting structures
US20050082347A1 (en) * 2003-10-17 2005-04-21 International Business Machines Corporation Self-locking wire bond structure and method of making the same
US20050087859A1 (en) * 2003-08-28 2005-04-28 Advanced Semiconductor Engineering, Inc. Semiconductor chip package and method for manufacturing the same
US6933617B2 (en) 2000-12-15 2005-08-23 Eaglestone Partners I, Llc Wafer interposer assembly
US20050194665A1 (en) * 2003-01-21 2005-09-08 Huang Chien P. Semiconductor package free of substrate and fabrication method thereof
US20050277279A1 (en) * 2004-06-14 2005-12-15 Shijian Luo Microfeature devices and methods for manufacturing microfeature devices
US20060012042A1 (en) * 2003-06-27 2006-01-19 Intel Corporation Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
US20060019468A1 (en) * 2004-07-21 2006-01-26 Beatty John J Method of manufacturing a plurality of electronic assemblies
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7087460B2 (en) 2002-03-04 2006-08-08 Micron Technology, Inc. Methods for assembly and packaging of flip chip configured dice with interposer
US7145225B2 (en) 2002-03-04 2006-12-05 Micron Technology, Inc. Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US20060273430A1 (en) * 2005-03-24 2006-12-07 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
US20070182010A1 (en) * 2004-03-31 2007-08-09 Koning Paul A Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor
WO2007115371A1 (en) * 2006-04-10 2007-10-18 Epitactix Pty Ltd Method, apparatus and resulting structures in the manufacture of semiconductors
US20080060838A1 (en) * 2006-09-13 2008-03-13 Phoenix Precision Technology Corporation Flip chip substrate structure and the method for manufacturing the same
US20080151519A1 (en) * 2000-02-25 2008-06-26 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
CN100416802C (en) * 2003-10-08 2008-09-03 联华电子股份有限公司 Wafer level packaging method and structure
CN100437958C (en) * 2005-11-03 2008-11-26 台湾应解股份有限公司 Chip packaging structure and manufacturing method thereof
US20090002963A1 (en) * 2007-06-27 2009-01-01 Cooney Robert C Method of attaching die to circuit board with an intermediate interposer
US20090017610A1 (en) * 2005-09-30 2009-01-15 Yasuo Tanaka Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device
US20090032957A1 (en) * 2007-07-31 2009-02-05 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US20090072394A1 (en) * 2007-02-28 2009-03-19 Masanori Onodera Semiconductor device and method of manufacturing the same
US20100148362A1 (en) * 2008-10-23 2010-06-17 Panasonic Corparation Semiconductor device and method for fabricating the same
US20100302749A1 (en) * 2009-06-01 2010-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling Warpage in BGA Components in a Re-flow Process
US20110049671A1 (en) * 2009-08-25 2011-03-03 Ming-Tzong Yang Bonding pad structure and integrated circuit chip using such bonding pad structure
US7915718B2 (en) 2002-03-04 2011-03-29 Micron Technology, Inc. Apparatus for flip-chip packaging providing testing capability
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
GB2477358A (en) * 2010-02-02 2011-08-03 Thales Holdings Uk Plc RF testing an integrated circuit assembly during manufacture using a interposed adaptor layer which is removed after test to attach the IC to a BGA
US20110187005A1 (en) * 2010-02-03 2011-08-04 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
US20110233745A1 (en) * 2007-05-17 2011-09-29 Micron Technology, Inc. Integrated Circuit Packages
EP2293325A3 (en) * 2001-12-14 2011-10-26 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof
TWI387067B (en) * 2009-03-17 2013-02-21 南茂科技股份有限公司 Substrate-free chip package and method of manufacturing same
CN103208482A (en) * 2012-01-17 2013-07-17 台湾积体电路制造股份有限公司 Through-assembly Via Modules And Methods For Forming The Same
US20140106511A1 (en) * 2012-03-06 2014-04-17 Triquint Semiconductor, Inc. Flip-chip packaging techniques and configurations
TWI501549B (en) * 2013-12-11 2015-09-21 Kuan Jung Chung Method for forming cavity of surface acoustic wave element
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9230873B2 (en) 2011-07-15 2016-01-05 3M Innovative Properties Company Semiconductor package resin composition and usage method thereof
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9490167B2 (en) 2012-10-11 2016-11-08 Taiwan Semiconductor Manufactoring Company, Ltd. Pop structures and methods of forming the same
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US10163773B1 (en) 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
WO2020000414A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101000455B1 (en) * 2004-01-15 2010-12-13 삼성전자주식회사 Driving chip and display device having same
US7524351B2 (en) 2004-09-30 2009-04-28 Intel Corporation Nano-sized metals and alloys, and methods of assembling packages containing same
KR100665288B1 (en) * 2005-11-15 2007-01-09 삼성전기주식회사 Flip chip package manufacturing method
CN100434354C (en) * 2006-04-07 2008-11-19 美新半导体（无锡）有限公司 Wafer-level hermetic packaging process with Y-shaped through-holes
CN100499097C (en) * 2006-08-21 2009-06-10 南茂科技股份有限公司 High frequency integrated circuit package structure with improved embedded bump connectivity and method of manufacture
US7662665B2 (en) * 2007-01-22 2010-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging
CN100590823C (en) * 2007-11-15 2010-02-17 南茂科技股份有限公司 Method for manufacturing alignment mark used in packaging structure with reconfigured crystal grains
KR100974244B1 (en) * 2008-06-12 2010-08-05 엘지이노텍 주식회사 Method of manufacturing semiconductor package substrate and semiconductor package substrate
CN102315186A (en) * 2010-06-30 2012-01-11 万国半导体股份有限公司 Semiconductor device packaged with printing bonding materials and manufacturing method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5569963A (en) 1989-08-28 1996-10-29 Lsi Logic Corporation Preformed planar structures for semiconductor device assemblies
US5604160A (en) 1996-07-29 1997-02-18 Motorola, Inc. Method for packaging semiconductor devices
US5798557A (en) 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
US5821624A (en) 1989-08-28 1998-10-13 Lsi Logic Corporation Semiconductor device assembly techniques using preformed planar structures
US5851845A (en) 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US6004867A (en) 1996-12-16 1999-12-21 Samsung Electronics Co., Ltd. Chip-size packages assembled using mass production techniques at the wafer-level
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7041771B1 (en) * 1995-08-11 2006-05-09 Kac Holdings, Inc. Encapsulant with fluxing properties and method of use in flip-chip surface mount reflow soldering
US6020220A (en) * 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
DE19702186C2 (en) * 1997-01-23 2002-06-27 Fraunhofer Ges Forschung Process for packaging integrated circuits
AU8502798A (en) * 1997-07-21 1999-02-10 Aguila Technologies, Inc. Semiconductor flip-chip package and method for the fabrication thereof
JPH11214421A (en) * 1997-10-13 1999-08-06 Matsushita Electric Ind Co Ltd Method for forming electrodes of semiconductor device
JP2000036518A (en) * 1998-07-16 2000-02-02 Nitto Denko Corp Wafer scale package structure and circuit board used therefor
US6388335B1 (en) * 1999-12-14 2002-05-14 Atmel Corporation Integrated circuit package formed at a wafer level

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5569963A (en) 1989-08-28 1996-10-29 Lsi Logic Corporation Preformed planar structures for semiconductor device assemblies
US5821624A (en) 1989-08-28 1998-10-13 Lsi Logic Corporation Semiconductor device assembly techniques using preformed planar structures
US5851845A (en) 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US5604160A (en) 1996-07-29 1997-02-18 Motorola, Inc. Method for packaging semiconductor devices
US5798557A (en) 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
US6004867A (en) 1996-12-16 1999-12-21 Samsung Electronics Co., Ltd. Chip-size packages assembled using mass production techniques at the wafer-level
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package

Cited By (191)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506672B1 (en) * 1999-06-30 2003-01-14 University Of Maryland, College Park Re-metallized aluminum bond pad, and method for making the same
US6825678B2 (en) 1999-11-16 2004-11-30 Eaglestone Partners I, Llc Wafer level interposer
US6413799B1 (en) * 1999-12-14 2002-07-02 Atmel Corporation Method of forming a ball-grid array package at a wafer level
US20080201944A1 (en) * 2000-02-25 2008-08-28 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US7842887B2 (en) 2000-02-25 2010-11-30 Ibiden Co., Ltd. Multilayer printed circuit board
US20100018049A1 (en) * 2000-02-25 2010-01-28 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US20080151519A1 (en) * 2000-02-25 2008-06-26 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US8186045B2 (en) * 2000-02-25 2012-05-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US20080151520A1 (en) * 2000-02-25 2008-06-26 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US7888606B2 (en) 2000-02-25 2011-02-15 Ibiden Co., Ltd. Multilayer printed circuit board
US7888605B2 (en) 2000-02-25 2011-02-15 Ibiden Co., Ltd. Multilayer printed circuit board
US7884286B2 (en) 2000-02-25 2011-02-08 Ibiden Co., Ltd. Multilayer printed circuit board
US20090070996A1 (en) * 2000-02-25 2009-03-19 Ibiden Co., Ltd. Printed circuit board manufacturing method
US8438727B2 (en) * 2000-02-25 2013-05-14 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US8079142B2 (en) 2000-02-25 2011-12-20 Ibiden Co., Ltd. Printed circuit board manufacturing method
US8046914B2 (en) 2000-02-25 2011-11-01 Ibiden Co., Ltd. Method for manufacturing multilayer printed circuit board
US8453323B2 (en) 2000-02-25 2013-06-04 Ibiden Co., Ltd. Printed circuit board manufacturing method
US6967494B2 (en) 2000-07-31 2005-11-22 Eaglestone Partners I, Llc Wafer-interposer assembly
US6759741B2 (en) 2000-07-31 2004-07-06 Eaglestone Partners I, Llc Matched set of integrated circuit chips selected from a multi wafer-interposer
US20040155328A1 (en) * 2000-07-31 2004-08-12 Kline Jerry D. Wafer-interposer assembly
US6812048B1 (en) 2000-07-31 2004-11-02 Eaglestone Partners I, Llc Method for manufacturing a wafer-interposer assembly
US20040256740A1 (en) * 2000-08-31 2004-12-23 Salman Akram Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof
US6762502B1 (en) 2000-08-31 2004-07-13 Micron Technology, Inc. Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof
US20020098623A1 (en) * 2000-08-31 2002-07-25 Salman Akram Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
US6794224B2 (en) 2000-08-31 2004-09-21 Micron Technology, Inc. Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
US20090263939A1 (en) * 2000-09-25 2009-10-22 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20090077796A1 (en) * 2000-09-25 2009-03-26 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US9245838B2 (en) 2000-09-25 2016-01-26 Ibiden Co., Ltd. Semiconductor element
US20100140803A1 (en) * 2000-09-25 2010-06-10 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7999387B2 (en) 2000-09-25 2011-08-16 Ibiden Co., Ltd. Semiconductor element connected to printed circuit board
US8293579B2 (en) 2000-09-25 2012-10-23 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20040014317A1 (en) * 2000-09-25 2004-01-22 Hajime Sakamoto Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7852634B2 (en) 2000-09-25 2010-12-14 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US8524535B2 (en) 2000-09-25 2013-09-03 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20080230914A1 (en) * 2000-09-25 2008-09-25 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7855342B2 (en) 2000-09-25 2010-12-21 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20080206926A1 (en) * 2000-09-25 2008-08-28 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20080169123A1 (en) * 2000-09-25 2008-07-17 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20080151522A1 (en) * 2000-09-25 2008-06-26 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20080148563A1 (en) * 2000-09-25 2008-06-26 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7893360B2 (en) * 2000-09-25 2011-02-22 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7908745B2 (en) 2000-09-25 2011-03-22 Ibiden Co., Ltd. Method of manufacturing multi-layer printed circuit board
US8822323B2 (en) 2000-09-25 2014-09-02 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US8067699B2 (en) * 2000-09-25 2011-11-29 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US8959756B2 (en) 2000-09-25 2015-02-24 Ibiden Co., Ltd. Method of manufacturing a printed circuit board having an embedded electronic component
US20070209831A1 (en) * 2000-09-25 2007-09-13 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US6815712B1 (en) * 2000-10-02 2004-11-09 Eaglestone Partners I, Llc Method for selecting components for a matched set from a wafer-interposer assembly
US20040166663A1 (en) * 2000-11-07 2004-08-26 Kline Jerry D. Method for constructing a wafer-interposer assembly
US6686657B1 (en) 2000-11-07 2004-02-03 Eaglestone Partners I, Llc Interposer for improved handling of semiconductor wafers and method of use of same
US6927083B2 (en) 2000-11-07 2005-08-09 Eaglestone Partners I, Llc Method for constructing a wafer-interposer assembly
US6890793B2 (en) * 2000-11-16 2005-05-10 Fairchild Semiconductor Corporation Method for producing a semiconductor die package using leadframe with locating holes
US20030178717A1 (en) * 2000-11-16 2003-09-25 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US20030128044A1 (en) * 2000-12-15 2003-07-10 Pierce John L. Method for producing a wafer interposer for use in a wafer interposer assembly
US7036218B2 (en) 2000-12-15 2006-05-02 Eaglestone Partners I, Llc Method for producing a wafer interposer for use in a wafer interposer assembly
US6933617B2 (en) 2000-12-15 2005-08-23 Eaglestone Partners I, Llc Wafer interposer assembly
US6445075B1 (en) 2001-01-26 2002-09-03 Amkor Technology, Inc. Semiconductor module package substrate
US6494361B1 (en) * 2001-01-26 2002-12-17 Amkor Technology, Inc. Semiconductor module package substrate fabrication method
US6673653B2 (en) 2001-02-23 2004-01-06 Eaglestone Partners I, Llc Wafer-interposer using a ceramic substrate
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US20020164838A1 (en) * 2001-05-02 2002-11-07 Moon Ow Chee Flexible ball grid array chip scale packages and methods of fabrication
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) * 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US20060267171A1 (en) * 2001-08-21 2006-11-30 Micron Technology, Inc. Semiconductor device modules, semiconductor devices, and microelectronic devices
US20040224437A1 (en) * 2001-08-21 2004-11-11 Micron Technology, Inc. Microelectronic devices including underfill apertures
US7087994B2 (en) 2001-08-21 2006-08-08 Micron Technology, Inc. Microelectronic devices including underfill apertures
EP2293325A3 (en) * 2001-12-14 2011-10-26 STMicroelectronics S.r.l. Semiconductor electronic device and method of manufacturing thereof
US20040219713A1 (en) * 2002-01-09 2004-11-04 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US8441113B2 (en) 2002-01-09 2013-05-14 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US7189593B2 (en) 2002-01-09 2007-03-13 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US7129584B2 (en) 2002-01-09 2006-10-31 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
US8125065B2 (en) 2002-01-09 2012-02-28 Micron Technology, Inc. Elimination of RDL using tape base flip chip on flex for die stacking
WO2003060985A1 (en) * 2002-01-11 2003-07-24 Motorola, Inc., A Corporation Of The State Of Delaware Semiconductor package device and method
US6673711B2 (en) * 2002-02-27 2004-01-06 Advanced Semiconductor Engineering, Inc. Solder ball fabricating process
US20030162380A1 (en) * 2002-02-27 2003-08-28 Ho-Ming Tong Solder ball fabricating process
US20030164541A1 (en) * 2002-03-04 2003-09-04 Lee Teck Kheng Method and apparatus for dielectric filling of flip chip on interposer assembly
US7161237B2 (en) * 2002-03-04 2007-01-09 Micron Technology, Inc. Flip chip packaging using recessed interposer terminals
US7348215B2 (en) 2002-03-04 2008-03-25 Micron Technology, Inc. Methods for assembly and packaging of flip chip configured dice with interposer
US20030164548A1 (en) * 2002-03-04 2003-09-04 Lee Teck Kheng Flip chip packaging using recessed interposer terminals
US6975035B2 (en) 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
US7112520B2 (en) 2002-03-04 2006-09-26 Micron Technology, Inc. Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US7087460B2 (en) 2002-03-04 2006-08-08 Micron Technology, Inc. Methods for assembly and packaging of flip chip configured dice with interposer
US7122907B2 (en) 2002-03-04 2006-10-17 Micron Technology, Inc. Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice
US8269326B2 (en) 2002-03-04 2012-09-18 Micron Technology, Inc. Semiconductor device assemblies
US7902648B2 (en) 2002-03-04 2011-03-08 Micron Technology, Inc. Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods
US7230330B2 (en) 2002-03-04 2007-06-12 Micron Technology, Inc. Semiconductor die packages with recessed interconnecting structures
SG115459A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
US20040159957A1 (en) * 2002-03-04 2004-08-19 Lee Teck Kheng Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice
US7569473B2 (en) 2002-03-04 2009-08-04 Micron Technology, Inc. Methods of forming semiconductor assemblies
US20050029550A1 (en) * 2002-03-04 2005-02-10 Lee Teck Kheng Semiconductor die packages with recessed interconnecting structures
US7534660B2 (en) 2002-03-04 2009-05-19 Micron Technology, Inc. Methods for assembly and packaging of flip chip configured dice with interposer
US7531906B2 (en) 2002-03-04 2009-05-12 Micron Technology, Inc. Flip chip packaging using recessed interposer terminals
US7915718B2 (en) 2002-03-04 2011-03-29 Micron Technology, Inc. Apparatus for flip-chip packaging providing testing capability
US7145225B2 (en) 2002-03-04 2006-12-05 Micron Technology, Inc. Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US20040219715A1 (en) * 2002-05-17 2004-11-04 Samsung Electronics Co., Ltd. Bump formed on semiconductor device chip and method for manufacturing the bump
US7074704B2 (en) * 2002-05-17 2006-07-11 Samsung Electronics Co., Ltd. Bump formed on semiconductor device chip and method for manufacturing the bump
US20040021234A1 (en) * 2002-07-15 2004-02-05 Kazutaka Shibata Semiconductor device and manufacturing method thereof
US20040266139A1 (en) * 2002-07-15 2004-12-30 Kazutaka Shibata Semiconductor device and manufacturing method thereof
US7329603B2 (en) 2002-07-15 2008-02-12 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof
US7358618B2 (en) * 2002-07-15 2008-04-15 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof
US20080128906A1 (en) * 2002-07-15 2008-06-05 Rohm Co., Ltd Semiconductor device and manufacturing method thereof
US7320933B2 (en) 2002-08-20 2008-01-22 Micron Technology, Inc. Double bumping of flexible substrate for first and second level interconnects
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US20050194665A1 (en) * 2003-01-21 2005-09-08 Huang Chien P. Semiconductor package free of substrate and fabrication method thereof
US6921860B2 (en) * 2003-03-18 2005-07-26 Micron Technology, Inc. Microelectronic component assemblies having exposed contacts
US20040188123A1 (en) * 2003-03-18 2004-09-30 Peterson Darin L. Microelectronic component assemblies having exposed contacts
US20060012042A1 (en) * 2003-06-27 2006-01-19 Intel Corporation Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
US20050087859A1 (en) * 2003-08-28 2005-04-28 Advanced Semiconductor Engineering, Inc. Semiconductor chip package and method for manufacturing the same
US7041534B2 (en) * 2003-08-28 2006-05-09 Advanced Semiconductor Engineering, Inc. Semiconductor chip package and method for making the same
CN100416802C (en) * 2003-10-08 2008-09-03 联华电子股份有限公司 Wafer level packaging method and structure
US7073702B2 (en) 2003-10-17 2006-07-11 International Business Machines Corporation Self-locking wire bond structure and method of making the same
US20050082347A1 (en) * 2003-10-17 2005-04-21 International Business Machines Corporation Self-locking wire bond structure and method of making the same
US20070182010A1 (en) * 2004-03-31 2007-08-09 Koning Paul A Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor
US7199037B2 (en) 2004-06-14 2007-04-03 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US7253089B2 (en) * 2004-06-14 2007-08-07 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US20050277279A1 (en) * 2004-06-14 2005-12-15 Shijian Luo Microfeature devices and methods for manufacturing microfeature devices
US7411297B2 (en) 2004-06-14 2008-08-12 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US20060194424A1 (en) * 2004-06-14 2006-08-31 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US20060189118A1 (en) * 2004-06-14 2006-08-24 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US20060019468A1 (en) * 2004-07-21 2006-01-26 Beatty John J Method of manufacturing a plurality of electronic assemblies
WO2006019674A3 (en) * 2004-07-21 2006-06-29 Intel Corp A method of manufacturing a plurality of electronic assemblies
US8709869B2 (en) 2004-07-21 2014-04-29 Intel Corporation Method of manufacturing a plurality of electronic assemblies
US7495462B2 (en) * 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
US20060273430A1 (en) * 2005-03-24 2006-12-07 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
US7947593B2 (en) * 2005-09-30 2011-05-24 Oki Semiconductor Co., Ltd. Method of manufacturing a semiconductor device having an intermetallic terminal pad and solder junction structure
US20090017610A1 (en) * 2005-09-30 2009-01-15 Yasuo Tanaka Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device
CN100437958C (en) * 2005-11-03 2008-11-26 台湾应解股份有限公司 Chip packaging structure and manufacturing method thereof
WO2007115371A1 (en) * 2006-04-10 2007-10-18 Epitactix Pty Ltd Method, apparatus and resulting structures in the manufacture of semiconductors
US20080060838A1 (en) * 2006-09-13 2008-03-13 Phoenix Precision Technology Corporation Flip chip substrate structure and the method for manufacturing the same
US20090072394A1 (en) * 2007-02-28 2009-03-19 Masanori Onodera Semiconductor device and method of manufacturing the same
US9508651B2 (en) * 2007-02-28 2016-11-29 Cypress Semiconductor Corporation Semiconductor device and method of manufacturing the same
US11018105B2 (en) 2007-02-28 2021-05-25 Cypress Semiconductor Corporation Semiconductor device and method of manufacturing the same
US20110233745A1 (en) * 2007-05-17 2011-09-29 Micron Technology, Inc. Integrated Circuit Packages
US8709866B2 (en) 2007-05-17 2014-04-29 Micron Technology, Inc. Methods of forming integrated circuit packages
US8531031B2 (en) * 2007-05-17 2013-09-10 Micron Technology, Inc. Integrated circuit packages
US20090002963A1 (en) * 2007-06-27 2009-01-01 Cooney Robert C Method of attaching die to circuit board with an intermediate interposer
US8481861B2 (en) 2007-06-27 2013-07-09 Hamilton Sundstrand Corporation Method of attaching die to circuit board with an intermediate interposer
US7982137B2 (en) 2007-06-27 2011-07-19 Hamilton Sundstrand Corporation Circuit board with an attached die and intermediate interposer
US20110232952A1 (en) * 2007-06-27 2011-09-29 Cooney Robert C Method of attaching die to circuit board with an intermediate interposer
US8610277B2 (en) * 2007-07-31 2013-12-17 Samsung Electronics Co., Ltd. Bridge type pad structure of a semiconductor device
US20090032957A1 (en) * 2007-07-31 2009-02-05 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US8450848B2 (en) * 2008-10-23 2013-05-28 Panasonic Corporation Semiconductor device and method for fabricating the same
US20100148362A1 (en) * 2008-10-23 2010-06-17 Panasonic Corparation Semiconductor device and method for fabricating the same
TWI387067B (en) * 2009-03-17 2013-02-21 南茂科技股份有限公司 Substrate-free chip package and method of manufacturing same
US8397380B2 (en) * 2009-06-01 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling warpage in BGA components in a re-flow process
US20100302749A1 (en) * 2009-06-01 2010-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling Warpage in BGA Components in a Re-flow Process
US20110049671A1 (en) * 2009-08-25 2011-03-03 Ming-Tzong Yang Bonding pad structure and integrated circuit chip using such bonding pad structure
US8278733B2 (en) 2009-08-25 2012-10-02 Mediatek Inc. Bonding pad structure and integrated circuit chip using such bonding pad structure
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
US8288175B2 (en) 2010-02-02 2012-10-16 Thales Holdings Uk Plc Method of manufacture of an integrated circuit package
US20110207242A1 (en) * 2010-02-02 2011-08-25 Thales Holdings Uk Plc Method of manufacture of an integrated circuit package
GB2477358A (en) * 2010-02-02 2011-08-03 Thales Holdings Uk Plc RF testing an integrated circuit assembly during manufacture using a interposed adaptor layer which is removed after test to attach the IC to a BGA
US20110187005A1 (en) * 2010-02-03 2011-08-04 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
US20140008769A1 (en) * 2010-02-03 2014-01-09 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US9679881B2 (en) * 2010-02-03 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US9230873B2 (en) 2011-07-15 2016-01-05 3M Innovative Properties Company Semiconductor package resin composition and usage method thereof
US9773714B2 (en) 2011-07-15 2017-09-26 3M Innovative Properties Company Semiconductor package resin composition and usage method thereof
CN103208482A (en) * 2012-01-17 2013-07-17 台湾积体电路制造股份有限公司 Through-assembly Via Modules And Methods For Forming The Same
US8928114B2 (en) * 2012-01-17 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
CN103208482B (en) * 2012-01-17 2015-11-18 台湾积体电路制造股份有限公司 Through-hole component module and forming method thereof
US20130181325A1 (en) * 2012-01-17 2013-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Through-Assembly Via Modules and Methods for Forming the Same
US9257332B2 (en) 2012-01-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US20140106511A1 (en) * 2012-03-06 2014-04-17 Triquint Semiconductor, Inc. Flip-chip packaging techniques and configurations
US10515938B2 (en) 2012-03-30 2019-12-24 Taiwan Semiconductor Manufacturing Company Package on-package (PoP) device with integrated passive device in a via
US10163873B2 (en) 2012-03-30 2018-12-25 Taiwan Semiconductor Manufacturing Company Package-on-package (PoP) device with integrated passive device in a via
US10978433B2 (en) 2012-03-30 2021-04-13 Taiwan Semiconductor Manufacturing Company Package-on-package (PoP) device with integrated passive device in a via
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US10510727B2 (en) 2012-09-10 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US11855045B2 (en) 2012-09-10 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9543278B2 (en) 2012-09-10 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US10008479B2 (en) 2012-09-10 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US11217562B2 (en) 2012-09-10 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US12334476B2 (en) 2012-09-10 2025-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9490167B2 (en) 2012-10-11 2016-11-08 Taiwan Semiconductor Manufactoring Company, Ltd. Pop structures and methods of forming the same
US10109567B2 (en) 2012-10-19 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US12170242B2 (en) 2012-10-19 2024-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US10804187B2 (en) 2012-10-19 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US11527464B2 (en) 2012-10-19 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US10510717B2 (en) 2013-10-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US10964666B2 (en) 2013-10-30 2021-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9704826B2 (en) 2013-10-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
TWI501549B (en) * 2013-12-11 2015-09-21 Kuan Jung Chung Method for forming cavity of surface acoustic wave element
US10163773B1 (en) 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
US10607929B2 (en) 2017-08-11 2020-03-31 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
US11508648B2 (en) 2018-06-29 2022-11-22 Intel Corporation Coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards
WO2020000414A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards

Also Published As

Publication number Publication date
NO20024196D0 (en) 2002-09-03
JP2003532294A (en) 2003-10-28
CA2402082A1 (en) 2001-11-01
TW503486B (en) 2002-09-21
WO2001082361A3 (en) 2002-05-16
CN1181524C (en) 2004-12-22
HK1053746A1 (en) 2003-10-31
KR20040004761A (en) 2004-01-14
MY134243A (en) 2007-11-30
NO20024196L (en) 2002-09-03
WO2001082361A2 (en) 2001-11-01
AU2001249879A1 (en) 2001-11-07
CN1426599A (en) 2003-06-25
EP1279193A2 (en) 2003-01-29

Similar Documents

Publication Publication Date Title
US6281046B1 (en) Method of forming an integrated circuit package at a wafer level
US6413799B1 (en) Method of forming a ball-grid array package at a wafer level
US7205178B2 (en) Land grid array packaged device and method of forming same
JP3142723B2 (en) Semiconductor device and manufacturing method thereof
US6344401B1 (en) Method of forming a stacked-die integrated circuit chip package on a water level
US6228676B1 (en) Near chip size integrated circuit package
US7119001B2 (en) Semiconductor chip packages and methods for fabricating the same
US20010000927A1 (en) Semiconductor and flip chip packages and method having a back-side connection
US20080197469A1 (en) Multi-chips package with reduced structure and method for forming the same
US20080237828A1 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
EP2207198A2 (en) Manufacturing method of a semiconductor device
CN101197356A (en) Multi-chip packaging structure and forming method thereof
CN101232008A (en) Multi-die packaging and method thereof
JP2000100851A (en) Semiconductor component and manufacturing method thereof, mounting structure of semiconductor component and mounting method thereof
US6911737B2 (en) Semiconductor device package and method
US6455941B1 (en) Chip scale package
US6339253B1 (en) Semiconductor package
JP2000150557A (en) Semiconductor device and manufacturing method thereof
HK1053746B (en) Method of forming an integrated circuit package at a wafer level
Kurata et al. Over-coated flip-chip fine package development for MCM fabricated with Si IC and GaAs MMIC
HK1052080A (en) Integrated circuit package formed at a wafer level

Legal Events

Date Code Title Description
AS Assignment

Owner name: ATMEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAM, KEN M.;REEL/FRAME:010922/0131

Effective date: 20000418

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20090828