CN100434354C - Round piece class airtight packing technique having low depth-width ratio through hole - Google Patents
Round piece class airtight packing technique having low depth-width ratio through hole Download PDFInfo
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- CN100434354C CN100434354C CNB2006100396682A CN200610039668A CN100434354C CN 100434354 C CN100434354 C CN 100434354C CN B2006100396682 A CNB2006100396682 A CN B2006100396682A CN 200610039668 A CN200610039668 A CN 200610039668A CN 100434354 C CN100434354 C CN 100434354C
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Abstract
The present invention relates to an airtight packaging technique for a wafer level with a low depth-width ratio through hole, which relates to a packaging technique for micro-electromechanical systems. According to a process flow and a design scheme provided by the present invention, the present invention comprises the following steps: deposition, the formation of a cavity for sealing and a V-shaped opening, a photo etching through hole, the formation of an insulating layer, the formation of a resistance welding film, weld and filling. The present invention has the most difficult problem of making a wafer level package directly used as an ultimate outer package that signals on the front side of a cover wafer or on the front side of an MEMS wafer are led to the back side of the cover wafer or to bonding pad on the back side of the MEMS wafer. The present invention aims to seek an airtight packaging technique for a wafer level with a low depth-width ratio through hole, and the aim of achieving airtight packaging for MEMS devices by that a cavity is sealed by metal between the cover wafer and the MEMS wafer and metallic bonding. Simultaneously, MEMS signals are led to the bonding pad on the back side of the cover wafer through a Y-shaped low depth-width ratio through hole and a leading wire.
Description
Technical field
Patent of the present invention relates to a kind of MEMS encapsulation technology of (Micro-Electro-Mechanical System is called for short MEMS), specially refers to a kind of wafer level air-tight packaging technology with low depth-to-width ratio through hole.
Background technology
Along with the development of microelectric technique,, require the air-tight packaging of miniaturization, lightweight, high performance, multifunction, low power consumption and cost degradation for the increasingly stringent that requires of the air-tight packaging technology of MEMS system.Wafer-level MEMS system air-tight packaging is compared with traditional air-tight packaging, have that volume is little, following process is simple, easily and integrated, the low cost and other advantages of other device.With regard to its technology, mainly contain two kinds of packaging technologies at present: the one, the film integrated technique.It deposited thin film on sacrifice layer before discharging in the MEMS micro-structural, remove sacrifice layer by technology etch pit on the film then, deposited thin film again and sealed these technology etch pits, thereby finish the air-tight packaging of MEMS.This technology has simple, the low cost and other advantages of operation, but the film of deposition has only several microns thickness, and this disk section and disk that is difficult in subsequently picks up and waits that assurance stands intact in the operation, and yield rate is lower.And do not have outer lead, need secondary encapsulation, still can not be directly as the final outer package of MEMS device.The 2nd, MEMS disk and lid disk combine by the technology of silicon and Si direct bonding, glass and glass bonding, metal and metal bonding, form air-tight packaging.Wherein, metal and metal bonding technology are the technology that reliability is the highest, applicability is the widest.If outer lead and pad on the lid disk back side or MEMS disk back side cloth just can be used as final outer package and directly use.
Summary of the invention
Allow wafer level packaging directly use as final outer package, the most difficult problem is that the signal in lid disk front or MEMS disk front is guided on the pad at the lid disk back side or the MEMS disk back side.The objective of the invention is to seek a kind of wafer level air-tight packaging technology of the Y of having shape through hole.Promptly seal the purpose that a hole reaches air-tight packaging MEMS device by metal between lid disk and MEMS disk and metal bonding.Simultaneously, by low depth-to-width ratio through hole of " Y " shape and lead-in wire the MEMS signal is guided on the pad at the lid disk back side.
According to technical flow design scheme provided by the present invention, the present invention includes following steps:
1, deposit: the silicon chip two sides is all polished, or directly buy the polishing both surfaces disk, as the lid disk.Grow or deposit silica by oxidation or CVD (chemical vapor deposition) technology on the surface then, use CVD (chemical vapor deposition) deposit silicon nitride again, as the mask of silicon wet etching;
2, sealing forms with cavity and " V " shape opening: again at the two sides resist coating through the lid disk after the above-mentioned processing, the lid disk is passed through the photoetching of double face photoetching machine two sides, etch away the silicon nitride and the silica of expose portion, remove photoresist with wet method or dry method then, use wet etching solution etch silicon again, use cavity in the positive formation sealing of lid disk, form the scribe line cavity overleaf, as " V " part of the low depth-to-width ratio through hole of " Y " shape;
3, photoetching through hole: use the wet etching Solution H
3PO
4(phosphoric acid) or dry method are removed whole silicon nitrides, remove whole silica with HF (hydrofluoric acid) solution or BOE (buffer oxide silicon etch solution), overleaf the positive photoetching through hole vertical component of scribe line cavity correspondence position.
4, form insulating barrier: the dry etching vertical through hole forms the through hole vertical component; Remove photoresist with wet method or dry method, by oxidation or CVD (chemical vapor deposition) technology silicon face growth or deposit silica at the lid disk, as insulating barrier, deposit UBM layer (projection lower metal layer) then.The UBM layer is as plating seed layer and the solder mask material that electrical connection is provided.
5, electroplate: with two sides litho machine two sides photoetching lid disk, electrogilding and scolder are removed photoresist then, form sealing ring, lead-in wire, pad and press welding block on the lid disk;
6, form soldering-resistance layer: photoetching lid disk, produce the soldering-resistance layer figure, wet etching falls the Gold plated Layer and the solder layer of expose portion on the soldering-resistance layer figure, removes photoresist then, and annealing forms soldering-resistance layer.When subsequently lid disk and MEMS disk added thermal weld, solder mask played the effect that resistance system scolder flows everywhere.Also when being welded to packaged MEMS device on the pcb board, the user plays the effect that resistance system scolder flows along lead-in wire at the solder mask on the outer lead.
7, welding: aim at and add thermal weld lid disk and have MEMS (MEMS) disk of corresponding sealing ring and press welding block, form annular seal space and electrical connection, cut the lid disk with wide blade, but do not cut MEMS (MEMS) disk, form wide scribe line, with the Gold plated Layer and the solder layer disconnection of adjacent lid.
8, fill: use liquid insulating material,, fill scribe line, be heating and curing, make Gold plated Layer and solder layer insulation on sidewall silicon and the lid disk as epoxy resin; By MEMS (MEMS) disk after the common chip cutting method cutting welding, obtain single packaged MEMS (MEMS) device then.
Described wet etching solution is KOH (potassium hydroxide) or EPW (ethylenediamine+catechol aqueous solution) or TMAH, or other wet etching solution.
The disc grade chip size sealed package in the formation sealing hole between lid disk and MEMS disk, the lid disk is made up of the through hole vertical component in hole, V-arrangement opening and the V-arrangement opening.The through hole vertical component can be an aperture, also can be rectangular aperture.V-arrangement opening and through hole vertical component are formed Y shape through hole, and it has the geometric feature of low depth-to-width ratio.Through hole can be easy to by sputter and electroplate cover metal level like this.Y shape through hole is to be used for connecting the lead-in wire at the press welding block in lid disk front and the lead-in wire and the lid disk back side and pad.The press welding block in the press welding block in lid disk front and sealing ring and MEMS disk front and sealing ring be by the scolder seal welding of heating, and forms the annular seal space that is electrically connected and protects the MEMS structure of MEMS disk and lid back side pad.The wide blade cuts of lid disk, with the metal level disconnection of adjacent lid, the wide scribe line filling liquid insulating materials after cutting is used for making the metal level insulation on sidewall silicon and the lid disk then.After insulating materials solidified, hermetically sealed MEMS disk was divided into single packaged finished product MEMS device by common scribing.
Than traditional high aspect ratio vias technology, it is few that low depth-to-width ratio through hole manufacturing technology of the present invention has an equipment investment, the advantage that yield rate is high.The manufacturing of lid disk does not need spraying to be coated with or to electroplate photoresist, thereby has reduced equipment investment.
Description of drawings
Fig. 1-8 is a process chart of the present invention.
Among the figure: 1, lid disk, 2, silica and silicon nitride film (SiO
2+ SiN), 3, lid disk back side scribe line cavity, 4, the positive sealing cavity of lid disk, 5, the photoresist that the etching vertical through hole is used (PR), 6, UBM layer (projection lower metal layer), 7, the through hole vertical component, 8, through hole V opening shape part, 9, electroplate with photoresist 10, Gold plated Layer+solder layer, 11, soldering-resistance layer, 12, lead-in wire (Gold plated Layer+solder layer lead portion), 13, pad (Gold plated Layer+solder layer pad portion), 14, sealing ring on the lid disk (Gold plated Layer+solder layer sealing ring part), 15, press welding block on the lid disk (Gold plated Layer+solder layer press welding block part), 16, wide scribe line, 17, press welding block after the welding, 18, sealing ring after the welding, 19, the MEMS disk, 20, press welding block on the MEMS disk, 21, sealing ring on the MEMS disk, 22, common scribe line, 23, liquid insulating material, 24, annular seal space.
The specific embodiment
The wafer-level MEMS air-tight packaging technological process that the present invention relates to is the manufacturing of finishing the lid disk on silicon chip, then with the welding of MEMS disk, and cutting lid disk and fill insulant, last burst.The packaging technology flow process that it comprises may further comprise the steps:
1, deposition process is all polished the silicon chip two sides as shown in Figure 1, or directly buys the polishing both surfaces disk, as the material of lid disk 1.By growth of oxidation or CVD (chemical vapor deposition) technology or deposit silica, CVD (chemical vapor deposition) deposit silicon nitride then is as the mask of silicon wet etching.Wherein silicon nitride is as the mask material of main silicon wet etching, and the effect of silica is as the stress-buffer layer between the silicon of silicon nitride and lid sheet 1.
The formation of 2, sealing usefulness cavity and " V " shape opening as shown in Figure 2, at the two sides of lid disk 1 resist coating, the lid disk is passed through the photoetching of double face photoetching machine two sides, etch away the silicon nitride and the silica 2 of expose portion, remove photoresist then, use KOH, EPW or other wet etching solution etch silicon, at the lid disk 1 positive trapezoidal sealing cavity 4 that forms, form trapezoidal scribe line cavity 3 overleaf.
3, the photoetching through hole is used whole silicon nitrides of wet etching solution removal and silica 2 as shown in Figure 3, lid disk 1 front resist coating 5, and the front lighting of scribe line cavity correspondence position carves through hole vertical component figure overleaf.
4, form insulating barrier shown in Fig. 4 a, dry etching through hole vertical component 7.A part of V-arrangement opening 8 of through hole vertical component 7 and back side scribe line cavity constitutes the low depth-to-width ratio through hole of " Y " shape.Remove photoresist 5, grow or deposit silica at the silicon face of lid disk, as insulating barrier, then by sputtering deposit UBM layer (projection lower metal layer) 6 by oxidation or CVD (chemical vapor deposition) technology.The UBM layer is as plating seed layer and the solder mask material that electrical connection is provided.Fig. 4 b represents be this moment from the top-down vertical view in lid disk 1 back side, wherein sealing is a dotted line with cavity 4, actual can't see.
5, electroplate as shown in Figure 5, at lid disk 1 both sides resist coating 9, photoetching lid disk 1, electrogilding and scolder 10, remove photoresist 9 then, as UBM (projection lower metal layer) layer 6 between mask removal sealing ring 14 and Gold plated Layer+solder layer 10 other parts, on the lid disk, form the sealing ring part 14 of Gold plated Layer+solder layer 10 with Gold plated Layer+solder layer 10.
6, form soldering-resistance layer as shown in Figure 6, at lid disk 1 both sides resist coating, the figure of photoetching soldering-resistance layer 11 is divided into lead portion 12 with Gold plated Layer and solder layer 10, press welding block 15 and pad 13.Etch away the Gold plated Layer and the solder layer 10 of expose portion, remove photoresist then, annealing forms soldering-resistance layer 11.When subsequently lid disk 1 and MEMS disk 19 added thermal weld, solder mask 11 played the effect that resistance system scolder flows everywhere.Solder mask on the lead-in wire 12 (outer lead) at the lid disk back side also plays the effect that resistance system scolder flows along lead-in wire 12 when the user is welded to packaged MEMS device on the pcb board.
7, welding is shown in Fig. 7 a, aims at and adds thermal weld lid disk 1 and have the MEMS disk 19 of corresponding sealing ring 21 and press welding block 20, forms sealing ring 17 after the welding and the press welding block 18 after the welding.Sealing ring 17 after the welding, the sealing of lid disk 1 has constituted annular seal space 24 with the surface of cavity 4 and MEMS disk 19.Cut lid disk 1 with wide blade then, form wide scribe line 16, with the Gold plated Layer of adjacent lid and partly 12 disconnections of lead-in wire of solder layer 10.
Fig. 7 b is depicted as from the three-dimensional view of the top-down single lid in lid disk 1 back side.
Fig. 7 c is depicted as from the three-dimensional view of lid disk 1 positive bottom-up single lid.
Fig. 7 d is depicted as from the three-dimensional view of MEMS disk 19 positive top-down single chips.
8, fill shown in Fig. 8 a,,, fill wide scribe line 16, be heating and curing, make on the lid disk 1 silicon and Gold plated Layer and solder layer 10 insulation as epoxy resin with liquid insulating material 23.By common chip cutting method sliver, form packaged MEMS device then.After being heating and curing, liquid insulating material 23 also can be used as the lead-in wire 12 in insulating materials protection " Y " shape through hole.
Fig. 8 b is depicted as the final single MEMS device three-dimensional view behind the sliver.
Claims (10)
1, a kind of wafer level air-tight packaging technology with Y shape through hole is characterized in that this technological process may further comprise the steps:
A, deposit: with the polishing both surfaces of silicon chip, as lid disk material; Then on the surface by oxidation or chemical vapor deposition growth silica, use the chemical vapor deposition silicon nitride again;
B, sealing form with cavity and " V " shape opening: again at the two sides resist coating through the lid disk after the above-mentioned processing, the lid disk is passed through the photoetching of double face photoetching machine two sides, etch away the silicon nitride and the silica of expose portion, remove photoresist with wet method or dry method then, use wet etching solution etch silicon again, use cavity in the positive formation sealing of lid disk, form the scribe line cavity overleaf, as " V " part of " Y " shape through hole;
C, photoetching through hole: remove whole silicon nitrides with wet etching solution phosphoric acid or dry method, remove whole silica, overleaf the positive photoetching through hole vertical component of scribe line cavity correspondence position with hydrofluoric acid solution or buffer oxide silicon etch solution;
D, formation insulating barrier: the dry etching vertical through hole forms the through hole vertical component; Remove photoresist with wet method or dry method, by oxidation or chemical vapor deposition method silicon face growth or the deposit silica at the lid disk, as insulating barrier, deposit projection lower metal layer then is as plating seed layer with the solder mask material of electrical connection is provided;
E, plating: with two sides litho machine two sides photoetching lid disk, electrogilding and scolder form sealing ring, press welding block, lead-in wire and pad;
F, formation soldering-resistance layer: photoetching lid disk, produce the soldering-resistance layer figure, wet etching falls the Gold plated Layer and the solder layer of expose portion on the soldering-resistance layer figure, removes photoresist then, and annealing forms soldering-resistance layer;
G, welding: aim at and add thermal weld lid disk and have the MEMS disk of corresponding sealing ring and press welding block, form annular seal space and electrical connection, cut the lid disk, form wide scribe line, with the Gold plated Layer and the solder layer disconnection of adjacent lid with wide blade;
H, filling: use liquid insulating material, fill scribe line, be heating and curing, make Gold plated Layer and solder layer insulation on sidewall silicon and the lid disk; By the MEMS disk after the common chip cutting method cutting welding, obtain single packaged mems device then.
2, have the wafer level air-tight packaging technology of Y shape through hole according to claim 1, it is characterized in that: described lid disk has through hole vertical component, Gold plated Layer+solder layer, the solder mask that seals with in cavity, V-arrangement opening and the V-arrangement opening; The through hole vertical component is aperture or rectangular aperture.
3, have the wafer level air-tight packaging technology of Y shape through hole according to claim 1, it is characterized in that: the wet etching solution in the step (b) is potassium hydroxide or the ethylenediamine+catechol aqueous solution or TMAH.
4, as having the wafer level air-tight packaging technology of Y shape through hole as described in the claim 2, it is characterized in that: utilize and fill metal in sputter, electroplating technology " Y " shape through hole on the lid disk, make " Y " shape through hole have conducting function.
5, as having the wafer level air-tight packaging technology of Y shape through hole as described in the claim 2, it is characterized in that: utilize sputter, photoetching, plating, etching technics on the lid disk, to form lead-in wire, press welding block, sealing ring, pad.
6, as having the wafer level air-tight packaging technology of Y shape through hole as described in the claim 2, it is characterized in that: " Y " shape through hole on the lid disk, lead-in wire, press welding block interconnect the press welding block in MEMS disk front and the pad at the lid back side.
7, the wafer level air-tight packaging technology that has Y shape through hole according to claim 1, it is characterized in that: in the described step (g), lid disk and MEMS disk utilize the scolder of electroplating in the heating steps (e) on the lid disk to finish sealing ring welding and press welding block welding.
8, have the wafer level air-tight packaging technology of Y shape through hole according to claim 1, it is characterized in that: the sealing of lid disk has constituted the annular seal space of protecting mems structure with the front surface and the sealing ring of cavity, MEMS disk.
9, have the wafer level air-tight packaging technology of Y shape through hole according to claim 1, it is characterized in that: in step (g), after the welding of lid disk and MEMS disk is finished, with wide blade cuts lid disk.
10, the wafer level air-tight packaging technology that has Y shape through hole according to claim 1, it is characterized in that: in the described step (h), after with wide blade cuts lid disk, fill wide scribe line with liquid insulating material, be used for making the silicon and the metal level insulation of lid disk, after insulating materials solidified, welding MEMS disk well was by the scribing sliver.
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| CNB2006100396682A CN100434354C (en) | 2006-04-07 | 2006-04-07 | Round piece class airtight packing technique having low depth-width ratio through hole |
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| CNB2006100396682A CN100434354C (en) | 2006-04-07 | 2006-04-07 | Round piece class airtight packing technique having low depth-width ratio through hole |
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| CN100434354C true CN100434354C (en) | 2008-11-19 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102089251B (en) * | 2008-07-16 | 2014-06-11 | 费罗公司 | Hot-melt sealing glass compositions and methods of making and using the same |
| CN101955152B (en) * | 2009-07-21 | 2012-04-18 | 深迪半导体(上海)有限公司 | Method of wafer-level airtight package with inverted Y-shaped through hole |
| CN102234830B (en) * | 2010-05-06 | 2014-04-16 | 台湾积体电路制造股份有限公司 | Electroplating apparatus and method for electroplating conducting layers on substrate |
| CN104098067B (en) * | 2014-08-01 | 2016-08-24 | 上海集成电路研发中心有限公司 | A kind of body silicon microelectromechanicgyroscope system MEMS structure continues the method for front technique |
| CN107986229B (en) * | 2017-12-04 | 2020-09-29 | 成都振芯科技股份有限公司 | Opening device of micro-electro-mechanical device and preparation multiplexing method thereof |
| CN111924795B (en) * | 2020-07-17 | 2021-06-22 | 诺思(天津)微系统有限责任公司 | Device packaging module, packaging method and electronic device with module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575245A (en) * | 1991-09-11 | 1993-03-26 | Nippon Avionics Co Ltd | Printed wiring board |
| JP2001237334A (en) * | 1999-12-15 | 2001-08-31 | Asulab Sa | Method of airtightly encapsulating microsystem in situ |
| CN1426599A (en) * | 2000-04-25 | 2003-06-25 | 爱特梅尔股份有限公司 | Method for forming integrated circuit package at wafer level |
| CN1463911A (en) * | 2002-06-25 | 2003-12-31 | 祥群科技股份有限公司 | Microcomputer electric component chips level packaging apparatus |
-
2006
- 2006-04-07 CN CNB2006100396682A patent/CN100434354C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575245A (en) * | 1991-09-11 | 1993-03-26 | Nippon Avionics Co Ltd | Printed wiring board |
| JP2001237334A (en) * | 1999-12-15 | 2001-08-31 | Asulab Sa | Method of airtightly encapsulating microsystem in situ |
| CN1426599A (en) * | 2000-04-25 | 2003-06-25 | 爱特梅尔股份有限公司 | Method for forming integrated circuit package at wafer level |
| CN1463911A (en) * | 2002-06-25 | 2003-12-31 | 祥群科技股份有限公司 | Microcomputer electric component chips level packaging apparatus |
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