WO2002017392A2

WO2002017392A2 - Polymer redistribution of flip chip bond pads

Info

Publication number: WO2002017392A2
Application number: PCT/US2001/026436
Authority: WO
Inventors: Richard H. Estes
Original assignee: Polymer Flip Chip Corporation
Priority date: 2000-08-24
Filing date: 2001-08-24
Publication date: 2002-02-28
Also published as: WO2002017392A3

Abstract

An electrical interconnection structure for a flip chip is produced for a flip chip having a plurality of chip bond pads in electrical connection with an electronic circuit, whit the chip bond pads provided on a first face of the flip chip. Electrically-conductive polymer bump bond pads are formed on the first face of the flip chip in an arrangement selected for electrical interconnection of the flip chip with a substrate. A plurality of electrically-conductive polymer redistribution traces are formed on the first face of the flip chip, each trace electrically connecting a chip bond pad to a bump bond pad. The electrically-conductive polymer bump bond pads and redistribution traces can be provided together of a common patterned electrically-conductive polymer layer by, e.g., stencilling or screen printing, to enable in one geometrically defined layer bot redistribution traces and interconnection bump bond pads. Historically, redistribution traces and bump bond pads have been provided as a metal layer, e.g., an aluminium layer, formed by, e.g., a sputtering or other metal deposition process, and geometrically defined by a separate photolithography technique. Employing an electrically-conductive polymer layer rather than a metal layer, the invention overcomes the limitations of a metal layer and expands the range of applications that are addressed by a flip chip bond pad redistribution configuration.

Description

POLYMER REDISTRIBUTION OF FLIP CHIP BOND PADS

BACKGROUND OF THE INVENTION

This invention relates generally to methods for electrically connecting a flip chip to a substrate, and more particularly relates to flip chip bond pad configurations for making such a connection. Flip chip mounting is an increasingly popular technique for directly electrically connecting a semiconductor integrated circuit chip, or die, to a substrate such as a circuit board. In this technique, the active face of the chip is mounted face down, or "flipped" on the substrate. The electrical bond pads on the flip chip are aligned with corresponding electrical bond pads on the substrate, with the chip and substrate bond pads electrically connected by way of an electrically-conductive material, known generally as an interconnection bump, provided on the bond pads.

The flip chip mounting technique eliminates the use of bond wires between a chip or chip package and a substrate, thereby providing increased reliability of the chip-to-substrate bond. The flip chip mounting technique generally also provides a reduced chip footprint on a substrate, minimizes overall chip geometry and weight, and accommodates increased signal speeds. As a result of these advantages, it has become desirable, for many applications, to adapt original wire bond chip layout configurations to flip chip mounting layout configurations.

Traditional wire bonding techniques for mounting a chip on a substrate employ an arrangement of interconnection bond pads that are typically located along the perimeter of the chip. Such a perimeter bond pad arrangement is generally required to enable attachment of bond wire from the chip to a substrate. The perimeter bond pads are characteristically of a relatively small pitch, which can be readily accommodated by the fine diameter that is typical of bonding wire. In contrast, flip chip interconnection techniques do not limit bond pad location to a chip perimeter. Flip chip bond pad arrays can instead be distributed across a chip surface in a convenient configuration. However, the pitch of a flip chip bond pad array generally must account for the diameter and height of interconnection bumps to be formed on the bond pads; generally, the diameter of an interconnection bump can be several times that of a bonding wire.

Due to these distinct requirements of bond pad arrangements for wire bonding and flip chip techniques, the conversion from wire bond to flip chip interconnect technology has often required a full redesign of a chip circuit layout. It has been shown, however, that such a redesign can be avoided by redistributing chip bond pads from an original peripheral wire bond arrangement to a flip chip array configuration. Such a redistributed bond pad arrangement can accommodate a flip chip interconnection technique while at the same time preserving an original chip layout and input/output circuit configuration that was intended for a wire bonding interconnection technique.

Redistribution of bond pads for conversion from wire bond to flip chip bond pad arrangement is also frequently employed to extend the useful life of older pick and place equipment configurations as well as printed circuit board designs. Older pick and place equipment typically cannot accommodate the increasingly smaller pitch of wire bond pad configurations employed by newer chip designs. Similarly, older printed circuit board layout designs often cannot accommodate the smaller wire bond pad pitch of new chip designs. Redistribution of a small pitch wire bond pad arrangement to a larger pitch flip chip bond pad arrangement is an effective and popular technique for overcoming the pitch limitations of older equipment and printed circuit board designs.

In a typical bond pad redistribution process, metal redistribution routing traces are provided between original chip wire bonding pads and redistributed flip chip bond pad locations. Redistributed metal flip chip bond pads are typically formed of a metal layer that is common with that of the metal routing traces; typically the metal layer consists of, e.g., aluminum, or other metal, such as copper or gold. A protective passivation layer is typically provided over the metal routing traces, with the redistributed flip chip bond pads left exposed for formation of interconnection bumps thereon. An additional passivation layer can also be provided under the metal redistribution routing traces to passivate the chip.

Generally, a metal sputtering, electroplating, chemical vapor deposition (CVD), or evaporation process is employed to produce the metal redistribution trace and bond pad layer, with photolithographic and etch techniques employed to define the geometry of the bond pads and traces in the layer. These steps are most significant in determining the process cost and process time required for a bond pad redistribution process, due to the limited capacity of most metal deposition equipment and the limited capacity and process cost of photolithographic metal patterning and etch processes. The efficiency and applicability of bond pad redistribution processes are therefore fundamentally constrained by the conventional techniques employed for producing redistributed metal bond pads and metal redistribution traces.

SUMMARY OF THE INVENTION The invention provides processes that produce a highly effective polymer redistribution configuration which overcomes the limitations of conventional metal redistribution configurations. In the invention, an electrical interconnection structure for a flip chip is produced by providing a flip chip having a plurality of chip bond pads in electrical connection with an electronic circuit, with the chip bond pads provided on a first face of the flip chip. Electrically-conductive polymer bump bond pads are formed on the first face of the flip chip in an arrangement selected for electrical interconnection of the flip chip with a substrate. A plurality of electrically- conductive polymer redistribution traces are formed on the first face of the flip chip, each trace electrically connecting a chip bond pad to a bump bond pad. In a preferred embodiment, the electrically-conductive polymer bump bond pads and redistribution traces are provided together of a common patterned electrically-conductive polymer layer by, e.g., stenciling or screen printing a polymer layer.

The electrically-conductive polymer redistribution layer of the invention enables, in one geometrically defined layer, both redistribution traces and interconnection bump bond pads on a flip chip. Historically, these redistribution traces and bump bond pads have typically been provided as a single metal layer, e.g., an aluminum layer, formed by sputtering, evaporation, or other metal deposition process, and geometrically defined by a separate photolithographic technique. By employing an electrically-conductive polymer layer rather than a metal layer, the invention overcomes the limitations inherent in use of a metal layer and expands the range of applications that are addressed by a bond pad redistribution configuration. In embodiments provided by the invention, the arrangement of electrically-conductive polymer bump bond pads can be located centrally on the flip chip relative to the chip bond pads. Auxiliary bump bond pads can be included in the arrangement of bump bond pads for, e.g., enhancing the mechanical integrity of the flip chip. Electrically-conductive polymer bumps can be provided on the bump bond pads by, e.g., stenciling, and interconnected between the bump bond pads and bond pads of the substrate. Alternatively, the bump bond pads of the flip chip can be directly interconnected to substrate bond pads.

A dielectric polymer layer can be formed on the substrate, with the bond pads of the substrate left exposed, and then the polymer bumps bonded to the substrate bond pads. Alternatively, a dielectric polymer layer can be formed on the flip chip, with the polymer bumps on the bump bond pads left exposed, and then the polymer bumps bonded to the substrate bond pads. Preferably, in either of these scenarios, the dielectric polymer layer on the flip chip or the substrate is provided of a thickness selected to eliminate void space between the flip chip and the substrate when the polymer bumps are bonded to the substrate bond pads. In a further technique provided by the invention, a dielectric polymer layer can be formed on the substrate, with bond pads of the substrate covered by the polymer layer. Polymer bumps on the bump bond pads are then pushed through the substrate dielectric ^* polymer layer to directly interconnect the bumps tot he substrate bond pads.

A dielectric polymer chip passivation layer can be provided on the first face of the flip chip under the electrically-conductive polymer bump bond pads and redistribution traces, with the chip bond pads exposed through the chip passivation layer for the electrical connection of the chip bond pads to the redistribution traces. Similarly, a dielectric polymer trace passivation layer can be provided on the first face of the flip chip over the electrically-conductive polymer redistribution traces, with the bump bond pads exposed through the trace passivation layer. Further, a dielectric polymer protective layer can be provided on a second face of the flip chip opposite the first flip chip face.

The electrically-conductive polymer bump bond pads and redistribution traces can be provided as, e.g., an electrically-conductive thermoset. The dielectric polymer trace passivation layer can be provided as, e.g., a thermoplastic or a thermoset layer. The electrically-conductive polymer bumps can be provided as, e.g., thermoplastic bumps.

In forming the interconnection structure of the invention, the flip chip can be provided on a semiconductor wafer that includes a plurality of flip chips. A last step can be provided for dicing the wafer to produce separated flip chips. The electrical interconnection structure of the invention can be employed in a wide range of chip-substrate configurations where it is desired to efficiently redistribute an original chip bond pad arrangement to an adjusted arrangement that accommodates a desired interconnection configuration. The electrical interconnection structure of the invention further can be applied to a wide range of structures beyond flip chips, to any structure for which bond pad redistribution is desired. For example, substrates such as printed circuit boards, unconventional substrates such as smart cards and other electronic chip support platforms, multi-chip modules, chip packages, conventional chip configurations, 3-D stacks of chips, and other substrates having bond pads can be accommodated by the processes of the invention to enable electrical interconnection to a second substrate or other platform. The polymer redistribution technique and resulting interconnection structure of the invention is therefore not limited to flip chips, but instead can be widely applied to various substrate and platform configurations, e.g., where on a first substrate bond pads are redistributed by polymer redistribution traces to polymer bump bond pads for electrical interconnection to a second substrate.

Polymer deposition techniques, and particularly screen printing and stenciling techniques, significantly enhance the efficiency and cost effectiveness of the polymer redistribution process of the invention over the multi-step deposition, pattern, and etch steps required of conventional metal-based redistribution processes. Other features and advantages of the invention will be apparent from the following detailed description and accompanying drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A-1D are schematic cross-sectional views of process steps provided by the invention for producing a redistributed polymer bond pad configuration on a flip chip;

Fig. 2 is a schematic plan view of an example bond pad redistribution configuration that can be produced by the redistribution processes of the invention;

Figs. 3A-3C are schematic cross-sectional views of steps in a first example process provided by the invention for electrically interconnecting redistributed polymer bond pads of a flip chip to bond pads of a substrate; Figs. 4A-4C are schematic cross-sectional views of steps in a second example process provided by the invention for electrically interconnecting redistributed polymer bond pads of a flip chip to bond pads of a substrate; Figs. 5A-5C are schematic cross-sectional views of steps in a third example process provided by the invention for electrically interconnecting redistributed polymer bond pads of a flip chip to bond pads of a substrate;

Figs. 6A-6C are schematic cross-sectional views of steps in a fourth example process provided by the invention for electrically interconnecting redistributed polymer bond pads of a flip chip to bond pads of a substrate; and

Figs. 7A-7B are schematic cross-sectional views of steps in a fifth example process provided by the invention for electrically interconnecting redistributed polymer bond pads of a flip chip to bond pads of a substrate.

DETAILED DESCRIPTION OF THE INVENTION The polymer bond pad redistribution technique described below is preferably carried out at the wafer level, i.e., the polymer redistribution configuration is to be simultaneously formed on multiple integrated circuit chips that are together provided on a single fabrication wafer in the conventional manner. Process efficiency and cost effectiveness are significantly enhanced by such. It is recognized, however, that the polymer redistribution technique of the invention can be carried out on individual die, on substrates, or on other suitable platforms that include bond pads to be redistributed. Referring to Fig. 1A, there is shown a cross-sectional view of an integrated circuit chip 10 for which bond pad redistribution is to be carried out. While a single integrated circuit chip is shown in the figures for clarity, it is to be recognized that such is not limiting, and that preferably, the chip is one of many included on a wafer and being processed simultaneously.

As shown in Fig. 1A, the semiconductor chip 10 includes on a first face 12 bond pads 14 . In the conventional manner, the bond pads 12 are provided for making electrical connection between circuits provided on the chip and, e.g., a substrate or other platform on which the chip is to be mounted. With the bond pads provided on the first face of the chip, the chip is to be mounted in flip chip fashion, i.e., the first face 12 of the chip is to be flipped to meet the face of a substrate or other platform.

In a first process step, it is preferred in accordance with the invention that the quality of the chip bond pads 14 be optimized for enabling low and stable contact resistance when electrically connected with a substrate.

Specifically, if the original bond pads 14 are formed of aluminum or other metal that is easily oxidized, it is preferred that any oxide present be etched away, e.g., by conventional sputter or chemical etch techniques. Once the oxide is removed, a layer 16 of a non-oxidizing metal, e.g., a noble metal, is formed on the bond pads 14. Sputtering, chemical vapor deposition, electroplating, electro-less deposition such as zincating, or other technique can be employed to form the non-oxidizing metal layer 16 in the conventional manner. The non-oxidizing metal layer can be provided as silver, gold, copper, palladium, or other appropriate metal. If the original bond pads 14 are themselves formed of a suitable non-oxidizing metal, then the additional bond pad metal layer is not required.

Referring to Fig. IB, in a next process step, a secondary dielectric chip passivation layer 18 is provided on the chip 10. Conventionally, integrated circuit chips are provided with a primary dielectric passivation layer applied over the front face of a chip to protect metal interconnect layers on the chip. The secondary passivation layer 18 can be provided over the primary dielectric passivation layer for applications where electrical interference or signal cross-talk between, e.g., high-speed memory, logic, or signal processing circuits is of concern, or where additional moisture and/or mechanical protection is desired.

In accordance with the invention, the secondary dielectric passivation layer 18 is preferably provided in a configuration that planarizes the chip surface, in the manner shown in Fig. IB, with the chip bond pads 14/16 left exposed. While it is preferred that the secondary passivation layer 18 be substantially flush with the upper surface of the bond pads, such is not required; the top surface of the passivation layer can be lower or can be higher than the top surface of the bond pads. The secondary passivation layer thickness is preferably between about 1 micron and about 75 microns; a thickness of between about 10 microns and about 15 microns can be preferable for many applications. It is to be recognized that if the existing primary dielectric passivation provided with the chip sufficiently meets planarization and/or passivation requirements, than a secondary dielectric passivation layer is not required.

Preferably, the secondary dielectric passivation layer is formed of a suitable organic or inorganic material, e.g., a polymer resin, including, e.g., a thermoplastic, a thermoset, a B-stage thermoset, a hot melt, a mixture of such compounds, or other material, e.g., a polyimide, that is a dielectric and that preferably is moisture resistant and mechanically stable.

If the pitch of the original bond pads 14/16 allows, it is preferable that the passivation layer 18 be formed by a screen printing or stenciling process, such processes being highly efficient, one-step application techniques that inherently leave the bond pads exposed as the layer is formed. If a stenciling or screen printing process is employed, the passivation layer material is preferably provided as, e.g., EPO-TEK® 600-3, EPO-TEK® 600- 4, EPO-TEK® 600, EPO-TEK® 600M, EPO-TEK® TE 179-8, EPO-TEK® TE179-9, or EPO-TEK® TE179-10, all available from Epoxy Technology,

Billerica, MA.

The invention contemplates a wide range of alternative passivation layer formation processes. For example, the passivation layer material can be applied to the chip by spin-coating, dispensing, spraying, dipping, or other suitable technique, or can be applied as a preformed film. If the passivation layer material is applied to the chip as a blanket coat, then a lithographic technique, a direct etch technique, or other suitable process for exposing the top surface of the bond pads, is to be employed.

For example, a photoimageable dielectric such as Epo-Tek 8000 can be applied by, e.g., spin-coating, to the chip, with a shadow mask employed to mask the bond pads from blanket radiation exposure to polymerize exposed layer regions. The unpolymerized dielectric regions over the bond pads are then stripped in the conventional manner to expose the bond pads. In a further example, a blanket passivation layer is processed by a laser etch technique, employing, e.g., an excimer laser, for opening regions over the bond pads to expose the bond pads. The invention is not limited to a particular passivation layer formation process; all that is required is exposure of the bond pads through the layer.

Referring to Fig. IC and to Fig. 2, in a next step, an electrically- conductive polymer layer 20 is formed on the passivation layer in a redistribution pattern that provides electrical redistribution traces 22 from the location of the chip bond pads 14/16 to the location of redistributed, interconnection bump bond pads 24. The redistributed interconnection bump bond pads 24 can be located at any convenient location on the chip 10, e.g., in a general area array pattern as shown in Fig. 2. The redistributed bump bond pads can be located on the chip either more centrally or more peripherally than the original chip bond pads 14/16. Auxiliary bond pads 26 can also be provided on the chip, at any suitable locations, for enhancing the mechanical strength of the chip, and for distributing and minimizing mechanical and thermal stress at points across the chip. In addition, supplemental bond pads 28 can be provided at any suitable locations on the chip for making electrical connections to chip circuitry points that could not be accessed by the original chip bond pad configuration.

The redistribution traces 22 can be provided in any convenient geometry and can take any convenient path for making electrical connection between the original chip bond pads and the redistributed interconnection bump bond pads. Similarly, the bump bond pads can take on any suitable geometry, e.g., circular, rectangular, octagonal, or other suitable geometry. For many applications, it can be preferable to optimize the geometry of the bump bond pads, the geometry of the redistribution traces, and the paths of the redistribution traces to meet operational and performance goals. For example, bump bond pad and trace geometries can be selected to equalize capacitance and resistance to thereby substantially minimize skew and crosstalk between signals carried on the traces to the bond pads. Such a control technique is described by Shenoy et al., in U.S. No. 6,025,647, issued February 15, 2000, the entirety of which is hereby incorporated by reference. Similarly, shield traces can be included between signal traces for minimizing capacitive coupling between the signal traces, in the manner described by Shenoy et al., in U.S. No. 5,994,766, issued November 30, 1999, the entirety of which is hereby incorporated by reference. In general any reasonable geometry, size, and location of the bump bond pads and redistribution traces can be accommodated by the polymer redistribution layer 20.

In a process preferred in accordance with the invention, the electrically-conductive polymer redistribution layer is both applied and geometrically defined in one step by screen printing or stenciling of the polymer onto the primary or secondary passivation layer. In an example screen printing process, the selected electrically-conductive polymer material is squeegeed through a wire mesh screen using, e.g., a metal or polymer-based squeegee, onto the passivation layer. The screen can be formed in the conventional manner of, e.g., stainless steel or other metal, or a plastic. For many applications, a metal squeegee can be preferred for its ability to enable polymer deposition in a manner more efficient than that of a plastic squeegee.

In the conventional manner, the diameter of the wire mesh is to be selected based on the selected thickness of the polymer redistribution layer.

The polymer redistribution layer is preferably provided with a thickness of between about 25 microns and about 75 microns; for many applications, a polymer redistribution layer of about 50 microns can be preferred. An emulsion pattern is provided on the screen to define the geometry of the redistribution traces as well as the geometry of the redistributed bump bond pads. The emulsion pattern thickness, like the wire mesh diameter, is preferably selected, in the conventional manner, based on the selected redistributed layer thickness. If the wire mesh is too large for a desired polymer layer thickness, or if the emulsion is too thin for the desired polymer layer thickness, gaps in the polymer layer can be formed at the location of a cross-over of the mesh wires. The general rheology of a selected polymer material must also be considered with regard to the screen wire diameter and the screen emulsion thickness. With proper selection of wire mesh diameter and emulsion thickness for a selected polymer layer thickness, void-free coverage can be achieved. In a stencil operation provided by the invention for applying the polymer redistribution layer, the polymer is pushed by a squeegee through open holes provided in a metal stencil onto the passivation layer. The metal stencil thickness is selected, in the conventional manner, based on the selected polymer layer thickness. The squeegee can be formed of metal or plastic. The openings in the stencil can be formed by, e.g., a subtractive chemical etch process, a subtractive laser etch process, an additive electroforming process, or other suitable stencil patter forming technique. For many applications, electroforming can be the preferred process based on its ability to produce high-definition patterns. For many applications, screen printing can be preferable to stenciling, because screen printing generally is found to provide superior print definition and print uniformity. Furthermore, screen printing requires less print pressure than stenciling, and enables more material to be deposited in one print operation. Conversely, for applications where a relatively thin polymer redistribution layer is to be employed, stenciling can be preferable to eliminate the formation of voids that can be formed at cross-over locations of a screen printing wire mesh. Stenciling operations also can be expected to be more reliable over the life of a production line in that unlike a mesh screen, a metal stencil generally does not clog with material being stenciled and exhibits a longer operation time to fatigue. The stenciling or screen printing process can be carried out in one pass or in multiple passes. Referring to Figs. 1B-1C, if the primary or secondary passivation layer 18 is substantially flush with the original chip bond pads 14/16, then a single screening or stenciling pass can be sufficient, but if the surface of the primary or secondary passivation layer is lower or higher than the top surface of the original chip bond pads 14/16, then multiple passes may be preferable. If the pitch of the redistribution bump bond pads is relatively small, it is then preferable to form the polymer redistribution layer in one stencil or screen print pass, to minimize the possibility of shorting of material between two pads during secondary passes.

The invention contemplates a wide range of alternative techniques for producing the electrically-conductive polymer redistribution layer. The techniques described above with regard to the passivation layer formation, e.g., spin-coating, dispensing, dipping, or spraying of a blanket coat layer, can here be employed also. Transfer print, pad print, stamp print, roller print, and other printing techniques can also be employed. Photolithography and laser etching can be employed to define the redistribution trace and bump bond pad geometries in a blanket coat layer. Alternatively, the trace and bump bond pad geometries can be directly formed by, e.g., a direct writing process of the polymer material. The invention is not limited to a particular polymer redistribution layer formation technique. All that is required is a technique that enables formation of polymer redistribution traces and polymer redistribution bump bond pads.

Whatever polymer deposition technique is selected, the electrically- conductive polymer redistribution layer material can be provided as, e.g., a thermoset, a B-stage thermoset, a thermoplastic, or other suitable epoxy or resin paste, including a mixture of compounds. Electrically-conductive particles, flakes, or other form of an electrically-conductive material, e.g.,

Ag, Ag-Pd, Au, Cu, Ni, Sn, Pb, In, or other material, is preferably provided mixed with the polymer for electrical conductivity. Example electrically- conductive polymers include EPO-TEK® H20E-PFC, EPO-TEK® E2101, EPO-TEK® E4110PFC, EPO-TEK® K5022-115Be, EPO-TEK® EE149-6, EPO-TEK® EG107, all available from Epoxy Technology, Billerica MA; or other suitable material.

It is preferable that the viscosity and the specific gravity of a selected polymer redistribution layer material be tailored for a selected redistribution layer application technique. For screen printing and stenciling operations, the polymer preferably is characterized by relatively high viscosity and thixotropy. For dispensing operations, the polymer preferably is characterized by relatively low to medium viscosity and by relatively high thixotropy. For transfer printing and for spin coating operations, the polymer preferably is characterized by relatively low viscosity and by relatively medium thixotropy. After the electrically-conductive polymer material is applied to the chip, the polymer material is preferably at least partially polymerized, or more preferably fully polymerized, or is dried if provided as a thermoplastic or hot melt material. Polymerizing of the polymer can be accomplished by exposure to, e.g., heat, radiation such as UV, microwave, or other radiation, or by ambient conditions, in the conventional manner.

As just explained, the electrically-conductive polymer redistribution layer of the invention provides in one geometrically defined layer both redistribution traces and interconnection bump bond pads on the chip. Historically, these redistribution traces and bump bond pads have typically been provided as a single metal layer, e.g., an aluminum layer, formed by sputtering, evaporation, or other metal deposition process, and geometrically defined by a separate photolithographic technique. By employing an electrically-conductive polymer layer rather than a metal layer, the invention overcomes the limitations inherent in use of a metal layer and expands the range of applications that are addressed by a bond pad redistribution configuration. For example, given that the chip passivation layers are polymeric, the polymer redistribution layer enables a thermally-matched system, i.e., a substantially uniform coefficient of thermal expansion (CTE) provided across the chip and through the thickness of the layers on the chip. This CTE match substantially eliminates thermal stresses that could cause fracture of the chip from a substrate during operation. CTE matching can be further enhanced in accordance with the invention by employing electrically-conductive polymer bumps in the manner described below.

For many applications, a metal redistribution layer cannot withstand the temperature required of one or more thermal processing steps. In contrast, the polymer redistribution layer can generally withstand a range of processing temperatures. In addition, the polymer material can be selected as, e.g., a thermoplastic, for enabling reworkability of a chip mounting on a substrate. More importantly for many applications, a metal layer cannot be deposited universally on any selected material; rather, a surface pretreatment such as plasma ashing is often required to enable adhesion of a metal to an underlying material. In contrast, most polymer materials can in general adhere to any underlying layer without the need for an initial pretreatment preparation. As explained previously, metal deposition equipment is generally characterized by a relatively limited processing capacity. Equipment for the photolithographic patterning and etching of a deposited metal layer further is generally characterized by a limited process capacity, and requires additional processing steps beyond deposition. In contrast, most polymer deposition techniques, and particularly stenciling and screen printing techniques, are characterized by a relatively high through-put rate. In addition, stenciling and screen printing techniques eliminate the need for separate photolithographic and etch steps because these techniques inherently geometrically define redistribution traces and bond pads at the time of polymer deposition. As a result, polymer deposition techniques, and particularly screen printing and stenciling techniques, significantly enhance the efficiency and cost effectiveness of the polymer redistribution process of the invention over the multi-step deposition, pattern, and etch steps required of conventional metal-based redistribution processes.

Referring to Fig. ID, with the electrically-conductive polymer redistribution layer in place, in a next, optional step of the process, a dielectric redistribution trace passivation layer can be formed to cover and protect the redistribution traces 22 and exposed regions of the secondary passivation layer 18. The bump bond pads 24 of the redistribution layer are preferably rendered exposed through the redistribution passivation layer, for application of interconnection bumps to the bond pads in a later process step. A redistribution passivation layer is not required by the invention; e.g., where an underfill material is to be provided between the flip chip and a substrate, the passivation layer may not be required. It is to be understood that the redistribution trace passivation layer is optional and can be preferred for applications where a high degree of environmental protection of flip chip interconnections are required.

The redistribution trace passivation layer, if employed, preferably is dielectric and is characterized by a relatively high glass transition temperature, a relatively high degradation temperature, good adhesion properties, and good moisture and chemical resistance. In accordance with the invention, the redistribution trace passivation layer preferably is a dielectric polymer layer, e.g., a thermoset, a B-stage thermoset, a thermoplastic, or other suitable organic resin material. Example suitable materials include EPO-TEK® 600, EPO-TEK® 600M, EPO-TEK® 688 PFC, EPO-TEK® K5022-115BT2, EPO-TEK® TE153-7, EPO-TEK® TE154-8, all available from Epoxy Technology, Incorporated, of Billerica, MA. While a polymer resin is preferred in accordance with the invention for enabling the thermal match and other advantages discussed above, such is not required; other dielectric materials such as an oxide or nitride can be employed. If a dielectric polymer resin is employed, the polymer layer preferably is applied by one of the processes described above in connection with the secondary passivation layer and the redistribution layer; screen printing or stenciling are application processes that are particularly preferred for their ability to apply and geometrically define the layer in a single step. Other processes that enable dielectric application in a manner that leaves the redistributed bump bond pads uncoated and exposed can also be preferred for many applications. Whatever application technique is employed, it is preferred that, as shown in Fig. ID, the edges of the bump bond pads 24 be slightly covered by the passivation layer 26 to seal the edges. An edge overlap of between about 5% and about 10% can be preferred for many applications. The redistribution trace passivation layer 26 can be formed in a single application step, or in multiple application steps as needed to enable a planarized topology like that shown in Fig. ID, which can be preferable for many applications. Whatever application process is employed, the layer preferably is partially or fully polymerized, or dried, as- appropriate, if required for the material selected.

With this optional passivation step completed, the polymer redistribution configuration is in place, with redistributed interconnection bump bond pads provided for flip chip mounting and electrical connection between the chip and a substrate. If the chip has been processed as one of a plurality of chips provided on a single semiconductor wafer, the wafer is then diced in the conventional manner for individual placement of the chips on substrates. As referred to herein, a substrate is meant as, e.g., a printed circuit board; a chip module, package, or other platform; a wafer; an electronic circuit die such as a conventional chip or a flip chip; a smart card or other non-standard chip platform; or other structure to which a chip is to be electrically attached.

The invention contemplates a wide range of chip-substrate interconnection techniques employing the polymer redistribution chip configuration of the invention. In one example technique, referring to Fig. 3A, interconnection bumps 28 are next formed on the bump bond pads 24 of the chip. In an alternative process step, the interconnection bumps 28 are formed on the bond pads 30 of the substrate 32 rather than the bump bond pads 24 of the chip. In either case, the interconnection bumps 28 preferably comprise an electrically-conductive polymer resin, and can be formed of the electrically-conductive polymer resin that was employed as the redistribution layer. Thermoset, B-stage thermoset, thermoplastic, and other such resins can be employed as polymer bump material; thermoset bump materials can be preferred for many applications. In general, any of a wide range of electrically-conductive epoxy paste materials can be employed.

With the use of such a material, thermal match through the thickness of the interconnection between a chip and a substrate is provided, with the advantages discussed above. Although not preferred, solder or other conventional bump material can also be employed.

The interconnection bumps are preferably generally the size of the bond pads, but can be slightly larger or smaller, depending on the pitch of the bond pads in the usual manner. The bump formation process is preferably a screen printing or stenciling process like those described above. Alternative bump formation processes are also contemplated by the invention, including blanket coating and photolithography or direct etch, direct write, or other bump formation process. As explained above, stenciling or screen printing can be preferred for their ability to apply and geometrically define bumps in a single step.

Referring to Fig. 3B, in an example process where the bumps are formed on the chip bond pads, the chip is then flipped and the bumps 28 are aligned with bond pads 30 of a substrate 32 to which the chip is to be electrically connected. Heat and pressure are applied to the configuration to adhere the bumps between the chip and substrate bond pads. For example, a temperature of between about 150°C-160°C, and a pressure of less than about .1 kg can be applied to the configuration during the bonding process. If desired, a protective layer, e.g., a dielectric polymer layer, can first be provided on the substrate prior to the bump bonding with the chip; in such a scenario the bond pads of the substrate are to be left exposed for contact with the bumps of the chip.

In a next step, referring to Fig. 3C, an underfill encapsulation material 34 can be dispensed, in the conventional manner, between the chip and the substrate, to provide environmental integrity of the bond and to enhance the strength of the bond between the chip and substrate, if such is desired for a given application. Conventional underfill materials can here be employed, e.g., polymeric resins such as EPO-TEK® X16-S, from Epoxy

Technology, Incorporated, of Billerica, MA, or other suitable underfill material.

As shown in Fig. 3C, at this point a protective glob top coating 36 can be applied on the back surface of the chip 10 to provide additional environmental protection of the chip and its connection to the substrate. In an additional or alternative process, a protective coating layer can also or alternatively be provided on the back surface of the chip while it is still in wafer form, e.g., at the very start of the redistribution process sequence. A dielectric, organic, resin material is preferred for the protective coating, e.g., EPO-TEK® T7139, from Epoxy Technology, Inc., of Billerica, MA, or other suitable material. As a glob top coating, the protective material can be dispensed, printed, or otherwise applied in the conventional manner. If provided on the back surface of a wafer at the start of the process sequence, the coating can be applied by spin-coating, stenciling, screen printing, or other blanket coating process like those described above. In this case, the coating can be diced through when individual chips are diced from the wafer, or can be photolithographically patterned to define scribe line regions that are devoid of the material. For many applications, it can be preferred to apply the back side chip coating at the start of the redistribution process to form a chip having its own protective package layer. Referring now to Fig. 4A, in a further example interconnection configuration provided by the invention, bumps, preferably polymer bumps, are formed on the bump bond pads 24 of the chip 10 in the manner described above. Then as shown in Fig. 4B, a dielectric underfill layer 38 is applied to the substrate 32, with the substrate bond pads 30 exposed. The dielectric underfill layer is preferably of a thickness selected such that when the chip 10 is flipped for connection of the bumps 28 with the substrate bond pads 30, in the manner shown in Fig. 4C, no void space is present between the substrate underfill layer 38 and the dielectric redistribution passivation layer 26 of the chip.

This process enables the effective formation of a preprinted underfill layer, thereby eliminating the need for dispensing of an underfill material in the manner of Fig. 3C. It is preferred that the underfill layer 38 be provided as a polymeric resin layer, e.g., a B-stage thermoset or a thermoplastic, such that only one heating cycle is required to both bond the bumps between the chip and substrate and to bond the underfill layer 38 with the redistribution passivation layer 26. Such a scenario also maximizes thermal match throughout the interconnection region. The polymeric underfill layer is preferably formed by stenciling or screen printing to thereby coat the substrate while leaving the bond pads open in a single step, but other processes, like those described above, can also be employed. Once the underfill layer 38 is formed, the chip 10 is flipped and the bumps 28 connected to the bond pads 30 of the substrate. Application of heat and pressure is then carried out in the manner described above to fully bond the bumps to the bond pads of both the chip and the substrate, and to fully bond the underfill layer 38 of the substrate with the chip. A temperature of between about 250°C and about 300°C, and a pressure of between about 50 grams to about 200 grams can be employed, but it is to be recognized that optimum temperature and pressure conditions vary with material selection and with chip size.

It is to be recognized that the invention contemplates a range of adaptations of the process steps illustrated in Fig. 4. For example, the underfill layer 38 can be formed on the chip 10 rather than the substrate 32. Similarly, the interconnection bumps can be formed on the substrate rather than the chip. In general, any convenient arrangement for the bumps and underfill layer can be employed. All that is required is that the underfill layer thickness be selected such that no gap between the chip and the substrate remains once the bumps are connected between the chip and the substrate.

Referring to Figs. 5A-C, in a further adaptation of this process, an underfill layer 38 is applied to the chip 10, with interconnection bumps 28 formed on the chip interconnection bump bond pads 24. The height of the interconnection bumps is preferably slightly less than the thickness of the underfill layer 38 to prevent electrical migration. Preferably the underfill layer and bumps are formed of a polymer resin by stenciling or screen printing in the manner described above. When the chip is flipped, as shown in Fig. 5C, for connection to the substrate 32, the underfill layer acts to eliminate any void space between the chip and the substrate in the manner described above, encircling and protecting the bumps from environmental exposure, and holding the flip chip in compression against the substrate.

Referring to Fig. 6A, in a further interconnection configuration contemplated by the invention, polymer bumps 28 are formed on interconnection bump bond pads 24 of the chip in the manner described above. The bumps here are at least partially polymerized or dried, as- appropriate, prior to substrate bonding. As shown in Fig. 6B, a dielectric adhesive layer 40 is applied to the substrate 32, covering the substrate bond pads 30. Preferably, the dielectric adhesive layer is a polymer resin layer, and can be applied by any of the blanket coating, stenciling, or screen printing techniques described above. Example adhesive layer materials include EPO-TEK® TE179-10 and EPO-TEK® 353 NBT, both from Epoxy Technology, Inc., of Billerica, MA, or other suitable material.

Referring to Fig. 6C, the polymer bumps 28 of the chip are pushed through the adhesive layer 40 of the substrate to contact the substrate bond pads 30. The adhesive layer 40 is provided with a thickness selected such that when the bumps are connected to the substrate bond pads, void space between the chip and the substrate is eliminated. The adhesive layer 40 thereby operates as an underfill layer, with the advantages discussed above.

Details of such an interconnection configuration are provided by Estes et al., in USSN 09/378,847, entitled "Flip Chip Mounting Technique," and filed

September 23, 1999, the entirety of which is hereby incorporated by reference.

Referring back to Fig. IC, in a further chip-substrate interconnection technique provided by the invention, the polymer bump bond pads 24 of the polymer redistribution layer are directly employed themselves to interconnect the chip to the substrate. As shown in Fig. 7A, in this process, a chip including the redistribution layer is flipped and the bump bond pads 24 of the chip are aligned with bond pads 30 of a substrate 32 to which the chip is to be electrically connected. Heat and pressure are applied to the configuration in the manner described above to adhere the bump bond pads

24 directly to the substrate bond pads 30. No interconnection bumps are provided on either the bump bond pads 24 or the substrate bond pads 30; the bump and substrate bond pads are bonded directly to each other, with no bumps in between them. Depending on the degree to which the bump bond pads are vertically compressed as they are bonded to the substrate bond pads, a gap can remain between the chip and the substrate due to the thickness of the bump bond pads and the substrate bond pads. In a next step, referring to Fig. 7B, this gap can be filled, if such is warranted for a given application, with an underfill material 34 that is, e.g., dispensed, in the manner described above, between the chip and the substrate. It is recognized in accordance with the invention, however, that if the substrate bond pads are depressed, and/or if the bump bond pads are substantially compressed during bonding, this interconnection configuration can eliminate the gap between the chip and substrate, and thus can eliminate the need for underfill between the chip and substrate. For many applications this interconnection technique can be particularly advantageous in that it eliminates the need for a bump forming step and for some configurations, further eliminates the need for an underfill forming step. A thermoplastic polymer layer is preferred for the bump bond pads in this configuration to enable compression of the bump bond pads to an extent that eliminates a gap between the chip and substrate. A thermoplastic polymer material such as, e.g., EPO-TEK®

K5022155BE, available from Epoxy Technology, Billerica, MA, or other suitable polymer material, can be employed. It is to be recognized that vertical compression of a bump bond pad during bonding can result in lateral expansion of the bump bond pad; therefore, it is preferred that the distance between redistribution traces and between bump bond pads be adequate to accommodate lateral pad expansion without electrical shorting of the traces or bond pads. Whatever chip-substrate interconnection configuration and technique is employed, the polymer redistribution process of the invention enables the formation of an electrical interconnection structure resulting in a true flip chip package having a form factor identical with that of the chip. The flip chip package accommodates existing peripheral wire bond pad configurations while providing the advantages of flip chip bond pad arrays and mounting techniques. A redistributed bond pad configuration can therefore enable the use of flip chip mounting techniques without the need for redesign of an existing, older chip layout.

It is contemplated that the polymer redistribution process and resulting interconnection structure of the invention can be applied to a wide range of structures beyond flip chips. Specifically, it is contemplated that the process steps of Figs. 1A-1D can be carried out on any structure for which bond pad redistribution is desired. For example, substrates such as printed circuit boards, unconventional substrates such as smart cards and other electronic chip support platforms, multi-chip modules, chip packages, conventional chip configurations, 3-D stacks of chips, and other substrates having bond pads can be accommodated by the processes of the invention to enable electrical interconnection to a second substrate or other platform.

The polymer redistribution technique and resulting interconnection structure of the invention is therefore not limited to flip chips, but instead can be widely applied to various substrate and platform configurations.

The invention further provides particularly advantages in a polymer redistribution configuration wherein in all-polymer passivation and electrically-conductive layers are employed; enabling thermal matching of materials, ease and cost of fabrication, and process efficiency optimization. All such layers can be applied using a single piece of equipment and with similar materials, reducing space and equipment requirements. Thermal stress is minimized across and at the surface of the chip, and reworkability of the substrate connection of a chip is enabled. It is recognized, of course, that those skilled in the art may make various modifications and additions to the polymer redistribution processes and electrical interconnection structures of the invention without departing from the spirit and scope of the present contribution to the art. Accordingly, it is to be understood that the protection sought to be afforded hereby should be deemed to extend to the subject matter of the claims and all equivalents thereof fairly within the scope of the invention.

I claim:

Claims

1. An electrical interconnection structure for a flip chip comprising: a plurality of chip bond pads in electrical connection with an electronic circuit, the chip bond pads provided on a first face of a flip chip; a plurality of electrically-conductive polymer bump bond pads provided on the first face of the flip chip in an arrangement selected for electrical interconnection of the flip chip with a substrate; and a plurality of electrically-conductive polymer redistribution traces provided on the first face of the flip chip, each trace electrically connecting a chip bond pad to a bump bond pad.

2. The flip chip interconnection structure of claim 1 wherein the electrically-conductive polymer bump bond pads and redistribution traces are provided together of a common patterned electrically-conductive polymer layer.

3. The flip chip interconnection structure of claim 2 wherein the electrically-conductive polymer bump bond pads and redistribution traces comprise electrically-conductive thermoset bump bond pads and redistribution traces.

4. The flip chip interconnection structure of claim 1 wherein the arrangement of electrically-conductive polymer bump bond pads is located centrally on the flip chip relative to the chip bond pads.

5. The flip chip interconnection structure of claim 1 further comprising a dielectric polymer chip passivation layer provided on the first face of the flip chip under the electrically-conductive polymer bump bond pads and redistribution traces, the chip bond pads exposed through the chip passivation layer for the electrical connection of the chip bond pads to the redistribution traces.

6. The flip chip interconnection structure of claim 1 further comprising a dielectric polymer trace passivation layer provided on the first face of the flip chip over the electrically-conductive polymer redistribution traces, the bump bond pads exposed through the trace passivation layer.

7. The flip chip interconnection structure of claim 6 wherein the dielectric polymer trace passivation layer comprises a thermoplastic layer.

8. The flip chip interconnection structure of claim 6 wherein the dielectric polymer trace passivation layer comprises a thermoset layer.

9. The flip chip interconnection structure of claim 1 wherein the flip chip includes a dielectric polymer protective layer provided on a second face of the flip chip opposite the first flip chip face.

10. The flip chip interconnection structure of claim 1 further comprising electrically-conductive polymer bumps provided on the bump bond pads.

11. The flip chip interconnection structure of claim 10 wherein the electrically-conductive polymer bumps comprise thermoplastic bumps.

12. The flip chip interconnection structure of claim 10 wherein the polymer bumps are interconnected between bump bond pads of the flip chip and substrate bond pads.

13. The flip chip interconnection structure of claim 1 wherein the bump bond pads of the flip chip are directly interconnected to substrate bond pads.

14. The flip chip interconnection structure of claim 1 wherein the arrangement of polymer bump bond pads includes auxiliary bump bond pads not connected to redistribution traces.

15. A method of forming an electrical interconnection structure for a flip chip comprising the steps of: providing a flip chip having a plurality of chip bond pads in electrical connection with an electronic circuit, the chip bond pads provided on a first face of the flip chip; forming a plurality of electrically-conductive polymer bump bond pads on the first face of the flip chip in an arrangement selected for electrical interconnection of the flip chip with a substrate; and forming a plurality of electrically-conductive polymer redistribution traces on the first face of the flip chip, each trace electrically connecting a chip bond pad to a bump bond pad.

16. The method of claim 15 wherein the step of providing a flip chip comprises providing a semiconductor wafer including a plurality of flip chips, and further comprising a last step of dicing the semiconductor wafer to produce separated flip chips.

17. The method of claim 15 further comprising a step of forming a dielectric polymer chip passivation layer on the first face of the flip chip prior to forming the electrically-conductive polymer bump bond pads and redistribution traces, the chip bond pads left exposed through the chip passivation layer for the electrical connection of the flip chip bond pads to the redistribution traces.

18. The method of claim 15 further comprising forming a dielectric polymer trace passivation layer on the first face of the flip chip over the electrically-conductive polymer redistribution traces, the bump bond pads left exposed through the trace passivation layer.

19. The method of claim 15 further comprising a step of forming a dielectric polymer protective layer on a second face of the flip chip opposite the first flip chip face.

20. The method of claim 15 wherein the electrically-conductive polymer bump bond pads and redistribution traces are formed together of a common layer of electrically-conductive polymer.

21. The method of claim 20 wherein the electrically-conductive polymer bump bond pads and redistribution traces are formed together by screen printing a polymer layer.

22. The method of claim 20 wherein the electrically-conductive polymer bump bond pads and redistribution traces are formed together by stenciling a polymer layer.

23. The method of claim 15 further comprising a step of directly bonding the bump bond pads of the flip chip to bond pads of the substrate.

24. The method of claim 15 further comprising a step of forming electrically-conductive polymer bumps on the bump bond pads.

25. The method of claim 24 wherein forming electrically-conductive polymer bumps comprises stenciling polymer bumps on the bump bond pads.

26. The method of claim 24 further comprising a step of bonding the polymer bumps to bond pads of the substrate.

27. The method of claim 24 further comprising the steps of: forming a dielectric polymer layer on the substrate, with bond pads of the substrate left exposed; and bonding the polymer bumps to the substrate bond pads, the substrate dielectric polymer layer provided of a thickness selected to eliminate void space between the flip chip and substrate when the polymer bumps are bonded to the substrate bond pads.

28. The method of claim 24 further comprising the steps of: forming a dielectric polymer layer on the flip chip, with the polymer bumps left exposed; and bonding the polymer bumps to bond pads of the substrate, the flip chip dielectric layer provided of a thickness selected to eliminate void space between the flip chip and the substrate when the polymer bumps are bonded to the substrate bond pads.

29. The method of claim 24 further comprising the steps of: forming a dielectric polymer layer on the substrate, with bond pads of the substrate covered by the polymer layer; and pushing the polymer bumps through the substrate dielectric polymer layer to directly interconnect the bumps to the substrate bond pads.

30. An electrical interconnection structure comprising: a plurality of substrate bond pads in electrical connection with an electronic circuit, the bond pads provided on a first face of a first substrate; a plurality of electrically-conductive polymer bump bond pads provided on the first face of the first substrate in an arrangement selected for electrical interconnection of the first substrate with a second substrate; and a plurality of electrically-conductive polymer redistribution traces provided on the first face of the first substrate, each trace electrically connecting a substrate bond pad to a bump bond pad.