US6093587A - Crystallization of amorphous silicon film using a metal catalyst - Google Patents

Crystallization of amorphous silicon film using a metal catalyst Download PDF

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US6093587A
US6093587A US09/026,888 US2688898A US6093587A US 6093587 A US6093587 A US 6093587A US 2688898 A US2688898 A US 2688898A US 6093587 A US6093587 A US 6093587A
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metal element
film
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semiconductor film
silicon film
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Hisashi Ohtani
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0225—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using crystallisation-promoting species, e.g. using a Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/016—Catalyst

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device using semiconductor with crystallinity.
  • TFT thin film transistor
  • the TFT is made up of thin film semiconductor formed on a substrate.
  • the TFT is used in a variety of integrated circuits, and in particular, attention is paid to the TFT as a switching device disposed in each pixel and a driver device formed on a peripheral circuit section in an active matrix-type liquid-crystal display device.
  • an amorphous silicon film has been employed as a thin film semiconductor for use in a TFT, but in order to obtain higher performance, an attempt has been made to use a silicon film (crystalline silicon film) having crystallinity.
  • the TFT using the crystalline silicon film enables higher speed operation than that using the amorphous silicon film by two digits or more, and enables the manufacturing peripheral drive circuit of the liquid crystal display device which has been formed of an external IC, on a substrate on which an active matrix circuit is also formed.
  • the conventional crystalline silicon film is obtained by crystallizing an amorphous silicon film formed through a plasma CVD method or a low pressure CVD method, by a heat treatment or the irradiation of a laser light.
  • the method of crystallizing the amorphous silicon film by heating suffers from the following problems although it has an advantage that the crystalline silicon thin film can be obtained over a large area.
  • a high heating temperature is required (it is difficult to use a glass substrate).
  • the method of crystallizing the amorphous silicon film by the irradiation of a laser light suffers from a problem that high productivity and large-area processing are difficult although it has superiority that a glass substrate can be used as the substrate.
  • the present inventors have developed a technique in which metal elements that promote the crystallization such as nickel, palladium, lead or the like are added to the amorphous silicon film to obtain the crystalline silicon film through a heat treatment conducted at a lower temperature than the conventional one (refer to Japanese Patent Unexamined Publication No. Hei 7-130652).
  • This method not only enables a crystallizing rate to increase so that crystallization can be achieved in a short time, but also enables high crystallinity to be uniformly obtained over a large area in comparison with the conventional method of crystallizing the amorphous silicon film by only heating or the crystallization of the amorphous silicon film by means of only the irradiation of a laser light.
  • a silicon oxide film 502 is formed on a glass substrate 501 as an under film, and an amorphous silicon film 503 is then formed on the silicon oxide film 502.
  • UV rays are applied to the amorphous silicon film 503 in an oxygen atmosphere to form an extremely thin oxide film on a surface of the amorphous silicon film. This is for preventing a solution containing nickel which will be introduced therein later from being repelled by the surface of the amorphous silicon film.
  • a mask 504 made of the silicon oxide film is formed. Then, an opening 505 is then defined in the mask 504. Further, a solution containing nickel therein is coated on the surface, and a excessive solution is blown off by a spin coater, to thereby obtain a state where a small amount of solution is held as indicated by reference numeral 506 (FIG. 5B).
  • the growth is hindered by the mask 504 made of the silicon oxide film.
  • the mask 504 is removed to conduct a heat treatment.
  • nickel is also removed together, which will adversely affect crystallization to be conducted later.
  • the present invention has been made in order to solve the above-described problems, and therefore an object of the present invention is to provide a technique of removing hindrance to crystal growth made in parallel to the above-described substrate.
  • a method of manufacturing a semiconductor device comprising the steps of:
  • the introduction of said metal elements is conducted by coating a solution containing metal elements therein, and the selective holding of said metal elements is conducted by using water repellency of the silicon film to said solution.
  • a method of introducing metal elements that promote the crystallization of silicon from a surface of an amorphous silicon film comprising the step of:
  • the metal elements are selectively introduced.
  • an oxide film is formed on a part of the amorphous silicon film with the result that the wettability of that region is improved. Then, the solution containing the metal elements therein is coated on the surface in that state so that the metal elements can be introduced in only that region, or an introduced amount of the metal elements can be increased only in that region.
  • the most preferable metal elements that promote the crystallization of silicon is Ni from the viewpoint of the effect and reproducibility.
  • the metal elements to be used may be one or plural kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au.
  • an amorphous film which is made of a silicon compound may be used instead of the amorphous silicon film.
  • an amorphous film indicated by Si x Ge 1-x (0 ⁇ x ⁇ 1) may be used.
  • FIGS. 1A to 1C are cross-sectional views each showing the vicinity of an opening into which metal elements are added at the time of crystallization according to the present invention
  • FIGS. 2A to 2D are diagrams showing a process of manufacturing a thin film transistor of the first embodiment
  • FIGS. 3E to 3H are diagrams showing a process of manufacturing a thin film transistor of the first embodiment
  • FIGS. 4I to 4K are diagrams showing a process of manufacturing a thin film transistor of the first embodiment
  • FIGS. 5A to 5C are diagrams showing a crystallizing method in a conventional example.
  • FIG. 6A to 6F are diagrams showing a process of manufacturing a thin film transistor of the second embodiment.
  • an amorphous silicon film 203 is formed (FIG. 2A).
  • a part of the amorphous silicon film 203 is removed to form a region into which metal elements indicated by reference numeral 205 are introduced (FIG. 2B).
  • a solution for example, nickel acetate solution
  • nickel elements therein which exhibits a water repellency (hydrophobic property) is coated on an entire surface of the amorphous silicon film 203.
  • the amount of the metal elements contained in the solution is desirably set so as to be 1 ppm to 200 ppm, preferably 1 ppm to 50 ppm (weight conversion) with respect to the solution when the metal elements are nickel, although it depends on the kind of solution. This is a value determined in view of the concentration of nickel and a hydrofluoric acid resistivity in the film after the completion of crystallization.
  • a solution 150 exists on a side surface of the amorphous silicon film 103.
  • reference numeral 100 denotes a glass substrate
  • 102 is a silicon oxide film which denotes an under layer.
  • a temperature at which the above-described heat treatment is conducted for crystallization is selected from a range of 550 to 650° C.
  • a configuration as indicated by reference numeral 205 in FIG. 2B (dimensions such as a length, a depth and a width) obtained by removing a part of the amorphous silicon film is important in controlling the crystallinity of the silicon film and the amount of metal elements.
  • crystallization is impeded by an influence of an interface between the oxide film and the amorphous silicon film, thereby being not capable of obtaining an excellent crystallinity.
  • crystal growth proceeds from an unintended region 151 on the amorphous surface, to thereby come to a state where crystal growth proceeding from a specified region toward a direction parallel to the substrate is impeded, because, when crystal growth collides with crystal growth proceeding from a different region, grain boundaries are formed there to stop crystal growth.
  • the solution is coated on the amorphous silicon film without allowing the amorphous silicon film to be in contact with an oxidizing atmosphere (for example, air) after the stains on the surface of the amorphous silicon film and the natural oxide film are removed by the hydrofluoric acid processing, etc., and then a heat treatment is conducted.
  • an oxidizing atmosphere for example, air
  • FIGS. 2A to 4K show a process of manufacturing a thin film transistor according to a first embodiment.
  • a silicon oxide film is formed in thickness of 30 nm ⁇ as an under film 202 on a quartz substrate 200. If the smoothness of the surface of the silica substrate is excellent, and the surface is sufficiently cleaned, the under film 202 is not particularly required.
  • the quartz substrate is used as an insulating substrate, a glass substrate, a single crystal silicon substrate or a polycrystal silicon substrate on a surface of which an insulating film is formed may be employed instead of the quartz substrate.
  • an amorphous silicon film 203 that serves as a starting film of the crystalline silicon film is formed in a thickness of 60 nm through the low pressure CVD method (FIG. 2A).
  • the thickness of the amorphous silicon film is set to 200 nm or less.
  • an opening indicated by reference numeral 205 is defined on the amorphous silicon film.
  • the opening 205 has a slender rectangular which is longitudinal along a backward direction and a forward direction of the figure.
  • the width of the opening 205 is properly set to be 10 ⁇ m or more.
  • an end portion of the opening 205 is designed so as to be apart from an island region of an active layer which will be formed in a later process.
  • the silicon oxide film 202 which is an under film is exposed.
  • the stains on the surface of the amorphous silicon film and a natural oxide film are removed by a hydrofluoric acid processing or the like.
  • a nickel acetate solution containing nickel elements of 10 ppm in weight conversion therein is coated on the surface.
  • spin dry is conducted using a spinner (not shown) to remove an excessive solution existing on the upper surface of the amorphous silicon film.
  • the nickel acetate solution has a sufficient water repellency to the amorphous silicon film. In this way, there is obtained a state in which the nickel elements exist in a state indicated by a dotted line 206 in FIG. 2C.
  • the nickel acetate solution is repelled by the surface of the amorphous silicon film in a region other than the opening 205. Then, there is obtained a state in which the nickel elements are selectively held in contact with a part of the amorphous silicon film on a side wall of the opening 205.
  • the crystal growth proceeds from the region of the opening 205 into which the nickel elements are introduced (a metal element added opening) toward a direction parallel to the substrate.
  • the surface of the crystalline silicon film that has laterally grown as obtained by this crystal growth is very excellent in smoothness in comparison with the conventional low-temperature polysilicon or high-temperature polysilicon. It is presumed that this is because directions along which grain boundaries extend are roughly uniform.
  • the silicon film which is called generally polycrystal silicon or polysilicon has a surface roughness of ⁇ 10 nm or more. However, in the case of allowing lateral growth as described in this embodiment, it is observed that the surface roughness is ⁇ 3 nm or less. The roughness deteriorates the characteristics of the interface between the silicon film and the gate insulating film, and therefore the roughness is preferably made as small as possible.
  • the lateral growth can be conducted over 100 ⁇ m or more.
  • a laser light may be irradiated thereonto.
  • the crystallization may be further promoted by the irradiation of a laser light.
  • the irradiation of the laser light has the effect of diffusing a mass of nickel elements existing in the film so that the nickel elements are liable to be removed later. Even if the laser light is irradiated thereon at this stage, the lateral growth does not further proceed.
  • the laser light to be used may be an excimer laser having the wavelengths of an ultraviolet region.
  • KrF excimer laser (248 nm in wavelength) or XeCl excimer laser (308 nm in wavelength) can be employed.
  • a heat treatment is conducted at 950° C. in an oxygen atmosphere containing halogen elements, for example, an oxygen atmosphere containing HCl of 3 vol % therein, to form a thermal oxide film in a thickness of 200 ⁇ (not shown).
  • the thickness of the silicon film is reduced about 100 ⁇ according to the formation of the thermal oxide film. That is, the thickness of the silicon film is set to be about 500 ⁇ .
  • the silicon elements having an unstable bonding state in the film are utilized for the formation of the thermal oxide film when the thermal oxide film is formed. Then, defects in the film are reduced, thereby being capable of obtaining higher crystallinity.
  • the gettering of the nickel elements in the film is conducted due to the formation of the thermal oxide film and the action of chlorine.
  • the thermal oxide film (not shown) is removed.
  • a crystalline silicon film in which the content concentration of the nickel elements is reduced is obtained.
  • the crystalline silicon film thus obtained has a structure in which crystal structures extend in one direction (this direction is identical with the crystal growth direction). That is, the crystalline silicon film has a structure in which a plurality of slender columnar crystals are aligned in parallel through a plurality of grain boundaries that extend in one direction.
  • patterning is conducted to form a pattern of a lateral growth region.
  • An island region 301 of this region will form an active layer of a TFT later (FIG. 3E).
  • the island region 301 is positioned in such a manner that a direction connecting a source region and a drain region is identical or substantially identical with the crystal growth direction. This enables a direction along which carriers move to be identical with a direction along which crystal lattices continuously extend, with the result that a TFT having a high-characteristic can be obtained.
  • a silicon oxide film 315 is formed in a thickness of 500 ⁇ through the plasma CVD method. Because no mask is formed on a surface, the silicon oxide film 315 should be formed over the entire surface of the under film 202 and the island region 301. (FIG. 3F).
  • the silicon oxide film 315 should be formed over the entire surface of the under film 202 and the island region 301.
  • a thermal oxide film 311 is formed in a thickness of 300 ⁇ through the thermal oxidation method.
  • the formation of the thermal oxide film 311 having a thickness of 300 ⁇ makes the surface of the island region 301 reduce to the thickness of 150 ⁇ . Accordingly, the thermal oxide film 311 is formed using part of the silicon island 301, so that it is apparent that the thermal oxide film 311 is formed between the silicon island 301 and the silicon oxide film formed through the plasma CVD method.
  • an aluminum film for forming a gate electrode is formed in a thickness of 4,000 ⁇ through the sputtering method. 0.2 wt % of scandium is allowed to be contained in the aluminum film.
  • the reason why scandium is allowed to be contained in the aluminum film is to suppress hillock or whisker from occurring in a later process.
  • the hillock or whisker is directed to a needle-shaped or sharp projection caused by abnormal growth of aluminum at the time of heating.
  • a material for forming the gate electrode may be tantalum (Ta), polycrystal silicon doped with phosphorus (P) with a high concentration, silicide of tungsten (WSi), or a structure in which polycrystal silicon doped with phosphorus and silicide of tungsten are laminated or hybridized, other than aluminum.
  • a dense anodic oxide film (not shown) is formed.
  • the anodic oxide film is formed under the condition where an electrolyte is an ethylene glycol solution containing 3% of tartaric acid, an anode is formed of an aluminum film and a cathode is made of platinum.
  • the anodic oxide film having a dense film quality is formed in a thickness of 100 ⁇ on the aluminum film.
  • the anodic oxide film not shown serves to improve the adhesion to a resist mask 322 which will be formed later.
  • the thickness of the anodic oxide film can be controlled by applied voltage at the time of anodic oxidation.
  • a resist mask is formed. Using this resist mask, the aluminum film is patterned to a pattern 318. Thus, a state shown in FIG. 3H is obtained.
  • anodic oxidation is again conducted.
  • a 3% of oxalic acid aqueous solution is used as the electrolyte.
  • anodic oxidation is conducted with the pattern 318 of aluminum as an anode, to thereby form a porous anodic oxide film.
  • porous anodic oxide films 419 are selectively formed on a side surface of the aluminum pattern because a high-adhesive resist mask 322 exists on the upper portion. (FIG. 4)
  • the porous anodic oxide films 419 can be allowed to grow up to the thickness of several ⁇ m. In this embodiment, the thickness is set to be 6,000 ⁇ . The growth distance can be controlled according to an anodic oxidation time.
  • anodic oxidation is again conducted with the above-mentioned, ethylene glycol solution containing 3% of tartaric acid as the electrolyte.
  • a dense-quality anodic oxide film is formed as indicated by reference numeral 420 because the electrolyte enters the porous anodic oxide films 419.
  • the thickness of the dense anodic oxide film 420 is set to be 1,000 ⁇ .
  • the thickness is controlled by applied voltage.
  • the exposed silicon oxide film 315 is etched. Also, the gate insulating film formed of the CVD silicon oxide film 315 and the thermal oxide film 311 is etched. The etching is made by dry etching.
  • impurity ions are implanted.
  • P (phosphorus) ions are implanted through the plasma doping method.
  • regions 430 and 434 to be heavy-doped and regions 431 and 433 to be light-doped are formed. This is because the remaining silicon oxide film 315 functions as a translucent mask to shield a part of ions as implanted there.
  • a laser light (or an intense light using a lamp) is irradiated to activate the region into which the impurity ions are implanted.
  • a source region 430, a channel forming region 432, a drain region 434, and low-concentration impurity regions 431 and 433 are formed in a self-alignment manner.
  • LDD light dope drain
  • offset gate regions can be formed outside of the channel forming region 432 with that thickness.
  • the offset gate regions are formed, but since their dimensions are small, the contribution of the offset gate regions is small, and in order to avoid complexity of the drawings, the offset gate regions are not shown in the figures.
  • the interlayer insulating film may be a layer made of a resin material formed on a silicon oxide film or a silicon nitride film.
  • a second embodiment is directed to an example in which a hydrophobic property of the surface of an amorphous silicon film is selectively controlled so as to selectively manufacture TFTs different in crystallinity.
  • a p-channel TFT (PTFT) is stable in characteristic but small in movability.
  • an n-channel TFT (NTFT) has an tendency that it is large in movability but unstable in characteristic because of the hot carrier effect.
  • the crystalline silicon film that forms a p-channel TFT is manufactured using metal elements with a high concentration, whereas a crystalline silicon film that forms an n-channel TFT is manufactured using metal elements with a low concentration.
  • FIGS. 6A to 6F show a manufacturing process according to the second embodiment.
  • a silicon oxide film 602 is formed as an under film on a glass substrate 601 (or quartz substrate).
  • an amorphous silicon film 603 is formed through the low pressure CVD method.
  • an extremely thin oxide film (not shown) is selectively formed on the entire surface, and an oxide film 604 is also selectively formed thereon.
  • an oxide film is formed by the irradiation of UV rays in an oxidization atmosphere.
  • the method of forming the oxide film may be a method of using an oxidation acting solution such as ozone water.
  • FIG. 6A a state shown in FIG. 6A is obtained.
  • a nickel acetate solution 605 is coated on the surface.
  • a region where the oxide film 604 is formed is held in contact with nickel elements because the surface of the oxide film 604 is deteriorated in hydrophobic property (FIG. 6B).
  • the nickel acetate solution is repelled by the surface of the amorphous silicon film, the nickel elements are not introduced into a region where the oxide film 604 is not formed.
  • the heat treatment is conducted at 600° C. for 4 hours in a nitrogen atmosphere.
  • the entire of the amorphous silicon film is crystallized in this heat treatment.
  • the nickel addition region first, in the region where the oxide film 604 is formed, that is, the region where the nickel elements are introduced (the nickel addition region), crystals grow vertically.
  • the region where the oxide film 604 is not formed that is, the region where the nickel elements are not introduced (the no nickel addition region)
  • crystals grow laterally from the nickel addition region.
  • natural nucleation also occurs before the crystal lateral growth starts. As a result, crystals by the lateral growth and the natural nucleation are mixed in the no nickel addition region, so that the crystallinity in the nickel no addition region becomes lower than that in the nickel addition region.
  • the crystal nucleation can be controlled. But, in the no nickel addition region, natural nucleation which cannot be controlled also occurs. Therefore, it results in the no nickel addition region having a lower crystallinity than the nickel addition region.
  • gate insulating film 600 is formed.
  • gate electrodes 610 and 612 made of aluminum are formed.
  • Anodic oxide films 611 and 613 are formed in the periphery of the gate electrode.
  • doping with phosphorus and born is selectively conducted, to thereby form a source region 614, a channel forming region 615 and a drain region 616 of a PTFT in a self-alignment manner (FIG. 6E).
  • a source region 617, a channel forming region 618 and a drain region 619 of an NTFT are formed in a self-alignment manner (FIG. 6E).
  • an interlayer insulating film 620 is formed, and contact holes are also defined to form a source electrode 621 and a drain electrode 622 of the PTFT. Also, a source electrode 623 and a drain electrode 624 of the NTFT are formed.
  • the PTFT and the NTFT are obtained.
  • the crystallinity of the active layer that forms the PTFT is higher than that of the active layer that forms the NTFT.
  • the movability of the PTFT can be relatively increased. Since the characteristics of the PTFT are more stable than those of the NTFT, even if the concentration of nickel elements becomes slightly high, there arises no problem on the whole.
  • the concentration of nickel elements in the active layer is reduced so as to enhance the stability of the characteristics.
  • the present invention using the hydrophobic property of the silicon film, when the solution containing the metal elements that promote the crystallization of silicon therein is coated, selective coating is realized, thereby being capable of conducting crystal growth in a direction parallel to the substrate.
  • the crystal growth since no mask that impedes crystal growth is formed on the upper portion of the crystal growth region, the crystal growth is not impeded, thereby being capable of obtaining the crystalline region high in quality.
  • the present invention described in this specification is applicable to not only the structure of a peripheral circuit formed together with an active matrix circuit on the same substrate in a transparent or reflection type active matrix liquid-crystal display device, but also a display device having an EL (electro luminescence) element, and a variety of circuits using a thin film transistor.
  • a display device having an EL (electro luminescence) element and a variety of circuits using a thin film transistor.
  • the present invention described in this specification is applicable to the manufacture of a variety of integrated circuits using a thin film transistor and a device using those various integrated circuits.
  • the device of this type may be, for example, a portable information processing terminal or a video camera.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
US09/026,888 1997-02-20 1998-02-19 Crystallization of amorphous silicon film using a metal catalyst Expired - Lifetime US6093587A (en)

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JP05384397A JP3983334B2 (ja) 1997-02-20 1997-02-20 半導体装置の作製方法
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US6312979B1 (en) * 1998-04-28 2001-11-06 Lg.Philips Lcd Co., Ltd. Method of crystallizing an amorphous silicon layer
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KR20080065460A (ko) * 2007-01-09 2008-07-14 엘지전자 주식회사 수평 금속 유도 결정화를 이용한 저온 다결정 실리콘광기전력 변환소자의 제조방법

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US6465288B1 (en) * 1997-07-30 2002-10-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device using a crystalline semiconductor film
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US20060278876A1 (en) * 1998-07-15 2006-12-14 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
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US7667235B2 (en) 1998-07-15 2010-02-23 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
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US20020013114A1 (en) * 1998-08-07 2002-01-31 Hisashi Ohtani Semiconductor device and method of manufacturing the same
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US20080138963A1 (en) * 2001-03-29 2008-06-12 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
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US20070196960A1 (en) * 2001-07-02 2007-08-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US20030032221A1 (en) * 2001-07-02 2003-02-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7998845B2 (en) 2001-07-02 2011-08-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7256109B2 (en) * 2003-08-13 2007-08-14 Sharp Laboratories Of America, Inc. Isotropic polycrystalline silicon
US20050170568A1 (en) * 2003-08-13 2005-08-04 Sharp Laboratories Of America, Inc. Isotropic polycrystalline silicon
US20080099793A1 (en) * 2006-10-13 2008-05-01 David Fattal Photodiode module and apparatus including multiple photodiode modules

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KR19980071529A (ko) 1998-10-26

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