US5825786A - Undersampling digital testability circuit - Google Patents

Undersampling digital testability circuit Download PDF

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Publication number
US5825786A
US5825786A US08/096,149 US9614993A US5825786A US 5825786 A US5825786 A US 5825786A US 9614993 A US9614993 A US 9614993A US 5825786 A US5825786 A US 5825786A
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word
data string
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circuit
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US08/096,149
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Mark Burns
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to DE69419292T priority patent/DE69419292T2/de
Priority to JP6201238A priority patent/JPH07167926A/ja
Priority to EP94305436A priority patent/EP0642085B1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Definitions

  • This invention relates to electronic circuits and more particularly relates to sampling circuits for circuit testing.
  • circuit performance is verified through functional and parametric testing. For example, a series of voltage values are placed on circuit inputs and the outputs are examined to see whether the circuit is functioning appropriately. Additionally, supply currents, signal transition times and other characteristics are measured to ensure each circuit meets the parametric specifications required by the customer. As circuits become faster, test mechanisms must become more creative to ensure that high speed data transfers are error free.
  • FIG. 1 is a prior art diagram illustrating a portion of a video driver circuit 10.
  • Video driver circuit 10 consists of a data source 12, typically pixel data, a bus 13, a control circuit 14, a second bus 15, and a digital-to-analog converter (DAC) 16.
  • Control circuit 14 may include internal multiplexing that ramps up the speed of internal operations on chip so that incoming pixel rates can be reduced, RAM look-up tables, and additional switching circuitry that is common in video drivers.
  • Control circuit 14 provides DAC 16 with a multiple bit code (or "word") that reflects a desired color intensity via bus 15.
  • DAC 16 converts the bit code into an analog voltage that reflects the desired color intensity.
  • a common prior art method of testing the integrity of data transfers is to digitize the analog voltage of DAC 16 and compare the digitized voltage value to the expected voltage. This is typically performed by transferring all "0"'s and "1"'s to obtain a black/white color pattern (square wave) at the DAC output.
  • this is a slow test to perform and therefore is expensive.
  • the resolution of the digitizing technique is not great enough to ensure transfer accuracy to the desired confidence levels. For example, if a least significant bit is getting dropped the error may not be large enough for a voltage error to be detected. Further, even if the error is sufficiently large to detect a failure it is not possible to determine what bit or bits have failed.
  • a second prior art method is a cyclic redundancy check test (CRC) or a "1's" accumulation method that inputs several bit words into video driver 10 and outputs the words at the output of control circuitry 14.
  • CRC cyclic redundancy check test
  • the words are algorithmically combined and compared to the pre-computed expected value. This method is undesirable because although it determines in a YES/NO fashion whether a failure exists, it does not provide any diagnostic capability; it cannot provide information on what specific bit or bits have failed.
  • An undersampling digital testability circuit 20 includes a means for carrying data transfers 15, a data capture array 22 and a divider circuit 18.
  • Divider circuit 18 provides an enable signal to data capture array 22 that undersamples data travelling along the means for carrying data transfers 15 at high data rates thereby effectively testing the integrity of high data rate transfers without the disadvantages of prior art test methodologies.
  • FIG. 1 is a prior art block diagram of a video driver 10.
  • FIG. 2 is a block diagram illustrating the preferred embodiment of the invention, an undersampling digital testability circuit 20 in a video driver circuit 30.
  • FIG. 3 is a schematic diagram illustrating in greater detail undersampling digital testability circuit 20.
  • FIG. 4 is a block diagram illustrating an undersampling register array 22.
  • FIG. 2 is a block diagram illustrating the preferred embodiment of the invention, undersampling digital testability circuit 20 in a video driver circuit 30.
  • Video driver circuit 30 consists of three palette RAMs 26a-26c receiving pixel data as inputs. Palette RAMs 26a-26c are connected to DACs 16a-16c via bus 15 and drive a video monitor.
  • Undersampling digital testability circuit 20 acts as a diagnostic port that accesses bus 15. Circuit 20 advantageously tests high speed data transfers without the limitations of prior art data transfer methodologies. Alternatively, bus 15 may be any means for carrying data transfers.
  • FIG. 3 is a block diagram illustrating in greater detail undersampling digital testability circuit 20.
  • Circuit 20 has data (in this particular embodiment a multiple bit word from one of palette RAMs 26a-26c) coming into an undersampling register array 22.
  • Undersampling register array 22 is also connected to a counter 18.
  • Counter 18 receives as an input a data transfer clock signal that is the same frequency of the high speed data transfer.
  • the output of register array 22 is connected to automated test equipment (ATE) external to video driver circuit 30.
  • ATE automated test equipment
  • FIG. 4 is a schematic diagram illustrating register array 22.
  • Register array 22 has a plurality of D-type flip flops 24a-24i each having a data input connected to bus 15, an enable input connected to counter 18, and an output connected to the ATE.
  • the letter "i" represents the number of flip flops used and corresponds to the number of bits of data to be captured.
  • the ATE takes the data on the output of flip flops 24a-24i and compares it to its expected values to check for errors in the data transfer. In this manner, the ATE can determine whether a data transfer failure occurred and which bit or bits caused the failure.
  • Undersampling digital testability circuit 20 undersamples the data being transferred within video driver circuit 30 and thus the transfer rate of undersampled data to the ATE is substantially slower than the rate of the high speed data transfers within video driver circuit 30.
  • pixel data is input to palette RAMs 26a-26c.
  • the pixel data represents an instruction regarding the color and intensity for each individual pixel and is driven by software in test mode.
  • the digital test vectors driving video circuit 30 will be from the ATE.
  • Palette RAMs 26a-26c form a look-up table and output a multi-bit code that reflects the desired color and intensity. It should be understood that most colors consist of a combination of varying red, blue, and green colors. Therefore, each desired color and intensity will be represented by three multi-bit codes, each being input to its appropriate DAC 16a-16c.
  • Each DAC 16a-16c receives its respective multi-bit code and converts it into an analog voltage as is well known in digital-to-analog converters.
  • the analog voltages on the output of DACs 16a-16c drive the output, typically a video monitor.
  • the DACs 16a-16c in this embodiment output a current, but drive an external resistance which converts the current to a voltage.
  • DACs 16a-16c may output a voltage directly.
  • circuit 20 In high performance graphics systems the rate of data transfer can be very high (75-200 Mhz).
  • digital testability circuit 20 is coupled to bus 15.
  • Undersampling digital testability circuit's 20 operation occurs in the following manner.
  • Multi-bit codes (data) from palette RAMs 26a-26c serve as data inputs to undersampling register array 22 of FIG. 3.
  • Register array 22 includes a plurality of D-type flip flops 24a-24i as shown in FIG. 4 where "i" equals the number of data bits input from palette RAMs 26a-26c. For example, if the multi-bit words from palette RAMs 26a-26c are eight bits long there would be eight D-type flip flops in register array 22.
  • Flip flops 24a-24i are enabled via the output signal from counter 18.
  • counter 18 must be synchronized appropriately with register array 22 so that flip flops 24a-24i are not enabled at the same instant that data is changing in flip flops 24a-24i. Therefore, flip flops 24a-24i may be enabled on the falling edge of the output signal of counter 18. Alternatively, the output of counter 18 may be sent through several transmission gates to provide sufficient delay to prohibit an indeterminate state in flip flops 24a-24i.
  • Counter 18 receives as an input a binary signal having a frequency that matches the frequency of the data transfer. Counter 18 outputs a binary signal that represents the frequency of the data transfer clock signal divided by "N" where "N" is an integer. The value for "N" will be described later.
  • a 48 bit binary sequence is repeatedly transferred through palette RAMs 26a-26c to DACs 16a-16c by ATE software at the rate determined by the data transfer clock rate, each color having four individual eight bit words.
  • a typical bit sequence for a single color may be as follows:
  • register array 22 consists of eight D-type flip flops. Therefore, each time the flip flops 24a-24i are enabled an eight bit word is captured.
  • N which represents the integer used to "divide down" the data transfer clock signal is 5 (five).
  • Table 1 illustrates this clearly. In Table 1 each sampled eight bit word is underlined. Also "J" represents the number of eight bit words that have been transferred. Therefore, in 16 data transfer clock cycles, each eight bit word (that is transferred at 85 Mhz, yet the data rate to the ATE is only 17 Mhz) will have been accurately sampled.
  • undersampling digital testability circuit 20 samples the repeating 32 bit sequence, thus accurately testing each high speed data transfer.
  • circuit 20 is not limited to this undersampling solution.
  • the above relation is desirable only because the sampled words come out in the same sequence in which they were input. This is not necessary.
  • circuit 20 will sample every word once every M*N clock cycles. Since an engineer has control of the values of M and N the engineer will also know the appropriate output sequence of words to expect and can test appropriately.
  • Undersampling digital testability circuit 20 advantageously overcomes the limitations of prior art. Circuit 20, by operating as a digital test circuit, eliminates the need for digitizing of analog voltage waveforms thus providing a significant decrease in test time from approximately 300 mS per DAC to approximately 1 mS per DAC. Further, circuit 20 provides diagnostic capability by identifying which bit is in error when failures are detected which is a significant advantage over the prior art digitizing solution and the prior art cyclic redundancy check solution which both fail to provide any detailed information regarding which bit or bits failed when failures are detected.
  • An alternative embodiment of the invention may include the use of a programmable counter instead of counter 18.
  • Programmable counters are well known by those skilled in the art of circuit design, such as the 8253 programmable counter provided by Intel Corp.
  • the programmable counter may then be configured appropriately by internal signals which will be driven by software.
  • Programmable counter would preferably be integrated onto video circuit 30, but could be placed externally on a test board if desired.
  • a programmable counter in circuit 20 would allow a test engineer greater flexibility in the design of tests for video circuit 30.
  • a further alternative would be any form of divider type circuit that would effectively produce an output signal that has a frequency that is a sub-multiple of its input signal.
  • register array 22 may also be composed of different types of flip flops or various type registers. Even latches could be used in register array 22. Any form of data capturing element would be an effective alternative in circuit 20.
  • circuit 20, although highly effective in testing high speed data transfers in video driver circuit 30, is not limited to this application. Rather, circuit 20 may advantageously be used to test any high speed data transfer such as data transfers in microprocessors or digital signal processors. The invention may also be incorporated at the system level to aid in testing electronic assemblies with remote ATE on diagnostic equipment.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
US08/096,149 1993-07-22 1993-07-22 Undersampling digital testability circuit Expired - Lifetime US5825786A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US08/096,149 US5825786A (en) 1993-07-22 1993-07-22 Undersampling digital testability circuit
DE69419292T DE69419292T2 (de) 1993-07-22 1994-07-22 Stichprobenschaltung
JP6201238A JPH07167926A (ja) 1993-07-22 1994-07-22 アンダーサンプリング・ディジタル試験装置および方法
EP94305436A EP0642085B1 (en) 1993-07-22 1994-07-22 Sampling circuit

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US08/096,149 US5825786A (en) 1993-07-22 1993-07-22 Undersampling digital testability circuit

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EP (1) EP0642085B1 (ja)
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324485B1 (en) 1999-01-26 2001-11-27 Newmillennia Solutions, Inc. Application specific automated test equipment system for testing integrated circuit devices in a native environment
US6492798B2 (en) 2001-04-27 2002-12-10 Logicvision, Inc. Method and circuit for testing high frequency mixed signal circuits with low frequency signals
US20080222180A1 (en) * 2001-03-13 2008-09-11 Hyung Bun Kim Recording medium containing sample data and reproducing thereof
US10014070B2 (en) 2013-01-14 2018-07-03 Micron Technology, Inc. Data path integrity verification in memory devices
CN113315532A (zh) * 2021-05-28 2021-08-27 成都谐盈科技有限公司 一种任意速率遥测信号的自适应接收装置及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0202865A2 (en) * 1985-05-17 1986-11-26 Honeywell Inc. Testable video display generator
US5196834A (en) * 1989-12-19 1993-03-23 Analog Devices, Inc. Dynamic palette loading opcode system for pixel based display
US5277863A (en) * 1993-02-26 1994-01-11 The United States Of America As Represented By The Secretary Of The Army Method of preparing non-composite, thermoplastic, high-temperature-resistant rocket motor cases
US5287100A (en) * 1990-06-27 1994-02-15 Texas Instruments Incorporated Graphics systems, palettes and methods with combined video and shift clock control
US5293468A (en) * 1990-06-27 1994-03-08 Texas Instruments Incorporated Controlled delay devices, systems and methods
US5309551A (en) * 1990-06-27 1994-05-03 Texas Instruments Incorporated Devices, systems and methods for palette pass-through mode

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IE904102A1 (en) * 1990-11-14 1992-05-20 Elverex Ltd A screen capture circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0202865A2 (en) * 1985-05-17 1986-11-26 Honeywell Inc. Testable video display generator
US5196834A (en) * 1989-12-19 1993-03-23 Analog Devices, Inc. Dynamic palette loading opcode system for pixel based display
US5287100A (en) * 1990-06-27 1994-02-15 Texas Instruments Incorporated Graphics systems, palettes and methods with combined video and shift clock control
US5293468A (en) * 1990-06-27 1994-03-08 Texas Instruments Incorporated Controlled delay devices, systems and methods
US5309551A (en) * 1990-06-27 1994-05-03 Texas Instruments Incorporated Devices, systems and methods for palette pass-through mode
US5277863A (en) * 1993-02-26 1994-01-11 The United States Of America As Represented By The Secretary Of The Army Method of preparing non-composite, thermoplastic, high-temperature-resistant rocket motor cases

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Chasters A 1 Micron CMOS 128 MHZ video serialiser Palette, and Digital to Analogue (DAC) chip IEEE 1989 p. 117. *
Chasters A 1-Micron CMOS 128 MHZ video serialiser Palette, and Digital to Analogue (DAC) chip IEEE 1989 p. 117.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324485B1 (en) 1999-01-26 2001-11-27 Newmillennia Solutions, Inc. Application specific automated test equipment system for testing integrated circuit devices in a native environment
US20080222180A1 (en) * 2001-03-13 2008-09-11 Hyung Bun Kim Recording medium containing sample data and reproducing thereof
US6492798B2 (en) 2001-04-27 2002-12-10 Logicvision, Inc. Method and circuit for testing high frequency mixed signal circuits with low frequency signals
US6703820B2 (en) 2001-04-27 2004-03-09 Logicvision, Inc. Method and circuit for testing high frequency mixed signal circuits with low frequency signals
US10014070B2 (en) 2013-01-14 2018-07-03 Micron Technology, Inc. Data path integrity verification in memory devices
US10622084B2 (en) 2013-01-14 2020-04-14 Micron Technology, Inc. Methods of verifying data path integrity
US11238949B2 (en) 2013-01-14 2022-02-01 Micron Technology, Inc. Memory devices configured to test data path integrity
CN113315532A (zh) * 2021-05-28 2021-08-27 成都谐盈科技有限公司 一种任意速率遥测信号的自适应接收装置及方法

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Publication number Publication date
EP0642085A1 (en) 1995-03-08
JPH07167926A (ja) 1995-07-04
DE69419292T2 (de) 1999-11-04
DE69419292D1 (de) 1999-08-05
EP0642085B1 (en) 1999-06-30

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