US5645683A - Etching method for etching a semiconductor substrate having a silicide layer and a polysilicon layer - Google Patents
Etching method for etching a semiconductor substrate having a silicide layer and a polysilicon layer Download PDFInfo
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- US5645683A US5645683A US08/385,124 US38512495A US5645683A US 5645683 A US5645683 A US 5645683A US 38512495 A US38512495 A US 38512495A US 5645683 A US5645683 A US 5645683A
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- etching
- polysilicon layer
- layer
- temperature
- semiconductor substrate
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- 238000005530 etching Methods 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 57
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 57
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 24
- 239000002826 coolant Substances 0.000 claims abstract description 16
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 239000007789 gas Substances 0.000 claims description 35
- 238000001816 cooling Methods 0.000 claims description 7
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical group [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 description 10
- 230000003068 static effect Effects 0.000 description 10
- 238000000295 emission spectrum Methods 0.000 description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 7
- 239000000460 chlorine Substances 0.000 description 7
- 229910052801 chlorine Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000498 cooling water Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
- H01J2237/2001—Maintaining constant desired temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
Definitions
- This invention relates to an etching method for etching a semiconductor substrate having a polysilicon layer and a silicide layer on the polysilicon layer.
- a semiconductor device which comprises a semiconductor substrate having a polysilicon layer and a silicide layer on the polysilicon layer.
- the silicide layer and the polysilicon layer will collectively be called a polycide layer.
- the polycide layer may be etched into a gate electrode by etching. It is necessary to etch the polycide layer into the gate electrode at high accuracy when the semiconductor device is an LSI.
- a conventional etching method is disclosed in Japanese Unexamined Publication Tokkai Hei 3-127826 (127826/1991) which was published on May 30, 1991.
- Plasma etching is used in the conventional etching method.
- the silicide layer is etched into a patterned silicide layer by an etching plasma.
- the etching plasma may be composed of chloride and hydrogen bromide.
- the polysilicon layer is etched into a patterned polysilicon layer by an etching gas by using an oxide film as a second etching mask. Hydrogen bromide may be used as the etching gas.
- the first etching mask is different in material from the second etching mask in the conventional etching method. Namely, it is necessary to use at least two etching masks on etching the polycide layer in the conventional etching method. In addition, it is necessary to remove the first etching mask after etching the silicide layer into the patterned silicide layer.
- an etching method for etching a semiconductor substrate having a polysilicon layer and a silicide layer on the polysilicon layer by plasma etching to produce a processed semiconductor substrate having a patterned polysilicon layer and a patterned silicide layer on the patterned polysilicon layer.
- the etching method comprises the steps of locating the semiconductor substrate on a supporting member of which temperature is controlled to a predetermined temperature, etching the silicide layer into the patterned silicide layer by the plasma etching, cooling the supporting member, and etching the polysilicon layer into the patterned polysilicon layer by the plasma etching to produce the processed semiconductor substrate.
- FIG. 1 is a block diagram illustrating an example of an etching apparatus for use in an etching method according to a preferred embodiment of this invention
- FIGS. 2a-2d depicts a signal view for describing an etching operation of the etching apparatus illustrated in FIG. 1;
- FIG. 3A is a sectional view illustrating a WSi layer and a polysilicon layer before etching the WSi layer;
- FIG. 3B is a sectional view illustrating a patterned WSi layer and the polysilicon layer after etching the WSi layer;
- FIG. 4 is a diagram for describing a relationship between a temperature of a semiconductor wafer and an etching rate ratio on etching a WSi layer by a gas including chlorine;
- FIG. 5 is a block diagram illustrating another example of an etching apparatus for use in the etching method according to the preferred embodiment of this invention.
- FIGS. 6a-6d depict a signal view for describing an etching operation of the etching apparatus illustrated in FIG. 5.
- the etching method is for etching a semiconductor substrate having a polysilicon layer and a silicide layer on the polysilicon layer by plasma etching to produce a processed semiconductor substrate having a patterned silicide layer and patterned polysilicon layer.
- the illustrated etching apparatus is for use in carrying out the etching method.
- the etching apparatus comprises a sealed metal chamber 11.
- a supporting electrode 12 is located on an inner wall of the sealed chamber 11.
- the supporting electrode 12 may be called a lower electrode.
- the lower electrode 12 is supplied with a high-frequency power from a high-frequency power source 13 through a high-frequency matching section 14 as will later be described.
- the lower electrode 12 has a cooling path 12a through which a cooling water passes.
- the cooling path 12a is connected to a temperature control section 15. Namely, the cooling path 12a is formed in the lower electrode 12 and is supplied with the cooling water from the temperature control section 15.
- the temperature control section 15 makes the temperature of the cooling water be a predetermined temperature. As a result, the temperature of the lower electrode 12 is controlled into the predetermined temperature by the temperature control section 15.
- First and second clamping plates 16a and 16b are positioned above the lower electrode 12 in the sealed chamber 11.
- the first clamping plate 16a and the second clamping plate 16b stand opposite to each other separated by a predetermined distance.
- the first and the second clamping plates 16a and 16b are connected to first and second plate driving sections 17a and 17b through first and second rods 171 and 172, respectively.
- the first and the second clamping plates 16a and 16b are synchronously driven upwardly and downwardly of FIG. 1 by the first and the second plate driving sections 17a and 17b, respectively.
- a ring-shaped plate may be used instead of the first and the second clamping plates 16a and 16b.
- the ring-shaped plate is supported by a cylindrical member which is connected to a driving section.
- the driving section may be one of the first and the second plate driving sections 17a and 17b.
- a semiconductor wafer 18 is located on the lower electrode 12 during etching the semiconductor wafer 18.
- the semiconductor wafer 18 has a polysilicon layer (not shown) and the silicide layer (not shown) on the polysilicon layer.
- the semiconductor wafer 18 may be clamping by the first and the second clamping plates 16a and 16b to be in close contact with the lower electrode 12. More particularly, the semiconductor wafer 18 may be pushed downwardly of FIG. 1 by the first and the second clamping plates 16a and 16b to be in close contact with the lower electrode 12.
- a gas path 12b is formed in the lower electrode 12.
- the gas path 12b reaches to an upper surface of the lower electrode 12 as shown in FIG. 1.
- the gas path 12b is given a coolant gas by a pressure control section 19 which is connected to a coolant gas source (not shown).
- the coolant gas may be, for example, helium gas.
- a monochromator 20 is attached on the side wall of the sealed chamber 11 so as to reach in the sealed chamber 11.
- the monochromator 20 is for monitoring an emission spectrum emitted from the semiconductor wafer 18 on etching to produce a monitored emission spectrum.
- the monochromator 20 is connected to a detecting section 21 which detects whether or not the etching of the semiconductor wafer 18 ends in accordance with the monitored emission spectrum. More specifically, the detecting section 21 produces a first end signal when the detecting section 21 knows that the etching of the silicide layer ends in accordance with the monitored emission spectrum. Similarly, the detecting section 21 produces a second end signal when the detecting section 21 knows that the etching of the polysilicon layer ends in accordance with the monitored emission spectrum.
- the detecting section 21 is connected to a main control section 22 and supplies the first and the second end signals to the main control section 22. Supplied with any one of the first and the second end signals, the main control section 22 controls the high-frequency matching section 14, first and second plate driving sections 17a and 17b, and pressure control section 19 as will later be described.
- the silicide layer is a WSi layer and that a photoresist film is used as an etching mask.
- the semiconductor wafer 18 is located on the lower electrode 12. At that time, a slight clearance inevitably exists between the semiconductor wafer 18 and the lower electrode 12.
- the temperature of the lower electrode 12 is controlled to 0° C. by the temperature control section 15.
- an etching gas is introduced into the sealed chamber 11 through an inlet port 11a.
- the etching gas is composed of chlorine and oxygen.
- the chlorine is introduced into the sealed chamber 11 with a flow rate of 30 sccm.
- the oxygen is introduced into the sealed chamber 11 with a flow rate of 2 sccm.
- the pressure of the sealed chamber 11 is kept at a pressure of 10 mTorr.
- the high-frequency matching section 14 supplies the lower electrode 12 with the high-frequency (HF) power of 300 watts under control of the main control section 22 as shown in a first row labelled (a) in FIG. 2.
- the WSi layer of the semiconductor wafer 18 is etched into a patterned WSi layer by the etching plasma.
- the polysilicon layer and the WSi layer are designated by reference numerals 31 and 32, respectively, in FIG. 3A.
- the photoresist mask is designated by a reference numeral 33 in FIG. 3A.
- the photoresist mask 33 has a first part 33a and a second part 33b.
- the first part 33a has a dense resist pattern.
- the second part 33b has a coarse resist pattern.
- the WSi layer 32 is etched by using the photoresist mask 33 as shown in FIG. 3A, the WSi layer 32 is etched into a patterned WSi layer 32a having a first etched pattern 321 and a second etched pattern 322 as shown in FIG. 3B.
- the first etched pattern 321 corresponds to the first part 33a.
- the second etched pattern 322 corresponds to the second part 33b.
- the first etched pattern 321 may have a first etched depth given by dA.
- the second etched pattern 322 may have a second etched depth given by dB.
- an etching rate ratio is defined by dA/dB. From FIG. 4, it is to be noted that the etching rate ratio decreases as the temperature of the semiconductor wafer 18 becomes lower and lower. As described above, the etching rate ratio is defined by dA/dB. Therefore, the first etched depth dA is greatly different from the second etched depth dB when the etching rate ratio decreases. Namely, the first etched depth dA is greatly different from the second etched depth dB when the temperature of the semiconductor wafer 18 is low. Accordingly, it is desirable to make the temperature of the semiconductor wafer 18 be high in order that the first etched depth dA is approximately equal to the second etched depth dB.
- the temperature of the semiconductor wafer 18 is heated to about 100° C. by the etching plasma when the WSi layer is etched while controlling the temperature of the lower electrode 12 to 0° C. as described above. More particularly, the semiconductor wafer 18 is not effectively chilled by the lower electrode 12 because of the slight clearance between the lower electrode 12 and the semiconductor wafer 18. When the temperature of the lower electrode 12 is 0° C., the temperature of the semiconductor wafer 18 is about 100° C.
- the monochromator 20 monitors the emission spectrum emitted from the semiconductor wafer 18 on etching.
- the monochromator 20 produces a monitored signal representative of the monitored emission spectrum. More specifically, the monochromator 20 produces a first monitored signal as the monitored signal on etching the WSi layer to supply the first monitored signal to the detecting section 21.
- the first monitored signal has a first monitored level.
- the first monitored level rises to a first balance level after the start of etching of the WSi layer. After some etching interval, the first monitored level drops.
- the detecting section 21 detects that the etching of the WSi layer ends. Namely, the detecting section 21 detects whether or not the etching of the WSi layer ends in accordance with the first monitored signal. When the detecting section 21 detects that the etching of the WSi layer ends, the detecting section 21 supplies the first end signal to the main control section 22. As shown at a third row labelled (c) in FIG. 2, the temperature of the semiconductor wafer 18 rises to about 100° C. as the etching of the WSi layer proceeds.
- the main control section 22 controls the high-frequency matching section 14 to make the high-frequency matching section 14 stop supplying the high-frequency power to the lower electrode 12 as shown at the first row (a) in FIG. 2. After that, the etching gas is exhausted from the sealed chamber 11 through an outlet port 11b.
- the main control section 22 controls the first and the second plate driving sections 17a and 17b so that the first and the second plate driving sections 17a and 17b drive the first and the second clamping plates 16a and 16b downwardly of FIG. 1, respectively.
- the semiconductor wafer 18 is pushed downwardly of FIG. 1 by the first and the second clamping plates 16a and 16b to be clamped at a predetermined clamping pressure as shown at a fourth row labelled (d) in FIG. 2.
- the semiconductor wafer 18 is in close contact with the lower electrode 12. Namely, the slight clearance does not exist between the semiconductor wafer 18 and the lower electrode 12.
- the main control section 22 controls the pressure control section 19 to make the pressure control section 19 supply the coolant gas to the sealed chamber 11 through the gas path 12b which is formed in the lower electrode 12.
- the semiconductor wafer 18 When the semiconductor wafer 18 is in close contact with the lower electrode 12 and the coolant gas is supplied to the sealed chamber 11 as described above, the semiconductor wafer 18 is effectively chilled by the lower electrode 12 so that the temperature of the semiconductor wafer 18 drops as shown at the third row (c) in FIG. 2.
- the etching gas is introduced into the sealed chamber 11 through the inlet port 11a.
- the chlorine is introduced into the sealed chamber 11 with a flow rate of 10 sccm.
- the oxygen is introduced into the sealed chamber 11 with a flow rate of 2 sccm.
- the pressure of the sealed chamber 11 is kept at a pressure of 5 mTorr.
- the main control section 22 controls the high-frequency matching section 14 so that the high-frequency matching section 14 supplies the lower electrode 12 with the high-frequency power of 150 watts as shown at the first row (a) in FIG. 2 in order to produce the etching plasma in the sealed chamber 11.
- the polysilicon layer of the semiconductor wafer 18 is etched into a patterned polysilicon layer by the etching plasma.
- the temperature of the semiconductor wafer 18 is about 20° C. during etching of the polysilicon layer because as the semiconductor wafer 18 is in close contact with the lower electrode 12 and the coolant gas is supplied to the sealed chamber 11 through the gas path 12b which is formed in the lower electrode 12.
- the monochromator 20 monitors the emission spectrum emitted from the semiconductor wafer 18 on etching. More particularly, the monochromator 20 produces a second monitored signal as the monitored signal on etching the polysilicon layer to supply the second monitored signal to the detecting section 21.
- the second monitored signal has a second monitored level.
- the second monitored level rises to a second balance level after the start of etching of the polysilicon layer. After some etching interval, the second monitored level drops.
- the detecting section 21 detects that the etching of the polysilicon layer ends. Namely, the detecting section 21 detects whether or not the etching of the polysilicon layer ends in accordance with the second monitored signal. When the detecting section 21 detects that the etching of the polysilicon layer ends, the detecting section 21 supplies the second end signal to the main control section 22.
- the main control section 22 controls the high-frequency matching section 14 so that the high-frequency matching section 14 stops supplying the high-frequency power to the lower electrode 12 as shown at the first row (a) in FIG. 2 after a predetermined time duration lapses.
- the etching gas is exhausted from the sealed chamber 11 through the outlet port 11b.
- the polysilicon layer is etched until the predetermined time duration lapses after the second end signal is supplied to the main control section 22. This etching may be called over-etching.
- the semiconductor wafer 18 becomes to a processed semiconductor wafer having the patterned WSi layer and the patterned polysilicon layer.
- the main control section 22 controls the pressure control section 19 to make the pressure control section 19 stop supplying the coolant gas to the sealed chamber 11 as shown at the third row (c) in FIG. 2.
- the main control section 22 controls the first and the second plate driving sections 17a and 17b so that the first and the second plate driving sections 17a and 17b drive the first and the second clamping plates 16a and 16b upwardly of FIG. 1, respectively.
- the processed semiconductor wafer is removed from clamping. The slight clearance exists between the processed semiconductor wafer and the lower electrode 12.
- the illustrated etching apparatus is different in structure from the etching apparatus 10 illustrated in FIG. 1 and therefore designated by a different reference numeral 40.
- the etching apparatus 40 comprises similar parts which are designated by like reference numerals and are operable with likewise named signals.
- the etching apparatus 40 comprises a static electricity supplying section 41 instead of the first and the second clamping plates 16a and 16b and the first and the second plate driving sections 17a and 17b all of which are illustrated in FIG. 1.
- the static electricity supplying section 41 is for supplying static electricity to the lower electrode 12 under control of the main control section 22.
- the temperature of the lower electrode 12 is controlled to 0° C. by the temperature control section 15.
- the etching gas composed of chlorine and oxygen is introduced into the sealed chamber 11 through the inlet port 11a.
- chlorine is introduced into the sealed chamber 11 with the flow rate of 30 sccm.
- Oxygen is introduced into the sealed chamber 11 with the flow rate of 2 sccm.
- the pressure of a sealed chamber 11 is kept at the pressure of 10 mTorr.
- the high-frequency matching section 14 supplies the lower electrode 12 with the high-frequency power of 300 watts under control of the main control section 22 as shown by a solid line at a first row labelled (a) in FIG. 6.
- the WSi layer of the semiconductor wafer 18 is etched into the patterned WSi layer by the etching plasma.
- the monochromator 20 monitors the emission spectrum emitted from the semiconductor wafer 18 on etching.
- the monochromator 20 produces the first monitored signal on etching the WSi layer to supply the first monitored signal to the detecting section 21 as shown at a second row labelled (b) in FIG. 6.
- the temperature of the semiconductor wafer 18 rises to about 100° C. as the etching of the WSi layer proceeds.
- the detecting section 21 detects that the etching of the WSi layer ends.
- the detecting section 21 detects that the etching of the WSi layer ends, the detecting section 21 supplies the first end signal to the main control section 22.
- the main control section 22 controls the high-frequency matching section 14 to make the high-frequency matching section 14 stop supplying the high-frequency power to the lower electrode 12 as shown by the solid line at the first row labelled (a) in FIG. 6. After that, the etching gas is exhausted from the sealed chamber 11 through an outlet port 11b.
- the main control section 22 controls the static electricity supplying section 41 to make the static electricity supplying section 41 supply static electricity to the lower electrode 12 as shown by a broken line at the first row (a) in FIG. 6. As a result, the semiconductor wafer 18 is in close contact with the lower electrode 12 by static electricity. As shown in a fourth row labelled (d) in FIG. 6, the main control section 22 controls the pressure control section 19 so that the pressure control section 22 supplies the coolant gas to the sealed chamber 11 through the gas path 12b which is formed in the lower electrode 12.
- the semiconductor wafer 18 When the semiconductor wafer 18 is in close contact with the lower electrode 12 and the coolant gas is supplied to the sealed chamber 11 as described above, the semiconductor wafer 18 is effectively chilled by the lower electrode 12 so that the temperature of the semiconductor wafer 18 drops as shown by the third row (c) in FIG. 6.
- the etching gas is introduced into the sealed chamber 11 through the inlet port 11a.
- chlorine is introduced into the sealed chamber 11 with a flow rate of 10 sccm.
- Oxygen is introduced into the sealed chamber 11 with a flow rate of 2 sccm.
- the pressure of the sealed chamber 11 is kept at a pressure of 5 mTorr.
- the main control section 22 controls the high-frequency matching section 14 so that the high-frequency matching section 14 supplies the lower electrode 12 with the high-frequency power of 150 watts as shown by a solid line at the first row (a) in FIG. 6 in order to produce the etching plasma in the sealed chamber 11.
- the polysilicon layer of the semiconductor wafer 18 is etched into a patterned polysilicon layer by the etching plasma.
- the monochromator 20 produces the second monitored signal on etching the polysilicon layer to supply the second monitored signal to the detecting section 21 as shown at the second row (b) in FIG. 6.
- the detecting section 21 detects that the etching of the polysilicon layer ends.
- the detecting section 21 supplies the second end signal to the main control section 22.
- the main control section 22 controls the static electricity supplying section 41 so that the static electricity supplying section 41 stops supplying static electricity to the lower electrode 12 immediately before the predetermined time duration lapses as shown by the broken line at the first row (a) in FIG. 6.
- the main control section 22 controls the high-frequency matching section 14 so that the high-frequency matching section 14 stops supplying the high-frequency power to the lower electrode 12 as shown by the solid line at the first row (a) in FIG. 6 after the predetermined time duration lapses.
- the etching gas is exhausted from the sealed chamber 11 through the outlet port 11b.
- the polysilicon layer is etched until the predetermined time duration lapses after the second end signal is supplied to the main control section 22. Furthermore, the main control section 22 controls the pressure control section 19 so that the pressure control section 19 stops supplying the coolant gas to the sealed chamber 11 as shown at the fourth row (d) in FIG. 6.
- the polysilicon layer is etched into the patterned polysilicon layer under a low temperature as described above, it is possible to obtain the processed semiconductor wafer having a good etched form.
- the temperature control section 15 controls the temperature of the lower electrode 12 to the predetermined temperature.
- the predetermined temperature is controlled to 0° C. by the temperature control section 15 in order that the temperature of the semiconductor wafer 18 is controlled to about 100° C. during of etching the WSi layer and the temperature of the semiconductor wafer 18 is controlled to about 20° C. on etching the polysilicon layer.
- the processed semiconductor wafer having the good etched form when the silicide layer is etched at a high temperature and the polysilicon layer is etched at a lower temperature. According to a test, it is possible to obtain the processed semiconductor wafer having the good etched form when the predetermined temperature is a temperature between -30° C. and 0° C., inclusive.
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP6-013315 | 1994-02-07 | ||
JP6013315A JPH07221076A (ja) | 1994-02-07 | 1994-02-07 | エッチング方法及びこれに用いられる装置 |
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US5645683A true US5645683A (en) | 1997-07-08 |
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US08/385,124 Expired - Lifetime US5645683A (en) | 1994-02-07 | 1995-02-07 | Etching method for etching a semiconductor substrate having a silicide layer and a polysilicon layer |
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US (1) | US5645683A (ja) |
JP (1) | JPH07221076A (ja) |
KR (1) | KR0184934B1 (ja) |
GB (1) | GB2286802B (ja) |
Cited By (9)
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US5951879A (en) * | 1995-04-14 | 1999-09-14 | Matsushita Electronics Corporation | Method of etching polysilicon layer |
WO2001041189A2 (en) * | 1999-12-03 | 2001-06-07 | Tegal Corporation | Cobalt silicide etch process and apparatus |
US6424043B1 (en) | 1997-03-13 | 2002-07-23 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
US20050082278A1 (en) * | 2002-03-15 | 2005-04-21 | Boris Atlas | Semiconductor processing temperature control |
US7217652B1 (en) * | 2000-09-21 | 2007-05-15 | Spansion Llc | Method of forming highly conductive semiconductor structures via plasma etch |
US20070138136A1 (en) * | 2005-12-16 | 2007-06-21 | Jason Plumhoff | Method for etching photolithographic substrates |
USRE40264E1 (en) | 1995-12-04 | 2008-04-29 | Flamm Daniel L | Multi-temperature processing |
US20080147229A1 (en) * | 2005-01-18 | 2008-06-19 | Point 35 Microstructures Limited | Method And Apparatus For Monitoring A Microstructure Etching Process |
US8410393B2 (en) | 2010-05-24 | 2013-04-02 | Lam Research Corporation | Apparatus and method for temperature control of a semiconductor substrate support |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19706783A1 (de) * | 1997-02-20 | 1998-08-27 | Siemens Ag | Verfahren zur Herstellung dotierter Polysiliciumschichten und -schichtstrukturen und Verfahren zum Strukturieren von Schichten und Schichtstrukturen, welche Polysiliciumschichten umfassen |
US6479373B2 (en) | 1997-02-20 | 2002-11-12 | Infineon Technologies Ag | Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases |
JP4740599B2 (ja) * | 2005-01-07 | 2011-08-03 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
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JPH0629262A (ja) * | 1991-08-05 | 1994-02-04 | Fuji Electric Co Ltd | プラズマエッチング方法 |
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- 1995-02-07 GB GB9502363A patent/GB2286802B/en not_active Expired - Fee Related
- 1995-02-07 US US08/385,124 patent/US5645683A/en not_active Expired - Lifetime
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JPH04142737A (ja) * | 1990-10-04 | 1992-05-15 | Sony Corp | ドライエッチング方法 |
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Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
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US5951879A (en) * | 1995-04-14 | 1999-09-14 | Matsushita Electronics Corporation | Method of etching polysilicon layer |
USRE40264E1 (en) | 1995-12-04 | 2008-04-29 | Flamm Daniel L | Multi-temperature processing |
US6583002B2 (en) | 1997-03-13 | 2003-06-24 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
US6653187B2 (en) | 1997-03-13 | 2003-11-25 | Micron Technology, Inc. | Semiconductor processing methods |
US6611018B2 (en) | 1997-03-13 | 2003-08-26 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
US6424043B1 (en) | 1997-03-13 | 2002-07-23 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
US6495410B2 (en) * | 1997-03-13 | 2002-12-17 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
US6486069B1 (en) * | 1999-12-03 | 2002-11-26 | Tegal Corporation | Cobalt silicide etch process and apparatus |
US6391148B2 (en) * | 1999-12-03 | 2002-05-21 | Tegal Corporation | Cobalt silicide etch process and apparatus |
WO2001041189A3 (en) * | 1999-12-03 | 2001-10-25 | Tegal Corp | Cobalt silicide etch process and apparatus |
WO2001041189A2 (en) * | 1999-12-03 | 2001-06-07 | Tegal Corporation | Cobalt silicide etch process and apparatus |
US7217652B1 (en) * | 2000-09-21 | 2007-05-15 | Spansion Llc | Method of forming highly conductive semiconductor structures via plasma etch |
US20050082278A1 (en) * | 2002-03-15 | 2005-04-21 | Boris Atlas | Semiconductor processing temperature control |
US7180036B2 (en) * | 2002-03-15 | 2007-02-20 | Oriol, Inc. | Semiconductor processing temperature control |
US20070051818A1 (en) * | 2002-03-15 | 2007-03-08 | Boris Atlas | Semiconductor processing temperature control |
US20080147229A1 (en) * | 2005-01-18 | 2008-06-19 | Point 35 Microstructures Limited | Method And Apparatus For Monitoring A Microstructure Etching Process |
US7672750B2 (en) * | 2005-01-18 | 2010-03-02 | Point 35 Microstructures Ltd. | Method and apparatus for monitoring a microstructure etching process |
US20070138136A1 (en) * | 2005-12-16 | 2007-06-21 | Jason Plumhoff | Method for etching photolithographic substrates |
US7749400B2 (en) | 2005-12-16 | 2010-07-06 | Jason Plumhoff | Method for etching photolithographic substrates |
US8410393B2 (en) | 2010-05-24 | 2013-04-02 | Lam Research Corporation | Apparatus and method for temperature control of a semiconductor substrate support |
Also Published As
Publication number | Publication date |
---|---|
GB2286802B (en) | 1997-06-11 |
KR950025893A (ko) | 1995-09-18 |
KR0184934B1 (ko) | 1999-04-15 |
GB2286802A (en) | 1995-08-30 |
JPH07221076A (ja) | 1995-08-18 |
GB9502363D0 (en) | 1995-03-29 |
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